include/configs/M5253EVBE.h

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * Hayden Fraser (Hayden.Fraser@freescale.com)
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _M5253EVBE_H
   9 #define _M5253EVBE_H
  10
  11 #define CONFIG_MCF52x2          /* define processor family */
  12 #define CONFIG_M5253            /* define processor type */
  13 #define CONFIG_M5253EVBE        /* define board type */
  14
  15 #define CONFIG_MCFTMR
  16
  17 #define CONFIG_MCFUART
  18 #define CONFIG_SYS_UART_PORT            (0)
  19 #define CONFIG_BAUDRATE         115200
  20
  21 #undef CONFIG_WATCHDOG          /* disable watchdog */
  22
  23 #define CONFIG_BOOTDELAY        5
  24
  25 /* Configuration for environment
  26  * Environment is embedded in u-boot in the second sector of the flash
  27  */
  28 #ifndef CONFIG_MONITOR_IS_IN_RAM
  29 #define CONFIG_ENV_OFFSET               0x4000
  30 #define CONFIG_ENV_SECT_SIZE    0x2000
  31 #define CONFIG_ENV_IS_IN_FLASH  1
  32 #else
  33 #define CONFIG_ENV_ADDR         0xffe04000
  34 #define CONFIG_ENV_SECT_SIZE    0x2000
  35 #define CONFIG_ENV_IS_IN_FLASH  1
  36 #endif
  37
  38 /*
  39  * BOOTP options
  40  */
  41 #undef CONFIG_BOOTP_BOOTFILESIZE
  42 #undef CONFIG_BOOTP_BOOTPATH
  43 #undef CONFIG_BOOTP_GATEWAY
  44 #undef CONFIG_BOOTP_HOSTNAME
  45
  46 /*
  47  * Command line configuration.
  48  */
  49 #include <config_cmd_default.h>
  50 #define CONFIG_CMD_CACHE
  51 #undef CONFIG_CMD_NET
  52 #define CONFIG_CMD_LOADB
  53 #define CONFIG_CMD_LOADS
  54 #define CONFIG_CMD_EXT2
  55 #define CONFIG_CMD_FAT
  56 #define CONFIG_CMD_IDE
  57 #define CONFIG_CMD_MEMORY
  58 #define CONFIG_CMD_MISC
  59
  60 /* ATA */
  61 #define CONFIG_DOS_PARTITION
  62 #define CONFIG_MAC_PARTITION
  63 #define CONFIG_IDE_RESET        1
  64 #define CONFIG_IDE_PREINIT      1
  65 #define CONFIG_ATAPI
  66 #undef CONFIG_LBA48
  67
  68 #define CONFIG_SYS_IDE_MAXBUS           1
  69 #define CONFIG_SYS_IDE_MAXDEVICE        2
  70
  71 #define CONFIG_SYS_ATA_BASE_ADDR        (CONFIG_SYS_MBAR2 + 0x800)
  72 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
  73
  74 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O */
  75 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
  76 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers */
  77 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers */
  78
  79 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
  80
  81 #if defined(CONFIG_CMD_KGDB)
  82 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
  83 #else
  84 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
  85 #endif
  86 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
  87 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
  88 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
  89
  90 #define CONFIG_SYS_LOAD_ADDR            0x00100000
  91
  92 #define CONFIG_SYS_MEMTEST_START        0x400
  93 #define CONFIG_SYS_MEMTEST_END          0x380000
  94
  95 #undef CONFIG_SYS_PLL_BYPASS            /* bypass PLL for test purpose */
  96 #define CONFIG_SYS_FAST_CLK
  97 #ifdef CONFIG_SYS_FAST_CLK
  98 #       define CONFIG_SYS_PLLCR 0x1243E054
  99 #       define CONFIG_SYS_CLK           140000000
 100 #else
 101 #       define CONFIG_SYS_PLLCR 0x135a4140
 102 #       define CONFIG_SYS_CLK           70000000
 103 #endif
 104
 105 /*
 106  * Low Level Configuration Settings
 107  * (address mappings, register initial values, etc.)
 108  * You should know what you are doing if you make changes here.
 109  */
 110
 111 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
 112 #define CONFIG_SYS_MBAR2                0x80000000      /* Module Base Addrs 2 */
 113
 114 /*
 115  * Definitions for initial stack pointer and data area (in DPRAM)
 116  */
 117 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 118 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 119 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 120 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 121
 122 /*
 123  * Start addresses for the final memory configuration
 124  * (Set up by the startup code)
 125  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 126  */
 127 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 128 #define CONFIG_SYS_SDRAM_SIZE           8       /* SDRAM size in MB */
 129
 130 #ifdef CONFIG_MONITOR_IS_IN_RAM
 131 #define CONFIG_SYS_MONITOR_BASE 0x20000
 132 #else
 133 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 134 #endif
 135
 136 #define CONFIG_SYS_MONITOR_LEN          0x40000
 137 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 138 #define CONFIG_SYS_BOOTPARAMS_LEN       (64*1024)
 139
 140 /*
 141  * For booting Linux, the board info and command line data
 142  * have to be in the first 8 MB of memory, since this is
 143  * the maximum mapped by the Linux kernel during initialization ??
 144  */
 145 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 146 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 147
 148 /* FLASH organization */
 149 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 150 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 151 #define CONFIG_SYS_MAX_FLASH_SECT       35      /* max number of sectors on one chip */
 152 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 153
 154 #define CONFIG_SYS_FLASH_CFI            1
 155 #define CONFIG_FLASH_CFI_DRIVER 1
 156 #define CONFIG_SYS_FLASH_SIZE           0x200000
 157 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 158
 159 /* Cache Configuration */
 160 #define CONFIG_SYS_CACHELINE_SIZE       16
 161
 162 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 163                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 164 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 165                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 166 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 167 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
 168                                          CF_ADDRMASK(2) | \
 169                                          CF_ACR_EN | CF_ACR_SM_ALL)
 170 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
 171                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 172                                          CF_ACR_EN | CF_ACR_SM_ALL)
 173 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 174                                          CF_CACR_DBWE)
 175
 176 /* Port configuration */
 177 #define CONFIG_SYS_FECI2C               0xF0
 178
 179 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 180 #define CONFIG_SYS_CS0_MASK             0x001F0021
 181 #define CONFIG_SYS_CS0_CTRL             0x00001D80
 182
 183 /*-----------------------------------------------------------------------
 184  * Port configuration
 185  */
 186 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none */
 187 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 188 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable */
 189 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable */
 190 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 191 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 192 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led */
 193
 194 #endif                          /* _M5253EVB_H */