include/configs/M5253EVBE.h

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * Hayden Fraser (Hayden.Fraser@freescale.com)
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _M5253EVBE_H
   9 #define _M5253EVBE_H
  10
  11 #define CONFIG_M5253EVBE        /* define board type */
  12
  13 #define CONFIG_MCFTMR
  14
  15 #define CONFIG_MCFUART
  16 #define CONFIG_SYS_UART_PORT            (0)
  17 #define CONFIG_BAUDRATE         115200
  18
  19 #undef CONFIG_WATCHDOG          /* disable watchdog */
  20
  21 #define CONFIG_BOOTDELAY        5
  22
  23 /* Configuration for environment
  24  * Environment is embedded in u-boot in the second sector of the flash
  25  */
  26 #ifndef CONFIG_MONITOR_IS_IN_RAM
  27 #define CONFIG_ENV_OFFSET               0x4000
  28 #define CONFIG_ENV_SECT_SIZE    0x2000
  29 #define CONFIG_ENV_IS_IN_FLASH  1
  30 #else
  31 #define CONFIG_ENV_ADDR         0xffe04000
  32 #define CONFIG_ENV_SECT_SIZE    0x2000
  33 #define CONFIG_ENV_IS_IN_FLASH  1
  34 #endif
  35
  36 #define LDS_BOARD_TEXT \
  37         . = DEFINED(env_offset) ? env_offset : .; \
  38         common/env_embedded.o      (.text)
  39
  40
  41 /*
  42  * BOOTP options
  43  */
  44 #undef CONFIG_BOOTP_BOOTFILESIZE
  45 #undef CONFIG_BOOTP_BOOTPATH
  46 #undef CONFIG_BOOTP_GATEWAY
  47 #undef CONFIG_BOOTP_HOSTNAME
  48
  49 /*
  50  * Command line configuration.
  51  */
  52 #include <config_cmd_default.h>
  53 #define CONFIG_CMD_CACHE
  54 #undef CONFIG_CMD_NET
  55 #define CONFIG_CMD_LOADB
  56 #define CONFIG_CMD_LOADS
  57 #define CONFIG_CMD_EXT2
  58 #define CONFIG_CMD_FAT
  59 #define CONFIG_CMD_IDE
  60 #define CONFIG_CMD_MEMORY
  61 #define CONFIG_CMD_MISC
  62
  63 /* ATA */
  64 #define CONFIG_DOS_PARTITION
  65 #define CONFIG_MAC_PARTITION
  66 #define CONFIG_IDE_RESET        1
  67 #define CONFIG_IDE_PREINIT      1
  68 #define CONFIG_ATAPI
  69 #undef CONFIG_LBA48
  70
  71 #define CONFIG_SYS_IDE_MAXBUS           1
  72 #define CONFIG_SYS_IDE_MAXDEVICE        2
  73
  74 #define CONFIG_SYS_ATA_BASE_ADDR        (CONFIG_SYS_MBAR2 + 0x800)
  75 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
  76
  77 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O */
  78 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
  79 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers */
  80 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers */
  81
  82 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
  83
  84 #if defined(CONFIG_CMD_KGDB)
  85 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
  86 #else
  87 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
  88 #endif
  89 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
  90 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
  91 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
  92
  93 #define CONFIG_SYS_LOAD_ADDR            0x00100000
  94
  95 #define CONFIG_SYS_MEMTEST_START        0x400
  96 #define CONFIG_SYS_MEMTEST_END          0x380000
  97
  98 #undef CONFIG_SYS_PLL_BYPASS            /* bypass PLL for test purpose */
  99 #define CONFIG_SYS_FAST_CLK
 100 #ifdef CONFIG_SYS_FAST_CLK
 101 #       define CONFIG_SYS_PLLCR 0x1243E054
 102 #       define CONFIG_SYS_CLK           140000000
 103 #else
 104 #       define CONFIG_SYS_PLLCR 0x135a4140
 105 #       define CONFIG_SYS_CLK           70000000
 106 #endif
 107
 108 /*
 109  * Low Level Configuration Settings
 110  * (address mappings, register initial values, etc.)
 111  * You should know what you are doing if you make changes here.
 112  */
 113
 114 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
 115 #define CONFIG_SYS_MBAR2                0x80000000      /* Module Base Addrs 2 */
 116
 117 /*
 118  * Definitions for initial stack pointer and data area (in DPRAM)
 119  */
 120 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 121 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 122 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 123 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 124
 125 /*
 126  * Start addresses for the final memory configuration
 127  * (Set up by the startup code)
 128  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 129  */
 130 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 131 #define CONFIG_SYS_SDRAM_SIZE           8       /* SDRAM size in MB */
 132
 133 #ifdef CONFIG_MONITOR_IS_IN_RAM
 134 #define CONFIG_SYS_MONITOR_BASE 0x20000
 135 #else
 136 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 137 #endif
 138
 139 #define CONFIG_SYS_MONITOR_LEN          0x40000
 140 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 141 #define CONFIG_SYS_BOOTPARAMS_LEN       (64*1024)
 142
 143 /*
 144  * For booting Linux, the board info and command line data
 145  * have to be in the first 8 MB of memory, since this is
 146  * the maximum mapped by the Linux kernel during initialization ??
 147  */
 148 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 149 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 150
 151 /* FLASH organization */
 152 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 153 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 154 #define CONFIG_SYS_MAX_FLASH_SECT       35      /* max number of sectors on one chip */
 155 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 156
 157 #define CONFIG_SYS_FLASH_CFI            1
 158 #define CONFIG_FLASH_CFI_DRIVER 1
 159 #define CONFIG_SYS_FLASH_SIZE           0x200000
 160 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 161
 162 /* Cache Configuration */
 163 #define CONFIG_SYS_CACHELINE_SIZE       16
 164
 165 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 166                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 167 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 168                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 169 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 170 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
 171                                          CF_ADDRMASK(2) | \
 172                                          CF_ACR_EN | CF_ACR_SM_ALL)
 173 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
 174                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 175                                          CF_ACR_EN | CF_ACR_SM_ALL)
 176 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 177                                          CF_CACR_DBWE)
 178
 179 /* Port configuration */
 180 #define CONFIG_SYS_FECI2C               0xF0
 181
 182 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 183 #define CONFIG_SYS_CS0_MASK             0x001F0021
 184 #define CONFIG_SYS_CS0_CTRL             0x00001D80
 185
 186 /*-----------------------------------------------------------------------
 187  * Port configuration
 188  */
 189 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none */
 190 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 191 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable */
 192 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable */
 193 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 194 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 195 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led */
 196
 197 #endif                          /* _M5253EVB_H */