include/configs/M5271EVB.h

   1 /*
   2  * Configuation settings for the Freescale M5271EVB
   3  *
   4  * Based on MC5272C3 and r5200 board configs
   5  * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
   6  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * board/config.h - configuration options, board specific
  13  */
  14
  15 #ifndef _M5271EVB_H
  16 #define _M5271EVB_H
  17
  18 /*
  19  * High Level Configuration Options (easy to change)
  20  */
  21 #define CONFIG_MCF52x2          /* define processor family */
  22 #define CONFIG_M5271            /* define processor type */
  23 #define CONFIG_M5271EVB         /* define board type */
  24
  25 #define CONFIG_MCFTMR
  26
  27 #define CONFIG_MCFUART
  28 #define CONFIG_SYS_UART_PORT            (0)
  29 #define CONFIG_BAUDRATE         115200
  30
  31 #undef CONFIG_WATCHDOG          /* disable watchdog */
  32
  33 /* Configuration for environment
  34  * Environment is embedded in u-boot in the second sector of the flash
  35  */
  36 #ifndef CONFIG_MONITOR_IS_IN_RAM
  37 #define CONFIG_ENV_OFFSET               0x4000
  38 #else
  39 #define CONFIG_ENV_ADDR         0xffe04000
  40 #endif
  41 #define CONFIG_ENV_SECT_SIZE    0x2000
  42 #define CONFIG_ENV_IS_IN_FLASH  1
  43 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
  44
  45 /*
  46  * BOOTP options
  47  */
  48 #define CONFIG_BOOTP_BOOTFILESIZE
  49 #define CONFIG_BOOTP_BOOTPATH
  50 #define CONFIG_BOOTP_GATEWAY
  51 #define CONFIG_BOOTP_HOSTNAME
  52
  53 /*
  54  * Command line configuration.
  55  */
  56 #include <config_cmd_default.h>
  57
  58 #define CONFIG_CMD_CACHE
  59 #define CONFIG_CMD_PING
  60 #define CONFIG_CMD_NET
  61 #define CONFIG_CMD_MII
  62 #define CONFIG_CMD_ELF
  63 #define CONFIG_CMD_FLASH
  64 #define CONFIG_CMD_I2C
  65 #define CONFIG_CMD_MEMORY
  66 #define CONFIG_CMD_MISC
  67
  68 #undef CONFIG_CMD_LOADS
  69 #define CONFIG_CMD_LOADB
  70 #define CONFIG_CMDLINE_EDITING  1 /* enables command line history */
  71 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
  72
  73 #define CONFIG_MCFFEC
  74 #ifdef CONFIG_MCFFEC
  75 #       define CONFIG_MII               1
  76 #       define CONFIG_MII_INIT          1
  77 #       define CONFIG_SYS_DISCOVER_PHY
  78 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  79 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  80
  81 #       define CONFIG_SYS_FEC0_PINMUX           0
  82 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  83 #       define MCFFEC_TOUT_LOOP         50000
  84 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  85 #       ifndef CONFIG_SYS_DISCOVER_PHY
  86 #               define FECDUPLEX        FULL
  87 #               define FECSPEED         _100BASET
  88 #       else
  89 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  90 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  91 #               endif
  92 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  93 #endif
  94
  95 /* I2C */
  96 #define CONFIG_SYS_I2C
  97 #define CONFIG_SYS_I2C_FSL
  98 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  99 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 100 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
 101 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 102
 103 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 seconds */
 104 #define CONFIG_BOOTFILE         "u-boot.bin"
 105 #ifdef CONFIG_MCFFEC
 106 #       define CONFIG_NET_RETRY_COUNT   5
 107 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
 108 #       define CONFIG_IPADDR    192.162.1.2
 109 #       define CONFIG_NETMASK   255.255.255.0
 110 #       define CONFIG_SERVERIP  192.162.1.1
 111 #       define CONFIG_GATEWAYIP 192.162.1.1
 112 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 113 #endif                          /* FEC_ENET */
 114
 115 #define CONFIG_HOSTNAME         M5271EVB
 116 #define CONFIG_EXTRA_ENV_SETTINGS               \
 117         "netdev=eth0\0"                         \
 118         "loadaddr=10000\0"                      \
 119         "uboot=u-boot.bin\0"            \
 120         "load=tftp $loadaddr $uboot\0"  \
 121         "upd=run load; run prog\0"              \
 122         "prog=prot off ffe00000 ffe3ffff;"      \
 123         "era ffe00000 ffe3ffff;"                \
 124         "cp.b $loadaddr ffe00000 $filesize;"    \
 125         "save\0"                                \
 126         ""
 127
 128 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 129
 130 #if defined(CONFIG_CMD_KGDB)
 131 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 132 #else
 133 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 134 #endif
 135 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 136 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 137 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 138
 139 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 140
 141 #define CONFIG_SYS_MEMTEST_START        0x400
 142 #define CONFIG_SYS_MEMTEST_END          0x380000
 143
 144 #define CONFIG_SYS_HZ                   1000000
 145
 146 /* Clock configuration
 147  * The external oscillator is a 25.000 MHz
 148  * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
 149  * bus_clk = (cpu_clk/2) (fixed ratio)
 150  *
 151  * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
 152  * match the new clock speed. Max cpu_clk is 150 MHz.
 153  */
 154 #define CONFIG_SYS_CLK                  100000000
 155 #define CONFIG_SYS_MCF_SYNCR    (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
 156
 157 /*
 158  * Low Level Configuration Settings
 159  * (address mappings, register initial values, etc.)
 160  * You should know what you are doing if you make changes here.
 161  */
 162
 163 #define CONFIG_SYS_MBAR         0x40000000      /* Register Base Addrs */
 164
 165 /*
 166  * Definitions for initial stack pointer and data area (in DPRAM)
 167  */
 168 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 169 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in internal SRAM    */
 170 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 171 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 172
 173 /*
 174  * Start addresses for the final memory configuration
 175  * (Set up by the startup code)
 176  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 177  */
 178 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 179 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 180 #define CONFIG_SYS_FLASH_BASE           0xffe00000
 181
 182 #ifdef  CONFIG_MONITOR_IS_IN_RAM
 183 #define CONFIG_SYS_MONITOR_BASE 0x20000
 184 #else
 185 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 186 #endif
 187
 188 #define CONFIG_SYS_MONITOR_LEN          0x40000
 189 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 190 #define CONFIG_SYS_BOOTPARAMS_LEN       (64*1024)
 191
 192 /*
 193  * For booting Linux, the board info and command line data
 194  * have to be in the first 8 MB of memory, since this is
 195  * the maximum mapped by the Linux kernel during initialization ??
 196  */
 197 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 198
 199 /* FLASH organization */
 200 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 201 #define CONFIG_SYS_MAX_FLASH_SECT       11      /* max number of sectors on one chip    */
 202 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 203
 204 #define CONFIG_SYS_FLASH_CFI            1
 205 #define CONFIG_FLASH_CFI_DRIVER 1
 206 #define CONFIG_SYS_FLASH_SIZE           0x200000
 207
 208 /* Cache Configuration */
 209 #define CONFIG_SYS_CACHELINE_SIZE       16
 210
 211 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 212                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 213 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 214                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 215 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 216 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 217                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 218                                          CF_ACR_EN | CF_ACR_SM_ALL)
 219 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 220                                          CF_CACR_DISD | CF_CACR_INVI | \
 221                                          CF_CACR_CEIB | CF_CACR_DCM | \
 222                                          CF_CACR_EUSP)
 223
 224 /* Chip Select 0  : Boot Flash */
 225 #define CONFIG_SYS_CS0_BASE     0xFFE00000
 226 #define CONFIG_SYS_CS0_MASK     0x001F0001
 227 #define CONFIG_SYS_CS0_CTRL     0x00001980
 228
 229 /* Chip Select 1 : External SRAM */
 230 #define CONFIG_SYS_CS1_BASE     0x30000000
 231 #define CONFIG_SYS_CS1_MASK     0x00070001
 232 #define CONFIG_SYS_CS1_CTRL     0x00001900
 233
 234 #endif                          /* _M5271EVB_H */