include/configs/M5271EVB.h

   1 /*
   2  * Configuation settings for the Freescale M5271EVB
   3  *
   4  * Based on MC5272C3 and r5200 board configs
   5  * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
   6  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30
  31 #ifndef _M5271EVB_H
  32 #define _M5271EVB_H
  33
  34 /*
  35  * High Level Configuration Options (easy to change)
  36  */
  37 #define CONFIG_MCF52x2          /* define processor family */
  38 #define CONFIG_M5271            /* define processor type */
  39 #define CONFIG_M5271EVB         /* define board type */
  40
  41 #define CONFIG_MCFTMR
  42
  43 #define CONFIG_MCFUART
  44 #define CONFIG_SYS_UART_PORT            (0)
  45 #define CONFIG_BAUDRATE         115200
  46
  47 #undef CONFIG_WATCHDOG          /* disable watchdog */
  48
  49 /* Configuration for environment
  50  * Environment is embedded in u-boot in the second sector of the flash
  51  */
  52 #ifndef CONFIG_MONITOR_IS_IN_RAM
  53 #define CONFIG_ENV_OFFSET               0x4000
  54 #else
  55 #define CONFIG_ENV_ADDR         0xffe04000
  56 #endif
  57 #define CONFIG_ENV_SECT_SIZE    0x2000
  58 #define CONFIG_ENV_IS_IN_FLASH  1
  59 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
  60
  61 /*
  62  * BOOTP options
  63  */
  64 #define CONFIG_BOOTP_BOOTFILESIZE
  65 #define CONFIG_BOOTP_BOOTPATH
  66 #define CONFIG_BOOTP_GATEWAY
  67 #define CONFIG_BOOTP_HOSTNAME
  68
  69 /*
  70  * Command line configuration.
  71  */
  72 #include <config_cmd_default.h>
  73
  74 #define CONFIG_CMD_CACHE
  75 #define CONFIG_CMD_PING
  76 #define CONFIG_CMD_NET
  77 #define CONFIG_CMD_MII
  78 #define CONFIG_CMD_ELF
  79 #define CONFIG_CMD_FLASH
  80 #define CONFIG_CMD_I2C
  81 #define CONFIG_CMD_MEMORY
  82 #define CONFIG_CMD_MISC
  83
  84 #undef CONFIG_CMD_LOADS
  85 #define CONFIG_CMD_LOADB
  86 #define CONFIG_CMDLINE_EDITING  1 /* enables command line history */
  87 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
  88 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  89
  90 #define CONFIG_MCFFEC
  91 #ifdef CONFIG_MCFFEC
  92 #       define CONFIG_MII               1
  93 #       define CONFIG_MII_INIT          1
  94 #       define CONFIG_SYS_DISCOVER_PHY
  95 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  96 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  97
  98 #       define CONFIG_SYS_FEC0_PINMUX           0
  99 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
 100 #       define MCFFEC_TOUT_LOOP         50000
 101 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
 102 #       ifndef CONFIG_SYS_DISCOVER_PHY
 103 #               define FECDUPLEX        FULL
 104 #               define FECSPEED         _100BASET
 105 #       else
 106 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 107 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 108 #               endif
 109 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
 110 #endif
 111
 112 /* I2C */
 113 #define CONFIG_FSL_I2C
 114 #define CONFIG_HARD_I2C         /* I2C with hw support */
 115 #undef CONFIG_SOFT_I2C          /* I2C bit-banged */
 116 #define CONFIG_SYS_I2C_SPEED            80000
 117 #define CONFIG_SYS_I2C_SLAVE            0x7F
 118 #define CONFIG_SYS_I2C_OFFSET           0x00000300
 119 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 120
 121 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 seconds */
 122 #define CONFIG_BOOTFILE         "u-boot.bin"
 123 #ifdef CONFIG_MCFFEC
 124 #       define CONFIG_NET_RETRY_COUNT   5
 125 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
 126 #       define CONFIG_IPADDR    192.162.1.2
 127 #       define CONFIG_NETMASK   255.255.255.0
 128 #       define CONFIG_SERVERIP  192.162.1.1
 129 #       define CONFIG_GATEWAYIP 192.162.1.1
 130 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 131 #endif                          /* FEC_ENET */
 132
 133 #define CONFIG_HOSTNAME         M5271EVB
 134 #define CONFIG_EXTRA_ENV_SETTINGS               \
 135         "netdev=eth0\0"                         \
 136         "loadaddr=10000\0"                      \
 137         "uboot=u-boot.bin\0"            \
 138         "load=tftp $loadaddr $uboot\0"  \
 139         "upd=run load; run prog\0"              \
 140         "prog=prot off ffe00000 ffe3ffff;"      \
 141         "era ffe00000 ffe3ffff;"                \
 142         "cp.b $loadaddr ffe00000 $filesize;"    \
 143         "save\0"                                \
 144         ""
 145
 146 #define CONFIG_SYS_PROMPT               "=> "
 147 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 148
 149 #if defined(CONFIG_CMD_KGDB)
 150 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 151 #else
 152 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 153 #endif
 154 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 155 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 156 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 157
 158 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 159
 160 #define CONFIG_SYS_MEMTEST_START        0x400
 161 #define CONFIG_SYS_MEMTEST_END          0x380000
 162
 163 #define CONFIG_SYS_HZ                   1000000
 164
 165 /* Clock configuration
 166  * The external oscillator is a 25.000 MHz
 167  * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
 168  * bus_clk = (cpu_clk/2) (fixed ratio)
 169  *
 170  * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
 171  * match the new clock speed. Max cpu_clk is 150 MHz.
 172  */
 173 #define CONFIG_SYS_CLK                  100000000
 174 #define CONFIG_SYS_MCF_SYNCR    (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
 175
 176 /*
 177  * Low Level Configuration Settings
 178  * (address mappings, register initial values, etc.)
 179  * You should know what you are doing if you make changes here.
 180  */
 181
 182 #define CONFIG_SYS_MBAR         0x40000000      /* Register Base Addrs */
 183
 184 /*
 185  * Definitions for initial stack pointer and data area (in DPRAM)
 186  */
 187 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 188 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in internal SRAM    */
 189 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 190 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 191
 192 /*
 193  * Start addresses for the final memory configuration
 194  * (Set up by the startup code)
 195  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 196  */
 197 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 198 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 199 #define CONFIG_SYS_FLASH_BASE           0xffe00000
 200
 201 #ifdef  CONFIG_MONITOR_IS_IN_RAM
 202 #define CONFIG_SYS_MONITOR_BASE 0x20000
 203 #else
 204 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 205 #endif
 206
 207 #define CONFIG_SYS_MONITOR_LEN          0x40000
 208 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 209 #define CONFIG_SYS_BOOTPARAMS_LEN       (64*1024)
 210
 211 /*
 212  * For booting Linux, the board info and command line data
 213  * have to be in the first 8 MB of memory, since this is
 214  * the maximum mapped by the Linux kernel during initialization ??
 215  */
 216 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 217
 218 /* FLASH organization */
 219 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 220 #define CONFIG_SYS_MAX_FLASH_SECT       11      /* max number of sectors on one chip    */
 221 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 222
 223 #define CONFIG_SYS_FLASH_CFI            1
 224 #define CONFIG_FLASH_CFI_DRIVER 1
 225 #define CONFIG_SYS_FLASH_SIZE           0x200000
 226
 227 /* Cache Configuration */
 228 #define CONFIG_SYS_CACHELINE_SIZE       16
 229
 230 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 231                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 232 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 233                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 234 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 235 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 236                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 237                                          CF_ACR_EN | CF_ACR_SM_ALL)
 238 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 239                                          CF_CACR_DISD | CF_CACR_INVI | \
 240                                          CF_CACR_CEIB | CF_CACR_DCM | \
 241                                          CF_CACR_EUSP)
 242
 243 /* Chip Select 0  : Boot Flash */
 244 #define CONFIG_SYS_CS0_BASE     0xFFE00000
 245 #define CONFIG_SYS_CS0_MASK     0x001F0001
 246 #define CONFIG_SYS_CS0_CTRL     0x00001980
 247
 248 /* Chip Select 1 : External SRAM */
 249 #define CONFIG_SYS_CS1_BASE     0x30000000
 250 #define CONFIG_SYS_CS1_MASK     0x00070001
 251 #define CONFIG_SYS_CS1_CTRL     0x00001900
 252
 253 #endif                          /* _M5271EVB_H */