include/configs/M5282EVB.h

   1 /*
   2  * Configuation settings for the Motorola MC5282EVB board.
   3  *
   4  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config.h - configuration options, board specific
  27  */
  28
  29 #ifndef _CONFIG_M5282EVB_H
  30 #define _CONFIG_M5282EVB_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36 #define CONFIG_MCF52x2          /* define processor family */
  37 #define CONFIG_M5282            /* define processor type */
  38
  39 #define CONFIG_MCFTMR
  40
  41 #define CONFIG_MCFUART
  42 #define CFG_UART_PORT           (0)
  43 #define CONFIG_BAUDRATE 19200
  44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  45
  46 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  47
  48 /* Configuration for environment
  49  * Environment is embedded in u-boot in the second sector of the flash
  50  */
  51 #define CFG_ENV_ADDR            0xffe04000
  52 #define CFG_ENV_SIZE            0x2000
  53 #define CFG_ENV_IS_IN_FLASH     1
  54
  55 /*
  56  * BOOTP options
  57  */
  58 #define CONFIG_BOOTP_BOOTFILESIZE
  59 #define CONFIG_BOOTP_BOOTPATH
  60 #define CONFIG_BOOTP_GATEWAY
  61 #define CONFIG_BOOTP_HOSTNAME
  62
  63 /*
  64  * Command line configuration.
  65  */
  66 #include <config_cmd_default.h>
  67 #define CONFIG_CMD_NET
  68 #define CONFIG_CMD_PING
  69 #define CONFIG_CMD_MII
  70
  71 #undef CONFIG_CMD_LOADS
  72 #undef CONFIG_CMD_LOADB
  73
  74 #define CONFIG_MCFFEC
  75 #ifdef CONFIG_MCFFEC
  76 #       define CONFIG_NET_MULTI         1
  77 #       define CONFIG_MII               1
  78 #       define CFG_DISCOVER_PHY
  79 #       define CFG_RX_ETH_BUFFER        8
  80 #       define CFG_FAULT_ECHO_LINK_DOWN
  81
  82 #       define CFG_FEC0_PINMUX          0
  83 #       define CFG_FEC0_MIIBASE         CFG_FEC0_IOBASE
  84 #       define MCFFEC_TOUT_LOOP         50000
  85 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
  86 #       ifndef CFG_DISCOVER_PHY
  87 #               define FECDUPLEX        FULL
  88 #               define FECSPEED         _100BASET
  89 #       else
  90 #               ifndef CFG_FAULT_ECHO_LINK_DOWN
  91 #                       define CFG_FAULT_ECHO_LINK_DOWN
  92 #               endif
  93 #       endif                   /* CFG_DISCOVER_PHY */
  94 #endif
  95
  96 #define CONFIG_BOOTDELAY        5
  97 #ifdef CONFIG_MCFFEC
  98 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
  99 #       define CONFIG_IPADDR    192.162.1.2
 100 #       define CONFIG_NETMASK   255.255.255.0
 101 #       define CONFIG_SERVERIP  192.162.1.1
 102 #       define CONFIG_GATEWAYIP 192.162.1.1
 103 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 104 #endif                          /* CONFIG_MCFFEC */
 105
 106 #define CONFIG_HOSTNAME         M5272C3
 107 #define CONFIG_EXTRA_ENV_SETTINGS               \
 108         "netdev=eth0\0"                         \
 109         "loadaddr=10000\0"                      \
 110         "u-boot=u-boot.bin\0"                   \
 111         "load=tftp ${loadaddr) ${u-boot}\0"     \
 112         "upd=run load; run prog\0"              \
 113         "prog=prot off ffe00000 ffe3ffff;"      \
 114         "era ffe00000 ffe3ffff;"                \
 115         "cp.b ${loadaddr} ffe00000 ${filesize};"\
 116         "save\0"                                \
 117         ""
 118
 119 #define CFG_PROMPT              "-> "
 120 #define CFG_LONGHELP            /* undef to save memory         */
 121
 122 #if defined(CONFIG_CMD_KGDB)
 123 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 124 #else
 125 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 126 #endif
 127 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 128 #define CFG_MAXARGS             16      /* max number of command args   */
 129 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 130
 131 #define CFG_LOAD_ADDR           0x20000
 132
 133 #define CFG_MEMTEST_START       0x400
 134 #define CFG_MEMTEST_END         0x380000
 135
 136 #define CFG_HZ                  1000000
 137 #define CFG_CLK                 64000000
 138
 139 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
 140
 141 #define CFG_MFD                 0x02    /* PLL Multiplication Factor Devider */
 142 #define CFG_RFD                 0x00    /* PLL Reduce Frecuency Devider */
 143
 144 /*
 145  * Low Level Configuration Settings
 146  * (address mappings, register initial values, etc.)
 147  * You should know what you are doing if you make changes here.
 148  */
 149 #define CFG_MBAR                0x40000000
 150
 151 /*-----------------------------------------------------------------------
 152  * Definitions for initial stack pointer and data area (in DPRAM)
 153  */
 154 #define CFG_INIT_RAM_ADDR       0x20000000
 155 #define CFG_INIT_RAM_END        0x10000 /* End of used area in internal SRAM    */
 156 #define CFG_GBL_DATA_SIZE       64      /* size in bytes reserved for initial data */
 157 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 158 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 159
 160 /*-----------------------------------------------------------------------
 161  * Start addresses for the final memory configuration
 162  * (Set up by the startup code)
 163  * Please note that CFG_SDRAM_BASE _must_ start at 0
 164  */
 165 #define CFG_SDRAM_BASE          0x00000000
 166 #define CFG_SDRAM_SIZE          16      /* SDRAM size in MB */
 167 #define CFG_FLASH_BASE          0xffe00000
 168 #define CFG_INT_FLASH_BASE      0xf0000000
 169 #define CFG_INT_FLASH_ENABLE    0x21
 170
 171 /* If M5282 port is fully implemented the monitor base will be behind
 172  * the vector table. */
 173 #if (TEXT_BASE != CFG_INT_FLASH_BASE)
 174 #define CFG_MONITOR_BASE        (CFG_FLASH_BASE + 0x400)
 175 #else
 176 #define CFG_MONITOR_BASE        (TEXT_BASE + 0x418)     /* 24 Byte for CFM-Config */
 177 #endif
 178
 179 #define CFG_MONITOR_LEN         0x20000
 180 #define CFG_MALLOC_LEN          (256 << 10)
 181 #define CFG_BOOTPARAMS_LEN      64*1024
 182
 183 /*
 184  * For booting Linux, the board info and command line data
 185  * have to be in the first 8 MB of memory, since this is
 186  * the maximum mapped by the Linux kernel during initialization ??
 187  */
 188 #define CFG_BOOTMAPSZ           (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
 189
 190 /*-----------------------------------------------------------------------
 191  * FLASH organization
 192  */
 193 #define CFG_FLASH_CFI
 194 #ifdef CFG_FLASH_CFI
 195
 196 #       define CFG_FLASH_CFI_DRIVER     1
 197 #       define CFG_FLASH_SIZE           0x1000000       /* Max size that the board might have */
 198 #       define CFG_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 199 #       define CFG_MAX_FLASH_BANKS      1       /* max number of memory banks */
 200 #       define CFG_MAX_FLASH_SECT       137     /* max number of sectors on one chip */
 201 #       define CFG_FLASH_PROTECTION     /* "Real" (hardware) sectors protection */
 202 #       define CFG_FLASH_CHECKSUM
 203 #       define CFG_FLASH_BANKS_LIST     { CFG_FLASH_BASE }
 204 #endif
 205
 206 /*-----------------------------------------------------------------------
 207  * Cache Configuration
 208  */
 209 #define CFG_CACHELINE_SIZE      16
 210
 211 /*-----------------------------------------------------------------------
 212  * Memory bank definitions
 213  */
 214 #define CFG_CS0_BASE            CFG_FLASH_BASE
 215 #define CFG_CS0_SIZE            2*1024*1024
 216 #define CFG_CS0_WIDTH           16
 217 #define CFG_CS0_RO              0
 218 #define CFG_CS0_WS              6
 219 /*
 220 #define CFG_CS3_BASE            0xE0000000
 221 #define CFG_CS3_SIZE            1*1024*1024
 222 #define CFG_CS3_WIDTH           16
 223 #define CFG_CS3_RO              0
 224 #define CFG_CS3_WS              6
 225 */
 226 /*-----------------------------------------------------------------------
 227  * Port configuration
 228  */
 229 #define CFG_PACNT               0x0000000       /* Port A D[31:24] */
 230 #define CFG_PADDR               0x0000000
 231 #define CFG_PADAT               0x0000000
 232
 233 #define CFG_PBCNT               0x0000000       /* Port B D[23:16] */
 234 #define CFG_PBDDR               0x0000000
 235 #define CFG_PBDAT               0x0000000
 236
 237 #define CFG_PCCNT               0x0000000       /* Port C D[15:08] */
 238 #define CFG_PCDDR               0x0000000
 239 #define CFG_PCDAT               0x0000000
 240
 241 #define CFG_PDCNT               0x0000000       /* Port D D[07:00] */
 242 #define CFG_PCDDR               0x0000000
 243 #define CFG_PCDAT               0x0000000
 244
 245 #define CFG_PEHLPAR             0xC0
 246 #define CFG_PUAPAR              0x0F    /* UA0..UA3 = Uart 0 +1 */
 247 #define CFG_DDRUA               0x05
 248 #define CFG_PJPAR               0xFF;
 249
 250 #endif                          /* _CONFIG_M5282EVB_H */