include/configs/M53017EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF53017EVB.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef _M53017EVB_H
  31 #define _M53017EVB_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_MCF5301x         /* define processor family */
  38 #define CONFIG_M53015           /* define processor type */
  39
  40 #define CONFIG_MCFUART
  41 #define CONFIG_SYS_UART_PORT            (0)
  42 #define CONFIG_BAUDRATE                 115200
  43
  44 #undef CONFIG_WATCHDOG
  45 #define CONFIG_WATCHDOG_TIMEOUT         5000
  46
  47 /* Command line configuration */
  48 #include <config_cmd_default.h>
  49
  50 #define CONFIG_CMD_CACHE
  51 #define CONFIG_CMD_DATE
  52 #define CONFIG_CMD_ELF
  53 #define CONFIG_CMD_FLASH
  54 #undef CONFIG_CMD_I2C
  55 #define CONFIG_CMD_MEMORY
  56 #define CONFIG_CMD_MISC
  57 #define CONFIG_CMD_MII
  58 #define CONFIG_CMD_NET
  59 #define CONFIG_CMD_PING
  60 #define CONFIG_CMD_REGINFO
  61
  62 #define CONFIG_SYS_UNIFY_CACHE
  63
  64 #define CONFIG_MCFFEC
  65 #ifdef CONFIG_MCFFEC
  66 #       define CONFIG_MII               1
  67 #       define CONFIG_MII_INIT          1
  68 #       define CONFIG_SYS_DISCOVER_PHY
  69 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  70 #       define CONFIG_SYS_TX_ETH_BUFFER 8
  71 #       define CONFIG_SYS_FEC_BUF_USE_SRAM
  72 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  73 #       define CONFIG_HAS_ETH1
  74
  75 #       define CONFIG_SYS_FEC0_PINMUX   0
  76 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  77 #       define CONFIG_SYS_FEC1_PINMUX   0
  78 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC1_IOBASE
  79 #       define MCFFEC_TOUT_LOOP         50000
  80
  81 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock3 rw rootfstype=jffs2"
  82
  83 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  84 #       ifndef CONFIG_SYS_DISCOVER_PHY
  85 #               define FECDUPLEX        FULL
  86 #               define FECSPEED         _100BASET
  87 #       else
  88 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  89 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  90 #               endif
  91 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  92 #endif
  93
  94 #define CONFIG_MCFRTC
  95 #undef RTC_DEBUG
  96 #define CONFIG_SYS_RTC_CNT              (0x8000)
  97 #define CONFIG_SYS_RTC_SETUP            (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  98
  99 /* Timer */
 100 #define CONFIG_MCFTMR
 101 #undef CONFIG_MCFPIT
 102
 103 /* I2C */
 104 #define CONFIG_FSL_I2C
 105 #define CONFIG_HARD_I2C                 /* I2C with hw support */
 106 #define CONFIG_SYS_I2C_SPEED            80000
 107 #define CONFIG_SYS_I2C_SLAVE            0x7F
 108 #define CONFIG_SYS_I2C_OFFSET           0x58000
 109 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 110
 111 #define CONFIG_BOOTDELAY                1       /* autoboot after 5 seconds */
 112 #define CONFIG_UDP_CHECKSUM
 113
 114 #ifdef CONFIG_MCFFEC
 115 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
 116 #       define CONFIG_ETH1ADDR  00:e0:0c:bc:e5:61
 117 #       define CONFIG_IPADDR    192.162.1.2
 118 #       define CONFIG_NETMASK   255.255.255.0
 119 #       define CONFIG_SERVERIP  192.162.1.1
 120 #       define CONFIG_GATEWAYIP 192.162.1.1
 121 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 122 #endif                          /* FEC_ENET */
 123
 124 #define CONFIG_HOSTNAME         M53017
 125 #define CONFIG_EXTRA_ENV_SETTINGS               \
 126         "netdev=eth0\0"                         \
 127         "loadaddr=40010000\0"                   \
 128         "u-boot=u-boot.bin\0"                   \
 129         "load=tftp ${loadaddr) ${u-boot}\0"     \
 130         "upd=run load; run prog\0"              \
 131         "prog=prot off 0 3ffff;"                \
 132         "era 0 3ffff;"                          \
 133         "cp.b ${loadaddr} 0 ${filesize};"       \
 134         "save\0"                                \
 135         ""
 136
 137 #define CONFIG_PRAM             512     /* 512 KB */
 138 #define CONFIG_SYS_PROMPT       "-> "
 139 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 140
 141 #ifdef CONFIG_CMD_KGDB
 142 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 143 #else
 144 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 145 #endif
 146
 147 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 148 #define CONFIG_SYS_MAXARGS      16              /* max number of cmd args */
 149 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Arg Buf Sz */
 150 #define CONFIG_SYS_LOAD_ADDR    0x40010000
 151
 152 #define CONFIG_SYS_HZ           1000
 153 #define CONFIG_SYS_CLK          80000000
 154 #define CONFIG_SYS_CPU_CLK      CONFIG_SYS_CLK * 3
 155
 156 #define CONFIG_SYS_MBAR         0xFC000000
 157
 158 /*
 159  * Low Level Configuration Settings
 160  * (address mappings, register initial values, etc.)
 161  * You should know what you are doing if you make changes here.
 162  */
 163 /*
 164  * Definitions for initial stack pointer and data area (in DPRAM)
 165  */
 166 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 167 #define CONFIG_SYS_INIT_RAM_SIZE                0x20000 /* Size of used area in internal SRAM */
 168 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 169 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 170 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 171
 172 /*
 173  * Start addresses for the final memory configuration
 174  * (Set up by the startup code)
 175  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 176  */
 177 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 178 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
 179 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 180 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 181 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
 182 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 183 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 184
 185 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 186 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 187
 188 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 189 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 190
 191 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 192 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 193
 194 /*
 195  * For booting Linux, the board info and command line data
 196  * have to be in the first 8 MB of memory, since this is
 197  * the maximum mapped by the Linux kernel during initialization ??
 198  */
 199 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 200 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 201
 202 /*-----------------------------------------------------------------------
 203  * FLASH organization
 204  */
 205 #define CONFIG_SYS_FLASH_CFI
 206 #ifdef CONFIG_SYS_FLASH_CFI
 207 #       define CONFIG_FLASH_CFI_DRIVER          1
 208 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 209 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
 210 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 211 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 212 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 213 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 214 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 215 #endif
 216
 217 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 218
 219 /* Configuration for environment
 220  * Environment is embedded in u-boot in the second sector of the flash
 221  */
 222 #define CONFIG_ENV_OFFSET               0x8000
 223 #define CONFIG_ENV_SIZE                 0x1000
 224 #define CONFIG_ENV_SECT_SIZE            0x8000
 225 #define CONFIG_ENV_IS_IN_FLASH          1
 226
 227 /*-----------------------------------------------------------------------
 228  * Cache Configuration
 229  */
 230 #define CONFIG_SYS_CACHELINE_SIZE       16
 231
 232 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 233                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 234 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 235                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 236 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
 237 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 238                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 239                                          CF_ACR_EN | CF_ACR_SM_ALL)
 240 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_EC | CF_CACR_CINVA | \
 241                                          CF_CACR_DCM_P)
 242
 243 /*-----------------------------------------------------------------------
 244  * Chipselect bank definitions
 245  */
 246 /*
 247  * CS0 - NOR Flash
 248  * CS1 - Ext SRAM
 249  * CS2 - Available
 250  * CS3 - Available
 251  * CS4 - Available
 252  * CS5 - Available
 253  */
 254 #define CONFIG_SYS_CS0_BASE             0
 255 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 256 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 257
 258 #define CONFIG_SYS_CS1_BASE             0xC0000000
 259 #define CONFIG_SYS_CS1_MASK             0x00070001
 260 #define CONFIG_SYS_CS1_CTRL             0x00001FA0
 261
 262 #endif                          /* _M53017EVB_H */