include/configs/M5485EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF5485 FireEngine board.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M5485EVB_H
  15 #define _M5485EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_MCF547x_8x       /* define processor family */
  22 #define CONFIG_M548x            /* define processor type */
  23 #define CONFIG_M5485            /* define processor type */
  24
  25 #define CONFIG_DISPLAY_BOARDINFO
  26
  27 #define CONFIG_MCFUART
  28 #define CONFIG_SYS_UART_PORT            (0)
  29 #define CONFIG_BAUDRATE         115200
  30
  31 #undef CONFIG_HW_WATCHDOG
  32 #define CONFIG_WATCHDOG_TIMEOUT 5000    /* timeout in milliseconds, max timeout is 6.71sec */
  33
  34 /* Command line configuration */
  35 #include <config_cmd_default.h>
  36
  37 #define CONFIG_CMD_CACHE
  38 #undef CONFIG_CMD_DATE
  39 #define CONFIG_CMD_ELF
  40 #define CONFIG_CMD_FLASH
  41 #define CONFIG_CMD_I2C
  42 #define CONFIG_CMD_MEMORY
  43 #define CONFIG_CMD_MISC
  44 #define CONFIG_CMD_MII
  45 #define CONFIG_CMD_NET
  46 #define CONFIG_CMD_PCI
  47 #define CONFIG_CMD_PING
  48 #define CONFIG_CMD_REGINFO
  49 #define CONFIG_CMD_USB
  50
  51 #define CONFIG_SLTTMR
  52
  53 #define CONFIG_FSLDMAFEC
  54 #ifdef CONFIG_FSLDMAFEC
  55 #       define CONFIG_MII               1
  56 #       define CONFIG_MII_INIT          1
  57 #       define CONFIG_HAS_ETH1
  58
  59 #       define CONFIG_SYS_DMA_USE_INTSRAM       1
  60 #       define CONFIG_SYS_DISCOVER_PHY
  61 #       define CONFIG_SYS_RX_ETH_BUFFER 32
  62 #       define CONFIG_SYS_TX_ETH_BUFFER 48
  63 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  64
  65 #       define CONFIG_SYS_FEC0_PINMUX           0
  66 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  67 #       define CONFIG_SYS_FEC1_PINMUX           0
  68 #       define CONFIG_SYS_FEC1_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  69
  70 #       define MCFFEC_TOUT_LOOP         50000
  71 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  72 #       ifndef CONFIG_SYS_DISCOVER_PHY
  73 #               define FECDUPLEX        FULL
  74 #               define FECSPEED         _100BASET
  75 #       else
  76 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  77 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  78 #               endif
  79 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  80
  81 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
  82 #       define CONFIG_ETH1ADDR  00:e0:0c:bc:e5:61
  83 #       define CONFIG_IPADDR    192.162.1.2
  84 #       define CONFIG_NETMASK   255.255.255.0
  85 #       define CONFIG_SERVERIP  192.162.1.1
  86 #       define CONFIG_GATEWAYIP 192.162.1.1
  87 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  88
  89 #endif
  90
  91 #ifdef CONFIG_CMD_USB
  92 #       define CONFIG_USB_STORAGE
  93 #       define CONFIG_DOS_PARTITION
  94 #       define CONFIG_USB_OHCI_NEW
  95 #       ifndef CONFIG_CMD_PCI
  96 #               define CONFIG_CMD_PCI
  97 #       endif
  98 /*#     define CONFIG_PCI_OHCI*/
  99 #       define CONFIG_SYS_USB_OHCI_REGS_BASE            0x80041000
 100 #       define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS       15
 101 #       define CONFIG_SYS_USB_OHCI_SLOT_NAME            "isp1561"
 102 #       define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 103 #endif
 104
 105 /* I2C */
 106 #define CONFIG_SYS_I2C
 107 #define CONFIG_SYS_I2C_FSL
 108 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 109 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 110 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00008F00
 111 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 112
 113 /* PCI */
 114 #ifdef CONFIG_CMD_PCI
 115 #define CONFIG_PCI              1
 116 #define CONFIG_PCI_PNP          1
 117 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 118
 119 #define CONFIG_SYS_PCI_MEM_BUS          0x80000000
 120 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
 121 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 122
 123 #define CONFIG_SYS_PCI_IO_BUS           0x71000000
 124 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 125 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 126
 127 #define CONFIG_SYS_PCI_CFG_BUS          0x70000000
 128 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 129 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 130 #endif
 131
 132 #define CONFIG_BOOTDELAY        1       /* autoboot after 5 seconds */
 133 #define CONFIG_UDP_CHECKSUM
 134
 135 #define CONFIG_HOSTNAME         M548xEVB
 136 #define CONFIG_EXTRA_ENV_SETTINGS               \
 137         "netdev=eth0\0"                         \
 138         "loadaddr=10000\0"                      \
 139         "u-boot=u-boot.bin\0"                   \
 140         "load=tftp ${loadaddr) ${u-boot}\0"     \
 141         "upd=run load; run prog\0"              \
 142         "prog=prot off bank 1;"                 \
 143         "era ff800000 ff83ffff;"                \
 144         "cp.b ${loadaddr} ff800000 ${filesize};"\
 145         "save\0"                                \
 146         ""
 147
 148 #define CONFIG_PRAM             512     /* 512 KB */
 149 #define CONFIG_SYS_PROMPT               "-> "
 150 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 151
 152 #ifdef CONFIG_CMD_KGDB
 153 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 154 #else
 155 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 156 #endif
 157
 158 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 159 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 160 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 161 #define CONFIG_SYS_LOAD_ADDR            0x00010000
 162
 163 #define CONFIG_SYS_CLK                  CONFIG_SYS_BUSCLK
 164 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 2
 165
 166 #define CONFIG_SYS_MBAR         0xF0000000
 167 #define CONFIG_SYS_INTSRAM              (CONFIG_SYS_MBAR + 0x10000)
 168 #define CONFIG_SYS_INTSRAMSZ            0x8000
 169
 170 /*#define CONFIG_SYS_LATCH_ADDR         (CONFIG_SYS_CS1_BASE + 0x80000)*/
 171
 172 /*
 173  * Low Level Configuration Settings
 174  * (address mappings, register initial values, etc.)
 175  * You should know what you are doing if you make changes here.
 176  */
 177 /*-----------------------------------------------------------------------
 178  * Definitions for initial stack pointer and data area (in DPRAM)
 179  */
 180 #define CONFIG_SYS_INIT_RAM_ADDR        0xF2000000
 181 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in internal SRAM */
 182 #define CONFIG_SYS_INIT_RAM_CTRL        0x21
 183 #define CONFIG_SYS_INIT_RAM1_ADDR       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
 184 #define CONFIG_SYS_INIT_RAM1_END        0x1000  /* End of used area in internal SRAM */
 185 #define CONFIG_SYS_INIT_RAM1_CTRL       0x21
 186 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 187 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 188
 189 /*-----------------------------------------------------------------------
 190  * Start addresses for the final memory configuration
 191  * (Set up by the startup code)
 192  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 193  */
 194 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 195 #define CONFIG_SYS_SDRAM_CFG1           0x73711630
 196 #define CONFIG_SYS_SDRAM_CFG2           0x46770000
 197 #define CONFIG_SYS_SDRAM_CTRL           0xE10B0000
 198 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 199 #define CONFIG_SYS_SDRAM_MODE           0x018D0000
 200 #define CONFIG_SYS_SDRAM_DRVSTRENGTH    0x000002AA
 201 #ifdef CONFIG_SYS_DRAMSZ1
 202 #       define CONFIG_SYS_SDRAM_SIZE    (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
 203 #else
 204 #       define CONFIG_SYS_SDRAM_SIZE    CONFIG_SYS_DRAMSZ
 205 #endif
 206
 207 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 208 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 209
 210 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 211 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 212
 213 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 214
 215 /* Reserve 256 kB for malloc() */
 216 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 217 /*
 218  * For booting Linux, the board info and command line data
 219  * have to be in the first 8 MB of memory, since this is
 220  * the maximum mapped by the Linux kernel during initialization ??
 221  */
 222 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 223
 224 /*-----------------------------------------------------------------------
 225  * FLASH organization
 226  */
 227 #define CONFIG_SYS_FLASH_CFI
 228 #ifdef CONFIG_SYS_FLASH_CFI
 229 #       define CONFIG_SYS_FLASH_BASE            (CONFIG_SYS_CS0_BASE)
 230 #       define CONFIG_FLASH_CFI_DRIVER  1
 231 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 232 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 233 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 234 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 235 #ifdef CONFIG_SYS_NOR1SZ
 236 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 237 #       define CONFIG_SYS_FLASH_SIZE            ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
 238 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 239 #else
 240 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 241 #       define CONFIG_SYS_FLASH_SIZE            (CONFIG_SYS_BOOTSZ << 20)
 242 #endif
 243 #endif
 244
 245 /* Configuration for environment
 246  * Environment is not embedded in u-boot. First time runing may have env
 247  * crc error warning if there is no correct environment on the flash.
 248  */
 249 #define CONFIG_ENV_OFFSET               0x40000
 250 #define CONFIG_ENV_SECT_SIZE    0x10000
 251 #define CONFIG_ENV_IS_IN_FLASH  1
 252
 253 /*-----------------------------------------------------------------------
 254  * Cache Configuration
 255  */
 256 #define CONFIG_SYS_CACHELINE_SIZE       16
 257
 258 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 259                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 260 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 261                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 262 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA + \
 263                                          CF_CACR_IDCM)
 264 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 265 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 266                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 267                                          CF_ACR_EN | CF_ACR_SM_ALL)
 268 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_BCINVA | \
 269                                          CF_CACR_IEC | CF_CACR_ICINVA)
 270 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 271                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 272                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 273
 274 /*-----------------------------------------------------------------------
 275  * Chipselect bank definitions
 276  */
 277 /*
 278  * CS0 - NOR Flash 1, 2, 4, or 8MB
 279  * CS1 - NOR Flash
 280  * CS2 - Available
 281  * CS3 - Available
 282  * CS4 - Available
 283  * CS5 - Available
 284  */
 285 #define CONFIG_SYS_CS0_BASE             0xFF800000
 286 #define CONFIG_SYS_CS0_MASK             (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
 287 #define CONFIG_SYS_CS0_CTRL             0x00101980
 288
 289 #ifdef CONFIG_SYS_NOR1SZ
 290 #define CONFIG_SYS_CS1_BASE             0xE0000000
 291 #define CONFIG_SYS_CS1_MASK             (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
 292 #define CONFIG_SYS_CS1_CTRL             0x00101D80
 293 #endif
 294
 295 #endif                          /* _M5485EVB_H */