include/configs/M5485EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF5485 FireEngine board.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef _M5485EVB_H
  31 #define _M5485EVB_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_MCF547x_8x       /* define processor family */
  38 #define CONFIG_M548x            /* define processor type */
  39 #define CONFIG_M5485            /* define processor type */
  40
  41 #define CONFIG_MCFUART
  42 #define CONFIG_SYS_UART_PORT            (0)
  43 #define CONFIG_BAUDRATE         115200
  44
  45 #define CONFIG_HW_WATCHDOG
  46 #define CONFIG_WATCHDOG_TIMEOUT 5000    /* timeout in milliseconds, max timeout is 6.71sec */
  47
  48 /* Command line configuration */
  49 #include <config_cmd_default.h>
  50
  51 #define CONFIG_CMD_CACHE
  52 #undef CONFIG_CMD_DATE
  53 #define CONFIG_CMD_ELF
  54 #define CONFIG_CMD_FLASH
  55 #define CONFIG_CMD_I2C
  56 #define CONFIG_CMD_MEMORY
  57 #define CONFIG_CMD_MISC
  58 #define CONFIG_CMD_MII
  59 #define CONFIG_CMD_NET
  60 #define CONFIG_CMD_PCI
  61 #define CONFIG_CMD_PING
  62 #define CONFIG_CMD_REGINFO
  63 #define CONFIG_CMD_USB
  64
  65 #define CONFIG_SLTTMR
  66
  67 #define CONFIG_FSLDMAFEC
  68 #ifdef CONFIG_FSLDMAFEC
  69 #       define CONFIG_MII               1
  70 #       define CONFIG_MII_INIT          1
  71 #       define CONFIG_HAS_ETH1
  72
  73 #       define CONFIG_SYS_DMA_USE_INTSRAM       1
  74 #       define CONFIG_SYS_DISCOVER_PHY
  75 #       define CONFIG_SYS_RX_ETH_BUFFER 32
  76 #       define CONFIG_SYS_TX_ETH_BUFFER 48
  77 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  78
  79 #       define CONFIG_SYS_FEC0_PINMUX           0
  80 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  81 #       define CONFIG_SYS_FEC1_PINMUX           0
  82 #       define CONFIG_SYS_FEC1_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  83
  84 #       define MCFFEC_TOUT_LOOP         50000
  85 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  86 #       ifndef CONFIG_SYS_DISCOVER_PHY
  87 #               define FECDUPLEX        FULL
  88 #               define FECSPEED         _100BASET
  89 #       else
  90 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  91 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  92 #               endif
  93 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  94
  95 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
  96 #       define CONFIG_ETH1ADDR  00:e0:0c:bc:e5:61
  97 #       define CONFIG_IPADDR    192.162.1.2
  98 #       define CONFIG_NETMASK   255.255.255.0
  99 #       define CONFIG_SERVERIP  192.162.1.1
 100 #       define CONFIG_GATEWAYIP 192.162.1.1
 101 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 102
 103 #endif
 104
 105 #ifdef CONFIG_CMD_USB
 106 #       define CONFIG_USB_STORAGE
 107 #       define CONFIG_DOS_PARTITION
 108 #       define CONFIG_USB_OHCI_NEW
 109 #       ifndef CONFIG_CMD_PCI
 110 #               define CONFIG_CMD_PCI
 111 #       endif
 112 /*#     define CONFIG_PCI_OHCI*/
 113 #       define CONFIG_SYS_USB_OHCI_REGS_BASE            0x80041000
 114 #       define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS       15
 115 #       define CONFIG_SYS_USB_OHCI_SLOT_NAME            "isp1561"
 116 #       define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
 117 #endif
 118
 119 /* I2C */
 120 #define CONFIG_FSL_I2C
 121 #define CONFIG_HARD_I2C         /* I2C with hw support */
 122 #define CONFIG_SYS_I2C_SPEED            80000
 123 #define CONFIG_SYS_I2C_SLAVE            0x7F
 124 #define CONFIG_SYS_I2C_OFFSET           0x00008F00
 125 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 126
 127 /* PCI */
 128 #ifdef CONFIG_CMD_PCI
 129 #define CONFIG_PCI              1
 130 #define CONFIG_PCI_PNP          1
 131 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 132
 133 #define CONFIG_SYS_PCI_MEM_BUS          0x80000000
 134 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
 135 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 136
 137 #define CONFIG_SYS_PCI_IO_BUS           0x71000000
 138 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 139 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 140
 141 #define CONFIG_SYS_PCI_CFG_BUS          0x70000000
 142 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 143 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 144 #endif
 145
 146 #define CONFIG_BOOTDELAY        1       /* autoboot after 5 seconds */
 147 #define CONFIG_UDP_CHECKSUM
 148
 149 #define CONFIG_HOSTNAME         M548xEVB
 150 #define CONFIG_EXTRA_ENV_SETTINGS               \
 151         "netdev=eth0\0"                         \
 152         "loadaddr=10000\0"                      \
 153         "u-boot=u-boot.bin\0"                   \
 154         "load=tftp ${loadaddr) ${u-boot}\0"     \
 155         "upd=run load; run prog\0"              \
 156         "prog=prot off bank 1;"                 \
 157         "era ff800000 ff83ffff;"                \
 158         "cp.b ${loadaddr} ff800000 ${filesize};"\
 159         "save\0"                                \
 160         ""
 161
 162 #define CONFIG_PRAM             512     /* 512 KB */
 163 #define CONFIG_SYS_PROMPT               "-> "
 164 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 165
 166 #ifdef CONFIG_CMD_KGDB
 167 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 168 #else
 169 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 170 #endif
 171
 172 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 173 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 174 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 175 #define CONFIG_SYS_LOAD_ADDR            0x00010000
 176
 177 #define CONFIG_SYS_HZ                   1000
 178 #define CONFIG_SYS_CLK                  CONFIG_SYS_BUSCLK
 179 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 2
 180
 181 #define CONFIG_SYS_MBAR         0xF0000000
 182 #define CONFIG_SYS_INTSRAM              (CONFIG_SYS_MBAR + 0x10000)
 183 #define CONFIG_SYS_INTSRAMSZ            0x8000
 184
 185 /*#define CONFIG_SYS_LATCH_ADDR         (CONFIG_SYS_CS1_BASE + 0x80000)*/
 186
 187 /*
 188  * Low Level Configuration Settings
 189  * (address mappings, register initial values, etc.)
 190  * You should know what you are doing if you make changes here.
 191  */
 192 /*-----------------------------------------------------------------------
 193  * Definitions for initial stack pointer and data area (in DPRAM)
 194  */
 195 #define CONFIG_SYS_INIT_RAM_ADDR        0xF2000000
 196 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in internal SRAM */
 197 #define CONFIG_SYS_INIT_RAM_CTRL        0x21
 198 #define CONFIG_SYS_INIT_RAM1_ADDR       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
 199 #define CONFIG_SYS_INIT_RAM1_END        0x1000  /* End of used area in internal SRAM */
 200 #define CONFIG_SYS_INIT_RAM1_CTRL       0x21
 201 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 202 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 203
 204 /*-----------------------------------------------------------------------
 205  * Start addresses for the final memory configuration
 206  * (Set up by the startup code)
 207  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 208  */
 209 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 210 #define CONFIG_SYS_SDRAM_CFG1           0x73711630
 211 #define CONFIG_SYS_SDRAM_CFG2           0x46770000
 212 #define CONFIG_SYS_SDRAM_CTRL           0xE10B0000
 213 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 214 #define CONFIG_SYS_SDRAM_MODE           0x018D0000
 215 #define CONFIG_SYS_SDRAM_DRVSTRENGTH    0x000002AA
 216 #ifdef CONFIG_SYS_DRAMSZ1
 217 #       define CONFIG_SYS_SDRAM_SIZE    (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
 218 #else
 219 #       define CONFIG_SYS_SDRAM_SIZE    CONFIG_SYS_DRAMSZ
 220 #endif
 221
 222 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 223 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 224
 225 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 226 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 227
 228 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 229
 230 /* Reserve 256 kB for malloc() */
 231 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 232 /*
 233  * For booting Linux, the board info and command line data
 234  * have to be in the first 8 MB of memory, since this is
 235  * the maximum mapped by the Linux kernel during initialization ??
 236  */
 237 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 238
 239 /*-----------------------------------------------------------------------
 240  * FLASH organization
 241  */
 242 #define CONFIG_SYS_FLASH_CFI
 243 #ifdef CONFIG_SYS_FLASH_CFI
 244 #       define CONFIG_SYS_FLASH_BASE            (CONFIG_SYS_CS0_BASE)
 245 #       define CONFIG_FLASH_CFI_DRIVER  1
 246 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 247 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 248 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 249 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 250 #ifdef CONFIG_SYS_NOR1SZ
 251 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 252 #       define CONFIG_SYS_FLASH_SIZE            ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
 253 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 254 #else
 255 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 256 #       define CONFIG_SYS_FLASH_SIZE            (CONFIG_SYS_BOOTSZ << 20)
 257 #endif
 258 #endif
 259
 260 /* Configuration for environment
 261  * Environment is not embedded in u-boot. First time runing may have env
 262  * crc error warning if there is no correct environment on the flash.
 263  */
 264 #define CONFIG_ENV_OFFSET               0x40000
 265 #define CONFIG_ENV_SECT_SIZE    0x10000
 266 #define CONFIG_ENV_IS_IN_FLASH  1
 267
 268 /*-----------------------------------------------------------------------
 269  * Cache Configuration
 270  */
 271 #define CONFIG_SYS_CACHELINE_SIZE       16
 272
 273 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 274                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 275 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 276                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 277 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA + \
 278                                          CF_CACR_IDCM)
 279 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 280 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 281                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 282                                          CF_ACR_EN | CF_ACR_SM_ALL)
 283 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_BCINVA | \
 284                                          CF_CACR_IEC | CF_CACR_ICINVA)
 285 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 286                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 287                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 288
 289 /*-----------------------------------------------------------------------
 290  * Chipselect bank definitions
 291  */
 292 /*
 293  * CS0 - NOR Flash 1, 2, 4, or 8MB
 294  * CS1 - NOR Flash
 295  * CS2 - Available
 296  * CS3 - Available
 297  * CS4 - Available
 298  * CS5 - Available
 299  */
 300 #define CONFIG_SYS_CS0_BASE             0xFF800000
 301 #define CONFIG_SYS_CS0_MASK             (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
 302 #define CONFIG_SYS_CS0_CTRL             0x00101980
 303
 304 #ifdef CONFIG_SYS_NOR1SZ
 305 #define CONFIG_SYS_CS1_BASE             0xE0000000
 306 #define CONFIG_SYS_CS1_MASK             (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
 307 #define CONFIG_SYS_CS1_CTRL             0x00101D80
 308 #endif
 309
 310 #endif                          /* _M5485EVB_H */