include/configs/MBX860T.h

   1  /*
   2   * A collection of structures, addresses, and values associated with
   3   * the Motorola 860T MBX board.
   4   * Copied from the FADS stuff, which was originally copied from the MBX stuff!
   5   * Magnus Damm added defines for 8xxrom and extended bd_info.
   6   * Helmut Buchsbaum added bitvalues for BCSRx
   7   * Rob Taylor coverted it back to MBX
   8   *
   9   * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
  10   */
  11
  12 /* ------------------------------------------------------------------------- */
  13
  14 /*
  15  * board/config.h - configuration options, board specific
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /*
  22  * High Level Configuration Options
  23  * (easy to change)
  24  */
  25 #include <mpc8xx_irq.h>
  26
  27 #define CONFIG_MPC860           1
  28 #define CONFIG_MPC860T          1
  29 #define CONFIG_MBX              1
  30
  31 #define CONFIG_SYS_TEXT_BASE    0xfe000000
  32
  33 #define CONFIG_8xx_CPUCLOCK     40
  34 #define CONFIG_8xx_BUSCLOCK     (CONFIG_8xx_CPUCLOCK)
  35 #define TARGET_SYSTEM_FREQUENCY 40
  36
  37 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  38 #undef  CONFIG_8xx_CONS_SMC2
  39 #define CONFIG_BAUDRATE         9600
  40
  41 #define MPC8XX_FACT     10                              /* Multiply by 10               */
  42 #define MPC8XX_XIN      40000000                /* 50 MHz in    */
  43 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
  44
  45 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  46
  47 #if 1
  48 #define CONFIG_8xx_BOOTDELAY    -1      /* autoboot disabled            */
  49 #define CONFIG_8xx_TFTP_MODE
  50 #else
  51 #define CONFIG_8xx_BOOTDELAY    5       /* autoboot after 5 seconds     */
  52 #undef  CONFIG_8xx_TFTP_MODE
  53 #endif
  54
  55 #define CONFIG_MISC_INIT_R
  56
  57 #define CONFIG_DRAM_SPEED       (CONFIG_8xx_BUSCLOCK)   /* MHz          */
  58 #define CONFIG_BOOTCOMMAND      "bootm FE020000"        /* autoboot command */
  59 #define CONFIG_BOOTARGS         " "
  60 /*
  61  * Miscellaneous configurable options
  62  */
  63 #undef  CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  64 #define CONFIG_SYS_PROMPT               ":>"            /* Monitor Command Prompt       */
  65 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  66 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  67 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  68 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  69
  70 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  71 #define CONFIG_SYS_MEMTEST_END          0x0800000       /* 4 ... 8 MB in DRAM   */
  72
  73 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
  74
  75 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
  76
  77 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  78
  79 /*
  80  * Low Level Configuration Settings
  81  * (address mappings, register initial values, etc.)
  82  * You should know what you are doing if you make changes here.
  83  */
  84 /*-----------------------------------------------------------------------
  85  * Internal Memory Mapped Register
  86  */
  87 #define CONFIG_SYS_IMMR                 0xFFA00000
  88 #define CONFIG_SYS_IMMR_SIZE            ((uint)(64 * 1024))
  89 #define CONFIG_SYS_NVRAM_BASE           0xFA000000 /* NVRAM                          */
  90 #define CONFIG_SYS_NVRAM_OR             0xffe00000 /* w/o speed dependent flags!!    */
  91 #define CONFIG_SYS_CSR_BASE             0xFA100000 /* Control/Status Registers       */
  92 #define CONFIG_SYS_PCIMEM_BASE          0x80000000 /* PCI I/O and Memory Spaces      */
  93 #define CONFIG_SYS_PCIMEM_OR            0xA0000108
  94 #define CONFIG_SYS_PCIBRIDGE_BASE       0xFA210000 /* PCI-Bus Bridge Registers       */
  95 #define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108
  96
  97 /*-----------------------------------------------------------------------
  98  * Definitions for initial stack pointer and data area (in DPRAM)
  99  */
 100 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 101 #define CONFIG_SYS_INIT_RAM_SIZE        0x2f00  /* Size of used area in DPRAM   */
 102 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 103 #define CONFIG_SYS_INIT_VPD_SIZE        256 /* size in bytes reserved for vpd buffer */
 104 #define CONFIG_SYS_INIT_VPD_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
 105 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_VPD_OFFSET-8)
 106
 107 /*-----------------------------------------------------------------------
 108  * Offset in DPMEM where we keep the VPD data
 109  */
 110 #define CONFIG_SYS_DPRAMVPD             (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000)
 111
 112 /*-----------------------------------------------------------------------
 113  * Start addresses for the final memory configuration
 114  * (Set up by the startup code)
 115  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 116  */
 117 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 118 #define CONFIG_SYS_FLASH_BASE           0x00000000
 119 /*0xFE000000*/
 120 #define CONFIG_SYS_FLASH_SIZE           ((uint)(8 * 1024 * 1024))       /* max 8Mbyte */
 121 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 122 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 123 #define CONFIG_SYS_HWINFO_ADDR          (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_SYS_HWINFO_LEN)
 124 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc()  */
 125
 126 /*
 127  * For booting Linux, the board info and command line data
 128  * have to be in the first 8 MB of memory, since this is
 129  * the maximum mapped by the Linux kernel during initialization.
 130  */
 131 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 132
 133 /*-----------------------------------------------------------------------
 134  * FLASH organization
 135  */
 136 #define CONFIG_SYS_MAX_FLASH_BANKS      4       /* max number of memory banks           */
 137 #define CONFIG_SYS_MAX_FLASH_SECT       16      /* max number of sectors on one chip    */
 138
 139 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 140 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 141
 142 /*-----------------------------------------------------------------------
 143  * NVRAM Configuration
 144  *
 145  * Note: the MBX is special because there is already a firmware on this
 146  * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
 147  * access the NVRAM at the offset 0x1000.
 148  */
 149 #define CONFIG_ENV_IS_IN_NVRAM  1       /* turn on NVRAM env feature */
 150 #define CONFIG_ENV_ADDR         (CONFIG_SYS_NVRAM_BASE + 0x1000)
 151 #define CONFIG_ENV_SIZE         0x1000
 152
 153 /*-----------------------------------------------------------------------
 154  * Cache Configuration
 155  */
 156 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 157 #if defined(CONFIG_CMD_KGDB)
 158 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 159 #endif
 160
 161 /*-----------------------------------------------------------------------
 162  * SYPCR - System Protection Control                            11-9
 163  * SYPCR can only be written once after reset!
 164  *-----------------------------------------------------------------------
 165  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 166  */
 167 #if defined(CONFIG_WATCHDOG)
 168 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 169                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 170 #else
 171 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 172 #endif
 173
 174 /*-----------------------------------------------------------------------
 175  * SIUMCR - SIU Module Configuration                            11-6
 176  *-----------------------------------------------------------------------
 177  * PCMCIA config., multi-function pin tri-state
 178  */
 179 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME)
 180
 181 /*-----------------------------------------------------------------------
 182  * TBSCR - Time Base Status and Control                         11-26
 183  *-----------------------------------------------------------------------
 184  * Clear Reference Interrupt Status, Timebase freezing enabled
 185  */
 186 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 187
 188 /*-----------------------------------------------------------------------
 189  * PISCR - Periodic Interrupt Status and Control                11-31
 190  *-----------------------------------------------------------------------
 191  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 192  */
 193 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF | PISCR_PTE)
 194
 195 /*-----------------------------------------------------------------------
 196  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 197  *-----------------------------------------------------------------------
 198  * Reset PLL lock status sticky bit, timer expired status bit and timer
 199  * interrupt status bit - leave PLL multiplication factor unchanged !
 200  */
 201 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 202
 203 /*-----------------------------------------------------------------------
 204  * SCCR - System Clock and reset Control Register               15-27
 205  *-----------------------------------------------------------------------
 206  * Set clock output, timebase and RTC source and divider,
 207  * power management and some other internal clocks
 208  */
 209 #define SCCR_MASK       (SCCR_RTDIV | SCCR_RTSEL)
 210 #define CONFIG_SYS_SCCR SCCR_TBS
 211
 212  /*-----------------------------------------------------------------------
 213  *
 214  *-----------------------------------------------------------------------
 215  *
 216  */
 217 #define CONFIG_SYS_DER          0
 218
 219 /* Because of the way the 860 starts up and assigns CS0 the
 220 * entire address space, we have to set the memory controller
 221 * differently.  Normally, you write the option register
 222 * first, and then enable the chip select by writing the
 223 * base register.  For CS0, you must write the base register
 224 * first, followed by the option register.
 225 */
 226
 227 /*
 228  * Init Memory Controller:
 229  *
 230  * BR0/1 and OR0/1 (FLASH)
 231  */
 232 /* the other CS:s are determined by looking at parameters in BCSRx */
 233
 234
 235 #define BCSR_ADDR               ((uint) 0xFF010000)
 236 #define BCSR_SIZE               ((uint)(64 * 1024))
 237
 238 #define FLASH_BASE0_PRELIM      0xFE000000      /* FLASH bank #0        */
 239 #define FLASH_BASE1_PRELIM      0xFF010000      /* FLASH bank #0        */
 240
 241 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 242 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF00000      /* OR addr mask */
 243
 244 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 245 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 246
 247 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 248 #define CONFIG_SYS_OR0_PRELIM   (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
 249 #define CONFIG_SYS_BR0_PRELIM   (0xFE000000 | BR_V )
 250
 251 /* BCSRx - Board Control and Status Registers */
 252 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 253 #define CONFIG_SYS_OR1_PRELIM   0xFFC00000 | OR_ACS_DIV4
 254 #define CONFIG_SYS_BR1_PRELIM   (0x00000000 | BR_MS_UPMA | BR_V )
 255
 256
 257 /*
 258  * Memory Periodic Timer Prescaler
 259  */
 260
 261 /* periodic timer for refresh */
 262 #define CONFIG_SYS_MAMR_PTA             97              /* start with divider for 100 MHz       */
 263
 264 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 265 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 266 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 267
 268 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 269 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 270 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 271
 272 /*
 273  * MAMR settings for SDRAM
 274  */
 275
 276 /* 8 column SDRAM */
 277 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 278                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 279                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 280 /* 9 column SDRAM */
 281 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 282                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 283                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 284
 285 #define CONFIG_SYS_MAMR         0x13821000
 286
 287 /* values according to the manual */
 288
 289
 290 #define PCMCIA_MEM_ADDR         ((uint)0xff020000)
 291 #define PCMCIA_MEM_SIZE         ((uint)(64 * 1024))
 292
 293 #define BCSR0                   ((uint) (BCSR_ADDR + 00))
 294 #define BCSR1                   ((uint) (BCSR_ADDR + 0x04))
 295 #define BCSR2                   ((uint) (BCSR_ADDR + 0x08))
 296 #define BCSR3                   ((uint) (BCSR_ADDR + 0x0c))
 297 #define BCSR4                   ((uint) (BCSR_ADDR + 0x10))
 298
 299 /* FADS bitvalues by Helmut Buchsbaum
 300  * see MPC8xxADS User's Manual for a proper description
 301  * of the following structures
 302  */
 303
 304 #define BCSR0_ERB       ((uint)0x80000000)
 305 #define BCSR0_IP        ((uint)0x40000000)
 306 #define BCSR0_BDIS      ((uint)0x10000000)
 307 #define BCSR0_BPS_MASK  ((uint)0x0C000000)
 308 #define BCSR0_ISB_MASK  ((uint)0x01800000)
 309 #define BCSR0_DBGC_MASK ((uint)0x00600000)
 310 #define BCSR0_DBPC_MASK ((uint)0x00180000)
 311 #define BCSR0_EBDF_MASK ((uint)0x00060000)
 312
 313 #define BCSR1_FLASH_EN           ((uint)0x80000000)
 314 #define BCSR1_DRAM_EN            ((uint)0x40000000)
 315 #define BCSR1_ETHEN              ((uint)0x20000000)
 316 #define BCSR1_IRDEN              ((uint)0x10000000)
 317 #define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
 318 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
 319 #define BCSR1_BCSR_EN            ((uint)0x02000000)
 320 #define BCSR1_RS232EN_1          ((uint)0x01000000)
 321 #define BCSR1_PCCEN              ((uint)0x00800000)
 322 #define BCSR1_PCCVCC0            ((uint)0x00400000)
 323 #define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
 324 #define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
 325 #define BCSR1_RS232EN_2          ((uint)0x00040000)
 326 #define BCSR1_SDRAM_EN           ((uint)0x00020000)
 327 #define BCSR1_PCCVCC1            ((uint)0x00010000)
 328
 329 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
 330 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 331 #define BCSR2_DRAM_PD_SHIFT      (23)
 332 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
 333 #define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
 334
 335 #define BCSR3_DBID_MASK          ((ushort)0x3800)
 336 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
 337 #define BCSR3_BREVNR0            ((ushort)0x0080)
 338 #define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
 339 #define BCSR3_BREVN1             ((ushort)0x0008)
 340 #define BCSR3_BREVN2_MASK        ((ushort)0x0003)
 341
 342 #define BCSR4_ETHLOOP            ((uint)0x80000000)
 343 #define BCSR4_TFPLDL             ((uint)0x40000000)
 344 #define BCSR4_TPSQEL             ((uint)0x20000000)
 345 #define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
 346 #ifdef CONFIG_MPC823
 347 #define BCSR4_USB_EN             ((uint)0x08000000)
 348 #endif /* CONFIG_MPC823 */
 349 #ifdef CONFIG_MPC860SAR
 350 #define BCSR4_UTOPIA_EN          ((uint)0x08000000)
 351 #endif /* CONFIG_MPC860SAR */
 352 #ifdef CONFIG_MPC860T
 353 #define BCSR4_FETH_EN            ((uint)0x08000000)
 354 #endif /* CONFIG_MPC860T */
 355 #define BCSR4_USB_SPEED          ((uint)0x04000000)
 356 #define BCSR4_VCCO               ((uint)0x02000000)
 357 #define BCSR4_VIDEO_ON           ((uint)0x00800000)
 358 #define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
 359 #define BCSR4_VIDEO_RST          ((uint)0x00200000)
 360 #define BCSR4_MODEM_EN           ((uint)0x00100000)
 361 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 362
 363 #define CONFIG_DRAM_40MHZ               1
 364
 365 #ifdef CONFIG_MPC860T
 366
 367 /* Interrupt level assignments.
 368 */
 369 #define FEC_INTERRUPT   SIU_LEVEL1      /* FEC interrupt */
 370
 371 #endif /* CONFIG_MPC860T */
 372
 373 /* We don't use the 8259.
 374 */
 375 #define NR_8259_INTS    0
 376
 377 #define CONFIG_CMD_NET
 378 /*
 379  * MPC8xx CPM Options
 380  */
 381 #define CONFIG_SCC_ENET 1
 382 #define CONFIG_SCC1_ENET 1
 383 #define CONFIG_FEC_ENET 1
 384 #undef  CONFIG_CPM_IIC
 385 #undef  CONFIG_UCODE_PATCH
 386
 387
 388 #define CONFIG_DISK_SPINUP_TIME 1000000
 389
 390
 391 /* PCMCIA configuration */
 392
 393 #define PCMCIA_MAX_SLOTS    2
 394
 395 #ifdef CONFIG_MPC860
 396 #define PCMCIA_SLOT_A 1
 397 #endif
 398
 399 #endif  /* __CONFIG_H */