include/configs/MBX860T.h

   1  /*
   2   * A collection of structures, addresses, and values associated with
   3   * the Motorola 860T MBX board.
   4   * Copied from the FADS stuff, which was originally copied from the MBX stuff!
   5   * Magnus Damm added defines for 8xxrom and extended bd_info.
   6   * Helmut Buchsbaum added bitvalues for BCSRx
   7   * Rob Taylor coverted it back to MBX
   8   *
   9   * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
  10   */
  11
  12 /* ------------------------------------------------------------------------- */
  13
  14 /*
  15  * board/config.h - configuration options, board specific
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /*
  22  * High Level Configuration Options
  23  * (easy to change)
  24  */
  25 #include <mpc8xx_irq.h>
  26
  27 #define CONFIG_MPC860           1
  28 #define CONFIG_MPC860T          1
  29 #define CONFIG_MBX              1
  30
  31 #define CONFIG_8xx_CPUCLOCK     40
  32 #define CONFIG_8xx_BUSCLOCK     (CONFIG_8xx_CPUCLOCK)
  33 #define TARGET_SYSTEM_FREQUENCY 40
  34
  35 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  36 #undef  CONFIG_8xx_CONS_SMC2
  37 #define CONFIG_BAUDRATE         9600
  38
  39 #define MPC8XX_FACT     10                              /* Multiply by 10               */
  40 #define MPC8XX_XIN      40000000                /* 50 MHz in    */
  41 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
  42
  43 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  44
  45 #if 1
  46 #define CONFIG_8xx_BOOTDELAY    -1      /* autoboot disabled            */
  47 #define CONFIG_8xx_TFTP_MODE
  48 #else
  49 #define CONFIG_8xx_BOOTDELAY    5       /* autoboot after 5 seconds     */
  50 #undef  CONFIG_8xx_TFTP_MODE
  51 #endif
  52
  53 #define CONFIG_MISC_INIT_R
  54
  55 #define CONFIG_DRAM_SPEED       (CONFIG_8xx_BUSCLOCK)   /* MHz          */
  56 #define CONFIG_BOOTCOMMAND      "bootm FE020000"        /* autoboot command */
  57 #define CONFIG_BOOTARGS         " "
  58 /*
  59  * Miscellaneous configurable options
  60  */
  61 #undef  CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  62 #define CONFIG_SYS_PROMPT               ":>"            /* Monitor Command Prompt       */
  63 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  64 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  65 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  66 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  67
  68 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  69 #define CONFIG_SYS_MEMTEST_END          0x0800000       /* 4 ... 8 MB in DRAM   */
  70
  71 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
  72
  73 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
  74
  75 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  76
  77 /*
  78  * Low Level Configuration Settings
  79  * (address mappings, register initial values, etc.)
  80  * You should know what you are doing if you make changes here.
  81  */
  82 /*-----------------------------------------------------------------------
  83  * Internal Memory Mapped Register
  84  */
  85 #define CONFIG_SYS_IMMR                 0xFFA00000
  86 #define CONFIG_SYS_IMMR_SIZE            ((uint)(64 * 1024))
  87 #define CONFIG_SYS_NVRAM_BASE           0xFA000000 /* NVRAM                          */
  88 #define CONFIG_SYS_NVRAM_OR             0xffe00000 /* w/o speed dependent flags!!    */
  89 #define CONFIG_SYS_CSR_BASE             0xFA100000 /* Control/Status Registers       */
  90 #define CONFIG_SYS_PCIMEM_BASE          0x80000000 /* PCI I/O and Memory Spaces      */
  91 #define CONFIG_SYS_PCIMEM_OR            0xA0000108
  92 #define CONFIG_SYS_PCIBRIDGE_BASE       0xFA210000 /* PCI-Bus Bridge Registers       */
  93 #define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108
  94
  95 /*-----------------------------------------------------------------------
  96  * Definitions for initial stack pointer and data area (in DPRAM)
  97  */
  98 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
  99 #define CONFIG_SYS_INIT_RAM_END 0x2f00  /* End of used area in DPRAM    */
 100 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 101 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 102 #define CONFIG_SYS_INIT_VPD_SIZE        256 /* size in bytes reserved for vpd buffer */
 103 #define CONFIG_SYS_INIT_VPD_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
 104 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_VPD_OFFSET-8)
 105
 106 /*-----------------------------------------------------------------------
 107  * Offset in DPMEM where we keep the VPD data
 108  */
 109 #define CONFIG_SYS_DPRAMVPD             (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000)
 110
 111 /*-----------------------------------------------------------------------
 112  * Start addresses for the final memory configuration
 113  * (Set up by the startup code)
 114  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 115  */
 116 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 117 #define CONFIG_SYS_FLASH_BASE           0x00000000
 118 /*0xFE000000*/
 119 #define CONFIG_SYS_FLASH_SIZE           ((uint)(8 * 1024 * 1024))       /* max 8Mbyte */
 120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 121 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 122 #define CONFIG_SYS_HWINFO_ADDR          (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_SYS_HWINFO_LEN)
 123 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc()  */
 124
 125 /*
 126  * For booting Linux, the board info and command line data
 127  * have to be in the first 8 MB of memory, since this is
 128  * the maximum mapped by the Linux kernel during initialization.
 129  */
 130 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 131
 132 /*-----------------------------------------------------------------------
 133  * FLASH organization
 134  */
 135 #define CONFIG_SYS_MAX_FLASH_BANKS      4       /* max number of memory banks           */
 136 #define CONFIG_SYS_MAX_FLASH_SECT       16      /* max number of sectors on one chip    */
 137
 138 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 139 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 140
 141 /*-----------------------------------------------------------------------
 142  * NVRAM Configuration
 143  *
 144  * Note: the MBX is special because there is already a firmware on this
 145  * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
 146  * access the NVRAM at the offset 0x1000.
 147  */
 148 #define CONFIG_ENV_IS_IN_NVRAM  1       /* turn on NVRAM env feature */
 149 #define CONFIG_ENV_ADDR         (CONFIG_SYS_NVRAM_BASE + 0x1000)
 150 #define CONFIG_ENV_SIZE         0x1000
 151
 152 /*-----------------------------------------------------------------------
 153  * Cache Configuration
 154  */
 155 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 156 #if defined(CONFIG_CMD_KGDB)
 157 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 158 #endif
 159
 160 /*-----------------------------------------------------------------------
 161  * SYPCR - System Protection Control                            11-9
 162  * SYPCR can only be written once after reset!
 163  *-----------------------------------------------------------------------
 164  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 165  */
 166 #if defined(CONFIG_WATCHDOG)
 167 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 168                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 169 #else
 170 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 171 #endif
 172
 173 /*-----------------------------------------------------------------------
 174  * SIUMCR - SIU Module Configuration                            11-6
 175  *-----------------------------------------------------------------------
 176  * PCMCIA config., multi-function pin tri-state
 177  */
 178 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME)
 179
 180 /*-----------------------------------------------------------------------
 181  * TBSCR - Time Base Status and Control                         11-26
 182  *-----------------------------------------------------------------------
 183  * Clear Reference Interrupt Status, Timebase freezing enabled
 184  */
 185 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 186
 187 /*-----------------------------------------------------------------------
 188  * PISCR - Periodic Interrupt Status and Control                11-31
 189  *-----------------------------------------------------------------------
 190  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 191  */
 192 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF | PISCR_PTE)
 193
 194 /*-----------------------------------------------------------------------
 195  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 196  *-----------------------------------------------------------------------
 197  * Reset PLL lock status sticky bit, timer expired status bit and timer
 198  * interrupt status bit - leave PLL multiplication factor unchanged !
 199  */
 200 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 201
 202 /*-----------------------------------------------------------------------
 203  * SCCR - System Clock and reset Control Register               15-27
 204  *-----------------------------------------------------------------------
 205  * Set clock output, timebase and RTC source and divider,
 206  * power management and some other internal clocks
 207  */
 208 #define SCCR_MASK       (SCCR_RTDIV | SCCR_RTSEL)
 209 #define CONFIG_SYS_SCCR SCCR_TBS
 210
 211  /*-----------------------------------------------------------------------
 212  *
 213  *-----------------------------------------------------------------------
 214  *
 215  */
 216 #define CONFIG_SYS_DER          0
 217
 218 /* Because of the way the 860 starts up and assigns CS0 the
 219 * entire address space, we have to set the memory controller
 220 * differently.  Normally, you write the option register
 221 * first, and then enable the chip select by writing the
 222 * base register.  For CS0, you must write the base register
 223 * first, followed by the option register.
 224 */
 225
 226 /*
 227  * Init Memory Controller:
 228  *
 229  * BR0/1 and OR0/1 (FLASH)
 230  */
 231 /* the other CS:s are determined by looking at parameters in BCSRx */
 232
 233
 234 #define BCSR_ADDR               ((uint) 0xFF010000)
 235 #define BCSR_SIZE               ((uint)(64 * 1024))
 236
 237 #define FLASH_BASE0_PRELIM      0xFE000000      /* FLASH bank #0        */
 238 #define FLASH_BASE1_PRELIM      0xFF010000      /* FLASH bank #0        */
 239
 240 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 241 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF00000      /* OR addr mask */
 242
 243 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 244 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 245
 246 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 247 #define CONFIG_SYS_OR0_PRELIM   (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
 248 #define CONFIG_SYS_BR0_PRELIM   (0xFE000000 | BR_V )
 249
 250 /* BCSRx - Board Control and Status Registers */
 251 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 252 #define CONFIG_SYS_OR1_PRELIM   0xFFC00000 | OR_ACS_DIV4
 253 #define CONFIG_SYS_BR1_PRELIM   (0x00000000 | BR_MS_UPMA | BR_V )
 254
 255
 256 /*
 257  * Memory Periodic Timer Prescaler
 258  */
 259
 260 /* periodic timer for refresh */
 261 #define CONFIG_SYS_MAMR_PTA             97              /* start with divider for 100 MHz       */
 262
 263 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 264 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 265 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 266
 267 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 268 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 269 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 270
 271 /*
 272  * MAMR settings for SDRAM
 273  */
 274
 275 /* 8 column SDRAM */
 276 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 277                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 278                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 279 /* 9 column SDRAM */
 280 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 281                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 282                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 283
 284 #define CONFIG_SYS_MAMR         0x13821000
 285 /*
 286  * Internal Definitions
 287  *
 288  * Boot Flags
 289  */
 290 #define BOOTFLAG_COLD                   0x01            /* Normal Power-On: Boot from FLASH     */
 291 #define BOOTFLAG_WARM                   0x02            /* Software reboot                      */
 292
 293
 294 /* values according to the manual */
 295
 296
 297 #define PCMCIA_MEM_ADDR         ((uint)0xff020000)
 298 #define PCMCIA_MEM_SIZE         ((uint)(64 * 1024))
 299
 300 #define BCSR0                   ((uint) (BCSR_ADDR + 00))
 301 #define BCSR1                   ((uint) (BCSR_ADDR + 0x04))
 302 #define BCSR2                   ((uint) (BCSR_ADDR + 0x08))
 303 #define BCSR3                   ((uint) (BCSR_ADDR + 0x0c))
 304 #define BCSR4                   ((uint) (BCSR_ADDR + 0x10))
 305
 306 /* FADS bitvalues by Helmut Buchsbaum
 307  * see MPC8xxADS User's Manual for a proper description
 308  * of the following structures
 309  */
 310
 311 #define BCSR0_ERB       ((uint)0x80000000)
 312 #define BCSR0_IP        ((uint)0x40000000)
 313 #define BCSR0_BDIS      ((uint)0x10000000)
 314 #define BCSR0_BPS_MASK  ((uint)0x0C000000)
 315 #define BCSR0_ISB_MASK  ((uint)0x01800000)
 316 #define BCSR0_DBGC_MASK ((uint)0x00600000)
 317 #define BCSR0_DBPC_MASK ((uint)0x00180000)
 318 #define BCSR0_EBDF_MASK ((uint)0x00060000)
 319
 320 #define BCSR1_FLASH_EN           ((uint)0x80000000)
 321 #define BCSR1_DRAM_EN            ((uint)0x40000000)
 322 #define BCSR1_ETHEN              ((uint)0x20000000)
 323 #define BCSR1_IRDEN              ((uint)0x10000000)
 324 #define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
 325 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
 326 #define BCSR1_BCSR_EN            ((uint)0x02000000)
 327 #define BCSR1_RS232EN_1          ((uint)0x01000000)
 328 #define BCSR1_PCCEN              ((uint)0x00800000)
 329 #define BCSR1_PCCVCC0            ((uint)0x00400000)
 330 #define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
 331 #define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
 332 #define BCSR1_RS232EN_2          ((uint)0x00040000)
 333 #define BCSR1_SDRAM_EN           ((uint)0x00020000)
 334 #define BCSR1_PCCVCC1            ((uint)0x00010000)
 335
 336 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
 337 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 338 #define BCSR2_DRAM_PD_SHIFT      (23)
 339 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
 340 #define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
 341
 342 #define BCSR3_DBID_MASK          ((ushort)0x3800)
 343 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
 344 #define BCSR3_BREVNR0            ((ushort)0x0080)
 345 #define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
 346 #define BCSR3_BREVN1             ((ushort)0x0008)
 347 #define BCSR3_BREVN2_MASK        ((ushort)0x0003)
 348
 349 #define BCSR4_ETHLOOP            ((uint)0x80000000)
 350 #define BCSR4_TFPLDL             ((uint)0x40000000)
 351 #define BCSR4_TPSQEL             ((uint)0x20000000)
 352 #define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
 353 #ifdef CONFIG_MPC823
 354 #define BCSR4_USB_EN             ((uint)0x08000000)
 355 #endif /* CONFIG_MPC823 */
 356 #ifdef CONFIG_MPC860SAR
 357 #define BCSR4_UTOPIA_EN          ((uint)0x08000000)
 358 #endif /* CONFIG_MPC860SAR */
 359 #ifdef CONFIG_MPC860T
 360 #define BCSR4_FETH_EN            ((uint)0x08000000)
 361 #endif /* CONFIG_MPC860T */
 362 #define BCSR4_USB_SPEED          ((uint)0x04000000)
 363 #define BCSR4_VCCO               ((uint)0x02000000)
 364 #define BCSR4_VIDEO_ON           ((uint)0x00800000)
 365 #define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
 366 #define BCSR4_VIDEO_RST          ((uint)0x00200000)
 367 #define BCSR4_MODEM_EN           ((uint)0x00100000)
 368 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 369
 370 #define CONFIG_DRAM_40MHZ               1
 371
 372 #ifdef CONFIG_MPC860T
 373
 374 /* Interrupt level assignments.
 375 */
 376 #define FEC_INTERRUPT   SIU_LEVEL1      /* FEC interrupt */
 377
 378 #endif /* CONFIG_MPC860T */
 379
 380 /* We don't use the 8259.
 381 */
 382 #define NR_8259_INTS    0
 383
 384 #define CONFIG_CMD_NET
 385 /*
 386  * MPC8xx CPM Options
 387  */
 388 #define CONFIG_SCC_ENET 1
 389 #define CONFIG_SCC1_ENET 1
 390 #define CONFIG_FEC_ENET 1
 391 #undef  CONFIG_CPM_IIC
 392 #undef  CONFIG_UCODE_PATCH
 393
 394
 395 #define CONFIG_DISK_SPINUP_TIME 1000000
 396
 397
 398 /* PCMCIA configuration */
 399
 400 #define PCMCIA_MAX_SLOTS    2
 401
 402 #ifdef CONFIG_MPC860
 403 #define PCMCIA_SLOT_A 1
 404 #endif
 405
 406 #endif  /* __CONFIG_H */