include/configs/MERGERBOX.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * Copyright (C) 2011 Matrix Vision GmbH
   5  * Andre Schwarz <andre.schwarz@matrix-vision.de>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __CONFIG_H
  24 #define __CONFIG_H
  25
  26 #include <version.h>
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_E300     1
  32 #define CONFIG_MPC83xx  1
  33 #define CONFIG_MPC837x  1
  34 #define CONFIG_MPC8377  1
  35
  36 #define CONFIG_SYS_TEXT_BASE    0xFC000000
  37
  38 #define CONFIG_PCI      1
  39 #define CONFIG_PCI_INDIRECT_BRIDGE 1
  40
  41 #define CONFIG_MASK_AER_AO
  42 #define CONFIG_DISPLAY_AER_FULL
  43
  44 #define CONFIG_MISC_INIT_R
  45
  46 /*
  47  * On-board devices
  48  */
  49 #define CONFIG_TSEC_ENET
  50
  51 /*
  52  * System Clock Setup
  53  */
  54 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  55 #define CONFIG_PCIE
  56 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
  57 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  58
  59 /*
  60  * Hardware Reset Configuration Word stored in EEPROM.
  61  */
  62 #define CONFIG_SYS_HRCW_LOW     0
  63 #define CONFIG_SYS_HRCW_HIGH    0
  64
  65 /* Arbiter Configuration Register */
  66 #define CONFIG_SYS_ACR_PIPE_DEP 3
  67 #define CONFIG_SYS_ACR_RPTCNT   3
  68
  69 /* System Priority Control Regsiter */
  70 #define CONFIG_SYS_SPCR_TSECEP  3
  71
  72 /* System Clock Configuration Register */
  73 #define CONFIG_SYS_SCCR_TSEC1CM         3
  74 #define CONFIG_SYS_SCCR_TSEC2CM         0
  75 #define CONFIG_SYS_SCCR_SDHCCM          3
  76 #define CONFIG_SYS_SCCR_ENCCM           3 /* also clock for I2C-1 */
  77 #define CONFIG_SYS_SCCR_USBDRCM         CONFIG_SYS_SCCR_ENCCM /* must match */
  78 #define CONFIG_SYS_SCCR_PCIEXP1CM       3
  79 #define CONFIG_SYS_SCCR_PCIEXP2CM       3
  80 #define CONFIG_SYS_SCCR_PCICM           1
  81 #define CONFIG_SYS_SCCR_SATACM          0xFF
  82
  83 /*
  84  * System IO Config
  85  */
  86 #define CONFIG_SYS_SICRH        0x087c0000
  87 #define CONFIG_SYS_SICRL        0x40000000
  88
  89 /*
  90  * Output Buffer Impedance
  91  */
  92 #define CONFIG_SYS_OBIR         0x30000000
  93
  94 /*
  95  * IMMR new address
  96  */
  97 #define CONFIG_SYS_IMMR         0xE0000000
  98
  99 /*
 100  * DDR Setup
 101  */
 102 #define CONFIG_SYS_DDR_BASE             0x00000000
 103 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 104 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 105 #define CONFIG_SYS_83XX_DDR_USES_CS0
 106
 107 #define CONFIG_SYS_DDRCDR_VALUE         (DDRCDR_EN | DDRCDR_PZ_HIZ |\
 108                                          DDRCDR_NZ_HIZ | DDRCDR_ODT |\
 109                                          DDRCDR_Q_DRN)
 110
 111 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 112
 113 #define CONFIG_SYS_DDR_MODE_WEAK
 114 #define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2
 115 #define CONFIG_SYS_DDR_CPO      0x1f
 116
 117 /* SPD table located at offset 0x20 in extended adressing ROM
 118  * used for HRCW fetch after power-on reset
 119  */
 120 #define CONFIG_SPD_EEPROM
 121 #define SPD_EEPROM_ADDRESS      0x50
 122 #define SPD_EEPROM_OFFSET       0x20
 123 #define SPD_EEPROM_ADDR_LEN     2
 124
 125 /*
 126  * The reserved memory
 127  */
 128 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 129 #define CONFIG_SYS_MONITOR_LEN          (512*1024)
 130 #define CONFIG_SYS_MALLOC_LEN           (512*1024)
 131
 132 /*
 133  * Initial RAM Base Address Setup
 134  */
 135 #define CONFIG_SYS_INIT_RAM_LOCK        1
 136 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 137 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
 138 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 139 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE -\
 140                                          CONFIG_SYS_GBL_DATA_SIZE)
 141
 142 /*
 143  * Local Bus Configuration & Clock Setup
 144  */
 145 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 146 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 147 #define CONFIG_SYS_LBC_LBCR     0x00000000
 148 #define CONFIG_FSL_ELBC         1
 149
 150 /*
 151  * FLASH on the Local Bus
 152  */
 153 #define CONFIG_SYS_FLASH_CFI
 154 #define CONFIG_FLASH_CFI_DRIVER
 155 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 156
 157 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE
 158 #define CONFIG_SYS_FLASH_SIZE           64
 159
 160 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 161 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 162
 163 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
 164                                  BR_MS_GPCM | BR_V)
 165 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
 166                                  OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
 167                                  OR_GPCM_XACS | OR_GPCM_SCY_15 |\
 168                                  OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
 169                                  OR_GPCM_EAD)
 170
 171 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 172 #define CONFIG_SYS_MAX_FLASH_SECT       512
 173
 174 #undef CONFIG_SYS_FLASH_CHECKSUM
 175 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000 /* Flash Erase Timeout (ms) */
 176 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 177
 178 /*
 179  * NAND Flash on the Local Bus
 180  */
 181 #define CONFIG_MTD_NAND_VERIFY_WRITE    1
 182 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 183 #define CONFIG_NAND_FSL_ELBC            1
 184
 185 #define CONFIG_SYS_NAND_BASE    0xE0600000
 186 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
 187                                  BR_PS_8 | BR_MS_FCM | BR_V)
 188 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
 189                                  OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
 190                                  OR_FCM_TRLX | OR_FCM_EHTR)
 191
 192 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 193 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 194
 195 /*
 196  * Serial Port
 197  */
 198 #define CONFIG_CONS_INDEX       1
 199 #define CONFIG_SYS_NS16550
 200 #define CONFIG_SYS_NS16550_SERIAL
 201 #define CONFIG_SYS_NS16550_REG_SIZE     1
 202 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 203
 204 #define CONFIG_SYS_BAUDRATE_TABLE \
 205         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 206
 207 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 208 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 209
 210 #define CONFIG_CONSOLE          ttyS0
 211 #define CONFIG_BAUDRATE         115200
 212
 213 /* SERDES */
 214 #define CONFIG_FSL_SERDES
 215 #define CONFIG_FSL_SERDES1      0xe3000
 216 #define CONFIG_FSL_SERDES2      0xe3100
 217
 218 /* Use the HUSH parser */
 219 #define CONFIG_SYS_HUSH_PARSER
 220
 221 /* Pass open firmware flat tree */
 222 #define CONFIG_OF_LIBFDT        1
 223 #define CONFIG_OF_BOARD_SETUP   1
 224 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
 225
 226 /* I2C */
 227 #define CONFIG_SYS_I2C
 228 #define CONFIG_SYS_I2C_FSL
 229 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 230 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 231 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 232 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 233 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 234 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 235
 236 /*
 237  * General PCI
 238  * Addresses are mapped 1-1.
 239  */
 240 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 241 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 242 #define CONFIG_SYS_PCI_MEM_SIZE         (256 << 20)
 243 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 244 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 245 #define CONFIG_SYS_PCI_MMIO_SIZE        (256 << 20)
 246 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 247 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 248 #define CONFIG_SYS_PCI_IO_SIZE          (1 << 20)
 249
 250 #ifdef CONFIG_PCIE
 251 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 252 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 253 #define CONFIG_SYS_PCIE1_CFG_SIZE       (128 << 20)
 254 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 255 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 256 #define CONFIG_SYS_PCIE1_MEM_SIZE       (256 << 20)
 257 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 258 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 259 #define CONFIG_SYS_PCIE1_IO_SIZE        (8 << 20)
 260
 261 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 262 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 263 #define CONFIG_SYS_PCIE2_CFG_SIZE       (128 << 20)
 264 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 265 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 266 #define CONFIG_SYS_PCIE2_MEM_SIZE       (256 << 20)
 267 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 268 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 269 #define CONFIG_SYS_PCIE2_IO_SIZE        (8 << 20)
 270 #endif
 271
 272 #define CONFIG_PCI_PNP
 273 #define CONFIG_PCI_SCAN_SHOW
 274 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 275
 276 /*
 277  * TSEC
 278  */
 279 #define CONFIG_GMII                     /* MII PHY management */
 280 #define CONFIG_SYS_VSC8601_SKEWFIX
 281 #define CONFIG_SYS_VSC8601_SKEW_TX      3
 282 #define CONFIG_SYS_VSC8601_SKEW_RX      3
 283
 284 #define CONFIG_TSEC1
 285 #define CONFIG_HAS_ETH0
 286 #define CONFIG_TSEC1_NAME               "TSEC0"
 287 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 288 #define TSEC1_PHY_ADDR                  0x10
 289 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 290 #define TSEC1_PHYIDX                    0
 291
 292 #define CONFIG_ETHPRIME                 "TSEC0"
 293 #define CONFIG_HAS_ETH0
 294
 295 /*
 296  * SATA
 297  */
 298 #define CONFIG_LIBATA
 299 #define CONFIG_FSL_SATA
 300
 301 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 302 #define CONFIG_SATA1
 303 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 304 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 305 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 306 #define CONFIG_SATA2
 307 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 308 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 309 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 310
 311 #define CONFIG_LBA48
 312 #define CONFIG_CMD_SATA
 313 #define CONFIG_DOS_PARTITION
 314 #define CONFIG_CMD_EXT2
 315
 316 /*
 317  * BOOTP options
 318  */
 319 #define CONFIG_BOOTP_BOOTFILESIZE
 320 #define CONFIG_BOOTP_BOOTPATH
 321 #define CONFIG_BOOTP_GATEWAY
 322 #define CONFIG_BOOTP_HOSTNAME
 323 #define CONFIG_BOOTP_VENDOREX
 324 #define CONFIG_BOOTP_SUBNETMASK
 325 #define CONFIG_BOOTP_DNS
 326 #define CONFIG_BOOTP_DNS2
 327 #define CONFIG_BOOTP_NTPSERVER
 328 #define CONFIG_BOOTP_RANDOM_DELAY
 329 #define CONFIG_BOOTP_SEND_HOSTNAME
 330
 331 /*
 332  * Command line configuration.
 333  */
 334 #include <config_cmd_default.h>
 335
 336 #define CONFIG_CMD_ASKENV
 337 #define CONFIG_CMD_NAND
 338 #define CONFIG_CMD_PING
 339 #define CONFIG_CMD_EEPROM
 340 #define CONFIG_CMD_I2C
 341 #define CONFIG_CMD_MII
 342 #define CONFIG_CMD_PCI
 343 #define CONFIG_CMD_USB
 344 #define CONFIG_CMD_SPI
 345 #define CONFIG_CMD_DHCP
 346 #define CONFIG_CMD_UBI
 347 #define CONFIG_CMD_UBIFS
 348 #define CONFIG_CMD_MTDPARTS
 349 #define CONFIG_CMD_SATA
 350
 351 #define CONFIG_CMD_EXT2
 352 #define CONFIG_CMD_FAT
 353 #define CONFIG_CMD_JFFS2
 354
 355 #define CONFIG_RBTREE
 356 #define CONFIG_LZO
 357
 358 #define CONFIG_MTD_DEVICE
 359 #define CONFIG_MTD_PARTITIONS
 360
 361 #define CONFIG_FLASH_CFI_MTD
 362 #define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
 363 #define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
 364
 365 #define CONFIG_FIT
 366 #define CONFIG_FIT_VERBOSE      1
 367
 368 #define CONFIG_CMDLINE_EDITING  1
 369 #define CONFIG_AUTO_COMPLETE
 370
 371 /*
 372  * Miscellaneous configurable options
 373  */
 374 #define CONFIG_SYS_LONGHELP
 375 #define CONFIG_SYS_LOAD_ADDR    0x2000000
 376 #define CONFIG_LOADADDR         0x4000000
 377 #define CONFIG_SYS_PROMPT       "=> "
 378 #define CONFIG_SYS_CBSIZE       256
 379
 380 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 381 #define CONFIG_SYS_MAXARGS      16
 382 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 383 #define CONFIG_SYS_HZ           1000
 384
 385 #define CONFIG_LOADS_ECHO               1
 386 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1
 387
 388 #define CONFIG_SYS_MEMTEST_START        (60<<20)
 389 #define CONFIG_SYS_MEMTEST_END          (70<<20)
 390
 391 /*
 392  * For booting Linux, the board info and command line data
 393  * have to be in the first 256 MB of memory, since this is
 394  * the maximum mapped by the Linux kernel during initialization.
 395  */
 396 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 397
 398 /*
 399  * Core HID Setup
 400  */
 401 #define CONFIG_SYS_HID0_INIT    0x000000000
 402 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 403                                  HID0_ENABLE_INSTRUCTION_CACHE)
 404 #define CONFIG_SYS_HID2         HID2_HBE
 405
 406 /*
 407  * MMU Setup
 408  */
 409 #define CONFIG_HIGH_BATS        1
 410
 411 /* DDR: cache cacheable */
 412 #define CONFIG_SYS_SDRAM        CONFIG_SYS_SDRAM_BASE
 413
 414 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM | BATL_PP_RW |\
 415                                  BATL_MEMCOHERENCE)
 416 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
 417                                  BATU_VP)
 418 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 419 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 420
 421 /* unused */
 422 #define CONFIG_SYS_IBAT1L       (0)
 423 #define CONFIG_SYS_IBAT1U       (0)
 424 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 425 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 426
 427 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 428 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR | BATL_PP_RW |\
 429                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 430 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
 431                                  BATU_VP)
 432 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 433 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 434
 435 /* unused */
 436 #define CONFIG_SYS_IBAT3L       (0)
 437 #define CONFIG_SYS_IBAT3U       (0)
 438 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 439 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 440
 441 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 442 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
 443                                  BATL_MEMCOHERENCE)
 444 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
 445                                  BATU_VS | BATU_VP)
 446 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 447                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 448 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 449
 450 /* Stack in dcache: cacheable, no memory coherence */
 451 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 452 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
 453                                  BATU_VS | BATU_VP)
 454 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 455 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 456
 457 /* PCI MEM space: cacheable */
 458 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
 459                                  BATL_MEMCOHERENCE)
 460 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
 461                                  BATU_VS | BATU_VP)
 462 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 463 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 464
 465 /* PCI MMIO space: cache-inhibit and guarded */
 466 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
 467                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 468 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
 469                                  BATU_VS | BATU_VP)
 470 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 471 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 472
 473 /*
 474  * I2C EEPROM settings
 475  */
 476 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 477 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 478 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 479 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 480 #define CONFIG_SYS_EEPROM_SIZE                  0x4000
 481
 482 /*
 483  * Environment Configuration
 484  */
 485 #define CONFIG_SYS_FLASH_PROTECTION
 486 #define CONFIG_ENV_OVERWRITE
 487 #define CONFIG_ENV_IS_IN_FLASH  1
 488 #define CONFIG_ENV_ADDR         0xFFD00000
 489 #define CONFIG_ENV_SECT_SIZE    0x20000
 490 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 491
 492 /*
 493  * Video
 494  */
 495 #define CONFIG_VIDEO
 496 #define CONFIG_VIDEO_SM501_PCI
 497 #define VIDEO_FB_LITTLE_ENDIAN
 498 #define CONFIG_CMD_BMP
 499 #define CONFIG_VIDEO_SM501
 500 #define CONFIG_VIDEO_SM501_32BPP
 501 #define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
 502 #define CONFIG_CFB_CONSOLE
 503 #define CONFIG_VIDEO_LOGO
 504 #define CONFIG_VIDEO_BMP_LOGO
 505 #define CONFIG_VGA_AS_SINGLE_DEVICE
 506 #define CONFIG_SPLASH_SCREEN
 507 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 508 #define CONFIG_VIDEO_BMP_GZIP
 509 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
 510
 511 /*
 512  * SPI
 513  */
 514 #define CONFIG_MPC8XXX_SPI
 515
 516 /*
 517  * USB
 518  */
 519 #define CONFIG_SYS_USB_HOST
 520 #define CONFIG_USB_EHCI
 521 #define CONFIG_USB_EHCI_FSL
 522 #define CONFIG_HAS_FSL_DR_USB
 523 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 524
 525 #define CONFIG_USB_STORAGE
 526 #define CONFIG_USB_KEYBOARD
 527 /*
 528  *
 529  */
 530 #define CONFIG_BOOTDELAY        5
 531 #define CONFIG_AUTOBOOT_KEYED
 532 #define CONFIG_AUTOBOOT_STOP_STR        "s"
 533 #define CONFIG_ZERO_BOOTDELAY_CHECK
 534 #define CONFIG_RESET_TO_RETRY   1000
 535
 536 #define MV_CI           "MergerBox"
 537 #define MV_VCI          "MergerBox"
 538 #define MV_FPGA_DATA    0xfc100000
 539 #define MV_FPGA_SIZE    0x00200000
 540
 541 #define CONFIG_SHOW_BOOT_PROGRESS 1
 542
 543 #define MV_KERNEL_ADDR_RAM      0x02800000
 544 #define MV_DTB_ADDR_RAM         0x00600000
 545 #define MV_INITRD_ADDR_RAM      0x01000000
 546 #define MV_FITADDR              0xfc300000
 547 #define MV_SPLAH_ADDR           0xffe00000
 548
 549 #define CONFIG_BOOTCOMMAND      "run i2c_init;if test ${boot_sqfs} -eq 1;"\
 550                                 "then; run fitboot;else;run ubiboot;fi;"
 551 #define CONFIG_BOOTARGS         "console=ttyS0,115200n8"
 552
 553 #define CONFIG_EXTRA_ENV_SETTINGS \
 554         "console_nr=0\0"\
 555         "stdin=serial\0"\
 556         "stdout=serial\0"\
 557         "stderr=serial\0"\
 558         "boot_sqfs=1\0"\
 559         "usb_dr_mode=host\0"\
 560         "bootfile=MergerBox.fit\0"\
 561         "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
 562         "fpga=0\0"\
 563         "fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
 564         "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
 565         "mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
 566         "mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
 567         "mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
 568         "uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
 569         "fitaddr=" __stringify(MV_FITADDR) "\0"\
 570         "mv_version=" U_BOOT_VERSION "\0"\
 571         "mtdids=" MTDIDS_DEFAULT "\0"\
 572         "mtdparts=" MTDPARTS_DEFAULT "\0"\
 573         "dhcp_client_id=" MV_CI "\0"\
 574         "dhcp_vendor-class-identifier=" MV_VCI "\0"\
 575         "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
 576                 "protect off all;erase $uboota +0xC0000;"\
 577                 "cp.b $loadaddr $uboota $filesize\0"\
 578         "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
 579                 "cp.b $loadaddr $fpgadata $filesize\0"\
 580         "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
 581                 "cp.b $loadaddr $fitaddr $filesize\0"\
 582         "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
 583                 "rootfstype=squashfs\0"\
 584         "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
 585                 "rootfstype=ubifs\0"\
 586         "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
 587                 "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
 588         "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
 589         "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
 590         "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
 591         "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
 592         "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
 593                 "imxtract $fitaddr ramdisk $mv_initrd_ram;"\
 594                 "imxtract $fitaddr fdt $mv_dtb_ram\0"\
 595         "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
 596         "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
 597         "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
 598         "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
 599                 "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
 600                 "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
 601         "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
 602         "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
 603                 "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
 604         "splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
 605         ""
 606
 607 /*
 608  * FPGA
 609  */
 610 #define CONFIG_FPGA_COUNT       1
 611 #define CONFIG_FPGA
 612 #define CONFIG_FPGA_ALTERA
 613 #define CONFIG_FPGA_CYCLON2
 614
 615 #endif