include/configs/MERGERBOX.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * Copyright (C) 2011 Matrix Vision GmbH
   5  * Andre Schwarz <andre.schwarz@matrix-vision.de>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <version.h>
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300     1
  19 #define CONFIG_MPC83xx  1
  20 #define CONFIG_MPC837x  1
  21 #define CONFIG_MPC8377  1
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFC000000
  24
  25 #define CONFIG_PCI      1
  26 #define CONFIG_PCI_INDIRECT_BRIDGE 1
  27
  28 #define CONFIG_MASK_AER_AO
  29 #define CONFIG_DISPLAY_AER_FULL
  30
  31 #define CONFIG_MISC_INIT_R
  32
  33 /*
  34  * On-board devices
  35  */
  36 #define CONFIG_TSEC_ENET
  37
  38 /*
  39  * System Clock Setup
  40  */
  41 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  42 #define CONFIG_PCIE
  43 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
  44 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  45
  46 /*
  47  * Hardware Reset Configuration Word stored in EEPROM.
  48  */
  49 #define CONFIG_SYS_HRCW_LOW     0
  50 #define CONFIG_SYS_HRCW_HIGH    0
  51
  52 /* Arbiter Configuration Register */
  53 #define CONFIG_SYS_ACR_PIPE_DEP 3
  54 #define CONFIG_SYS_ACR_RPTCNT   3
  55
  56 /* System Priority Control Regsiter */
  57 #define CONFIG_SYS_SPCR_TSECEP  3
  58
  59 /* System Clock Configuration Register */
  60 #define CONFIG_SYS_SCCR_TSEC1CM         3
  61 #define CONFIG_SYS_SCCR_TSEC2CM         0
  62 #define CONFIG_SYS_SCCR_SDHCCM          3
  63 #define CONFIG_SYS_SCCR_ENCCM           3 /* also clock for I2C-1 */
  64 #define CONFIG_SYS_SCCR_USBDRCM         CONFIG_SYS_SCCR_ENCCM /* must match */
  65 #define CONFIG_SYS_SCCR_PCIEXP1CM       3
  66 #define CONFIG_SYS_SCCR_PCIEXP2CM       3
  67 #define CONFIG_SYS_SCCR_PCICM           1
  68 #define CONFIG_SYS_SCCR_SATACM          0xFF
  69
  70 /*
  71  * System IO Config
  72  */
  73 #define CONFIG_SYS_SICRH        0x087c0000
  74 #define CONFIG_SYS_SICRL        0x40000000
  75
  76 /*
  77  * Output Buffer Impedance
  78  */
  79 #define CONFIG_SYS_OBIR         0x30000000
  80
  81 /*
  82  * IMMR new address
  83  */
  84 #define CONFIG_SYS_IMMR         0xE0000000
  85
  86 /*
  87  * DDR Setup
  88  */
  89 #define CONFIG_SYS_DDR_BASE             0x00000000
  90 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  91 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  92 #define CONFIG_SYS_83XX_DDR_USES_CS0
  93
  94 #define CONFIG_SYS_DDRCDR_VALUE         (DDRCDR_EN | DDRCDR_PZ_HIZ |\
  95                                          DDRCDR_NZ_HIZ | DDRCDR_ODT |\
  96                                          DDRCDR_Q_DRN)
  97
  98 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  99
 100 #define CONFIG_SYS_DDR_MODE_WEAK
 101 #define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2
 102 #define CONFIG_SYS_DDR_CPO      0x1f
 103
 104 /* SPD table located at offset 0x20 in extended adressing ROM
 105  * used for HRCW fetch after power-on reset
 106  */
 107 #define CONFIG_SPD_EEPROM
 108 #define SPD_EEPROM_ADDRESS      0x50
 109 #define SPD_EEPROM_OFFSET       0x20
 110 #define SPD_EEPROM_ADDR_LEN     2
 111
 112 /*
 113  * The reserved memory
 114  */
 115 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 116 #define CONFIG_SYS_MONITOR_LEN          (512*1024)
 117 #define CONFIG_SYS_MALLOC_LEN           (512*1024)
 118
 119 /*
 120  * Initial RAM Base Address Setup
 121  */
 122 #define CONFIG_SYS_INIT_RAM_LOCK        1
 123 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 124 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
 125 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 126 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE -\
 127                                          CONFIG_SYS_GBL_DATA_SIZE)
 128
 129 /*
 130  * Local Bus Configuration & Clock Setup
 131  */
 132 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 133 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 134 #define CONFIG_SYS_LBC_LBCR     0x00000000
 135 #define CONFIG_FSL_ELBC         1
 136
 137 /*
 138  * FLASH on the Local Bus
 139  */
 140 #define CONFIG_SYS_FLASH_CFI
 141 #define CONFIG_FLASH_CFI_DRIVER
 142 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 143
 144 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE
 145 #define CONFIG_SYS_FLASH_SIZE           64
 146
 147 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 148 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 149
 150 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
 151                                  BR_MS_GPCM | BR_V)
 152 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
 153                                  OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
 154                                  OR_GPCM_XACS | OR_GPCM_SCY_15 |\
 155                                  OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
 156                                  OR_GPCM_EAD)
 157
 158 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 159 #define CONFIG_SYS_MAX_FLASH_SECT       512
 160
 161 #undef CONFIG_SYS_FLASH_CHECKSUM
 162 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000 /* Flash Erase Timeout (ms) */
 163 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 164
 165 /*
 166  * NAND Flash on the Local Bus
 167  */
 168 #define CONFIG_MTD_NAND_VERIFY_WRITE    1
 169 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 170 #define CONFIG_NAND_FSL_ELBC            1
 171
 172 #define CONFIG_SYS_NAND_BASE    0xE0600000
 173 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
 174                                  BR_PS_8 | BR_MS_FCM | BR_V)
 175 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
 176                                  OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
 177                                  OR_FCM_TRLX | OR_FCM_EHTR)
 178
 179 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 180 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 181
 182 /*
 183  * Serial Port
 184  */
 185 #define CONFIG_CONS_INDEX       1
 186 #define CONFIG_SYS_NS16550
 187 #define CONFIG_SYS_NS16550_SERIAL
 188 #define CONFIG_SYS_NS16550_REG_SIZE     1
 189 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 190
 191 #define CONFIG_SYS_BAUDRATE_TABLE \
 192         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 193
 194 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 195 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 196
 197 #define CONFIG_CONSOLE          ttyS0
 198 #define CONFIG_BAUDRATE         115200
 199
 200 /* SERDES */
 201 #define CONFIG_FSL_SERDES
 202 #define CONFIG_FSL_SERDES1      0xe3000
 203 #define CONFIG_FSL_SERDES2      0xe3100
 204
 205 /* Use the HUSH parser */
 206 #define CONFIG_SYS_HUSH_PARSER
 207
 208 /* Pass open firmware flat tree */
 209 #define CONFIG_OF_LIBFDT        1
 210 #define CONFIG_OF_BOARD_SETUP   1
 211 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
 212
 213 /* I2C */
 214 #define CONFIG_HARD_I2C
 215 #define CONFIG_FSL_I2C
 216 #define CONFIG_I2C_MULTI_BUS
 217 #define CONFIG_SYS_I2C_SPEED            120000
 218 #define CONFIG_SYS_I2C_SLAVE            0x7F
 219 #define CONFIG_SYS_I2C_OFFSET           0x3000
 220 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 221
 222 /*
 223  * General PCI
 224  * Addresses are mapped 1-1.
 225  */
 226 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 227 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 228 #define CONFIG_SYS_PCI_MEM_SIZE         (256 << 20)
 229 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 230 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 231 #define CONFIG_SYS_PCI_MMIO_SIZE        (256 << 20)
 232 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 233 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 234 #define CONFIG_SYS_PCI_IO_SIZE          (1 << 20)
 235
 236 #ifdef CONFIG_PCIE
 237 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 238 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 239 #define CONFIG_SYS_PCIE1_CFG_SIZE       (128 << 20)
 240 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 241 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 242 #define CONFIG_SYS_PCIE1_MEM_SIZE       (256 << 20)
 243 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 244 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 245 #define CONFIG_SYS_PCIE1_IO_SIZE        (8 << 20)
 246
 247 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 248 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 249 #define CONFIG_SYS_PCIE2_CFG_SIZE       (128 << 20)
 250 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 251 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 252 #define CONFIG_SYS_PCIE2_MEM_SIZE       (256 << 20)
 253 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 254 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 255 #define CONFIG_SYS_PCIE2_IO_SIZE        (8 << 20)
 256 #endif
 257
 258 #define CONFIG_PCI_PNP
 259 #define CONFIG_PCI_SCAN_SHOW
 260 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 261
 262 /*
 263  * TSEC
 264  */
 265 #define CONFIG_GMII                     /* MII PHY management */
 266 #define CONFIG_SYS_VSC8601_SKEWFIX
 267 #define CONFIG_SYS_VSC8601_SKEW_TX      3
 268 #define CONFIG_SYS_VSC8601_SKEW_RX      3
 269
 270 #define CONFIG_TSEC1
 271 #define CONFIG_HAS_ETH0
 272 #define CONFIG_TSEC1_NAME               "TSEC0"
 273 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 274 #define TSEC1_PHY_ADDR                  0x10
 275 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 276 #define TSEC1_PHYIDX                    0
 277
 278 #define CONFIG_ETHPRIME                 "TSEC0"
 279 #define CONFIG_HAS_ETH0
 280
 281 /*
 282  * SATA
 283  */
 284 #define CONFIG_LIBATA
 285 #define CONFIG_FSL_SATA
 286
 287 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 288 #define CONFIG_SATA1
 289 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 290 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 291 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 292 #define CONFIG_SATA2
 293 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 294 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 295 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 296
 297 #define CONFIG_LBA48
 298 #define CONFIG_CMD_SATA
 299 #define CONFIG_DOS_PARTITION
 300 #define CONFIG_CMD_EXT2
 301
 302 /*
 303  * BOOTP options
 304  */
 305 #define CONFIG_BOOTP_BOOTFILESIZE
 306 #define CONFIG_BOOTP_BOOTPATH
 307 #define CONFIG_BOOTP_GATEWAY
 308 #define CONFIG_BOOTP_HOSTNAME
 309 #define CONFIG_BOOTP_VENDOREX
 310 #define CONFIG_BOOTP_SUBNETMASK
 311 #define CONFIG_BOOTP_DNS
 312 #define CONFIG_BOOTP_DNS2
 313 #define CONFIG_BOOTP_NTPSERVER
 314 #define CONFIG_BOOTP_RANDOM_DELAY
 315 #define CONFIG_BOOTP_SEND_HOSTNAME
 316
 317 /*
 318  * Command line configuration.
 319  */
 320 #include <config_cmd_default.h>
 321
 322 #define CONFIG_CMD_ASKENV
 323 #define CONFIG_CMD_NAND
 324 #define CONFIG_CMD_PING
 325 #define CONFIG_CMD_EEPROM
 326 #define CONFIG_CMD_I2C
 327 #define CONFIG_CMD_MII
 328 #define CONFIG_CMD_PCI
 329 #define CONFIG_CMD_USB
 330 #define CONFIG_CMD_SPI
 331 #define CONFIG_CMD_DHCP
 332 #define CONFIG_CMD_UBI
 333 #define CONFIG_CMD_UBIFS
 334 #define CONFIG_CMD_MTDPARTS
 335 #define CONFIG_CMD_SATA
 336
 337 #define CONFIG_CMD_EXT2
 338 #define CONFIG_CMD_FAT
 339 #define CONFIG_CMD_JFFS2
 340
 341 #define CONFIG_RBTREE
 342 #define CONFIG_LZO
 343
 344 #define CONFIG_MTD_DEVICE
 345 #define CONFIG_MTD_PARTITIONS
 346
 347 #define CONFIG_FLASH_CFI_MTD
 348 #define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
 349 #define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
 350
 351 #define CONFIG_FIT
 352 #define CONFIG_FIT_VERBOSE      1
 353
 354 #define CONFIG_CMDLINE_EDITING  1
 355 #define CONFIG_AUTO_COMPLETE
 356
 357 /*
 358  * Miscellaneous configurable options
 359  */
 360 #define CONFIG_SYS_LONGHELP
 361 #define CONFIG_SYS_LOAD_ADDR    0x2000000
 362 #define CONFIG_LOADADDR         0x4000000
 363 #define CONFIG_SYS_PROMPT       "=> "
 364 #define CONFIG_SYS_CBSIZE       256
 365
 366 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 367 #define CONFIG_SYS_MAXARGS      16
 368 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 369 #define CONFIG_SYS_HZ           1000
 370
 371 #define CONFIG_LOADS_ECHO               1
 372 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1
 373
 374 #define CONFIG_SYS_MEMTEST_START        (60<<20)
 375 #define CONFIG_SYS_MEMTEST_END          (70<<20)
 376
 377 /*
 378  * For booting Linux, the board info and command line data
 379  * have to be in the first 256 MB of memory, since this is
 380  * the maximum mapped by the Linux kernel during initialization.
 381  */
 382 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 383
 384 /*
 385  * Core HID Setup
 386  */
 387 #define CONFIG_SYS_HID0_INIT    0x000000000
 388 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 389                                  HID0_ENABLE_INSTRUCTION_CACHE)
 390 #define CONFIG_SYS_HID2         HID2_HBE
 391
 392 /*
 393  * MMU Setup
 394  */
 395 #define CONFIG_HIGH_BATS        1
 396
 397 /* DDR: cache cacheable */
 398 #define CONFIG_SYS_SDRAM        CONFIG_SYS_SDRAM_BASE
 399
 400 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM | BATL_PP_RW |\
 401                                  BATL_MEMCOHERENCE)
 402 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
 403                                  BATU_VP)
 404 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 405 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 406
 407 /* unused */
 408 #define CONFIG_SYS_IBAT1L       (0)
 409 #define CONFIG_SYS_IBAT1U       (0)
 410 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 411 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 412
 413 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 414 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR | BATL_PP_RW |\
 415                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 416 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
 417                                  BATU_VP)
 418 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 419 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 420
 421 /* unused */
 422 #define CONFIG_SYS_IBAT3L       (0)
 423 #define CONFIG_SYS_IBAT3U       (0)
 424 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 425 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 426
 427 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 428 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
 429                                  BATL_MEMCOHERENCE)
 430 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
 431                                  BATU_VS | BATU_VP)
 432 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 433                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 434 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 435
 436 /* Stack in dcache: cacheable, no memory coherence */
 437 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 438 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
 439                                  BATU_VS | BATU_VP)
 440 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 441 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 442
 443 /* PCI MEM space: cacheable */
 444 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
 445                                  BATL_MEMCOHERENCE)
 446 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
 447                                  BATU_VS | BATU_VP)
 448 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 449 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 450
 451 /* PCI MMIO space: cache-inhibit and guarded */
 452 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
 453                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 454 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
 455                                  BATU_VS | BATU_VP)
 456 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 457 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 458
 459 /*
 460  * I2C EEPROM settings
 461  */
 462 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 463 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 464 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 465 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 466 #define CONFIG_SYS_EEPROM_SIZE                  0x4000
 467
 468 /*
 469  * Environment Configuration
 470  */
 471 #define CONFIG_SYS_FLASH_PROTECTION
 472 #define CONFIG_ENV_OVERWRITE
 473 #define CONFIG_ENV_IS_IN_FLASH  1
 474 #define CONFIG_ENV_ADDR         0xFFD00000
 475 #define CONFIG_ENV_SECT_SIZE    0x20000
 476 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 477
 478 /*
 479  * Video
 480  */
 481 #define CONFIG_VIDEO
 482 #define CONFIG_VIDEO_SM501_PCI
 483 #define VIDEO_FB_LITTLE_ENDIAN
 484 #define CONFIG_CMD_BMP
 485 #define CONFIG_VIDEO_SM501
 486 #define CONFIG_VIDEO_SM501_32BPP
 487 #define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
 488 #define CONFIG_CFB_CONSOLE
 489 #define CONFIG_VIDEO_LOGO
 490 #define CONFIG_VIDEO_BMP_LOGO
 491 #define CONFIG_VGA_AS_SINGLE_DEVICE
 492 #define CONFIG_SPLASH_SCREEN
 493 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 494 #define CONFIG_VIDEO_BMP_GZIP
 495 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
 496
 497 /*
 498  * SPI
 499  */
 500 #define CONFIG_MPC8XXX_SPI
 501
 502 /*
 503  * USB
 504  */
 505 #define CONFIG_SYS_USB_HOST
 506 #define CONFIG_USB_EHCI
 507 #define CONFIG_USB_EHCI_FSL
 508 #define CONFIG_HAS_FSL_DR_USB
 509 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 510
 511 #define CONFIG_USB_STORAGE
 512 #define CONFIG_USB_KEYBOARD
 513 /*
 514  *
 515  */
 516 #define CONFIG_BOOTDELAY        5
 517 #define CONFIG_AUTOBOOT_KEYED
 518 #define CONFIG_AUTOBOOT_STOP_STR        "s"
 519 #define CONFIG_ZERO_BOOTDELAY_CHECK
 520 #define CONFIG_RESET_TO_RETRY   1000
 521
 522 #define MV_CI           "MergerBox"
 523 #define MV_VCI          "MergerBox"
 524 #define MV_FPGA_DATA    0xfc100000
 525 #define MV_FPGA_SIZE    0x00200000
 526
 527 #define CONFIG_SHOW_BOOT_PROGRESS 1
 528
 529 #define MV_KERNEL_ADDR_RAM      0x02800000
 530 #define MV_DTB_ADDR_RAM         0x00600000
 531 #define MV_INITRD_ADDR_RAM      0x01000000
 532 #define MV_FITADDR              0xfc300000
 533 #define MV_SPLAH_ADDR           0xffe00000
 534
 535 #define CONFIG_BOOTCOMMAND      "run i2c_init;if test ${boot_sqfs} -eq 1;"\
 536                                 "then; run fitboot;else;run ubiboot;fi;"
 537 #define CONFIG_BOOTARGS         "console=ttyS0,115200n8"
 538
 539 #define CONFIG_EXTRA_ENV_SETTINGS \
 540         "console_nr=0\0"\
 541         "stdin=serial\0"\
 542         "stdout=serial\0"\
 543         "stderr=serial\0"\
 544         "boot_sqfs=1\0"\
 545         "usb_dr_mode=host\0"\
 546         "bootfile=MergerBox.fit\0"\
 547         "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
 548         "fpga=0\0"\
 549         "fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
 550         "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
 551         "mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
 552         "mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
 553         "mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
 554         "uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
 555         "fitaddr=" __stringify(MV_FITADDR) "\0"\
 556         "mv_version=" U_BOOT_VERSION "\0"\
 557         "mtdids=" MTDIDS_DEFAULT "\0"\
 558         "mtdparts=" MTDPARTS_DEFAULT "\0"\
 559         "dhcp_client_id=" MV_CI "\0"\
 560         "dhcp_vendor-class-identifier=" MV_VCI "\0"\
 561         "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
 562                 "protect off all;erase $uboota +0xC0000;"\
 563                 "cp.b $loadaddr $uboota $filesize\0"\
 564         "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
 565                 "cp.b $loadaddr $fpgadata $filesize\0"\
 566         "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
 567                 "cp.b $loadaddr $fitaddr $filesize\0"\
 568         "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
 569                 "rootfstype=squashfs\0"\
 570         "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
 571                 "rootfstype=ubifs\0"\
 572         "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
 573                 "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
 574         "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
 575         "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
 576         "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
 577         "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
 578         "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
 579                 "imxtract $fitaddr ramdisk $mv_initrd_ram;"\
 580                 "imxtract $fitaddr fdt $mv_dtb_ram\0"\
 581         "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
 582         "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
 583         "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
 584         "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
 585                 "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
 586                 "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
 587         "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
 588         "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
 589                 "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
 590         "splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
 591         ""
 592
 593 /*
 594  * FPGA
 595  */
 596 #define CONFIG_FPGA_COUNT       1
 597 #define CONFIG_FPGA
 598 #define CONFIG_FPGA_ALTERA
 599 #define CONFIG_FPGA_CYCLON2
 600
 601 #endif