include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /***********************************************************
  32  * High Level Configuration Options
  33  * (easy to change)
  34  ***********************************************************/
  35 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  36 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  37 #define CONFIG_MIP405           1       /* ...on a MIP405 board         */
  38
  39 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  40
  41 /***********************************************************
  42  * Note that it may also be a MIP405T board which is a subset of the
  43  * MIP405
  44  ***********************************************************/
  45 /***********************************************************
  46  * WARNING:
  47  * CONFIG_BOOT_PCI is only used for first boot-up and should
  48  * NOT be enabled for production bootloader
  49  ***********************************************************/
  50 /*#define        CONFIG_BOOT_PCI         1*/
  51 /***********************************************************
  52  * Clock
  53  ***********************************************************/
  54 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  55
  56
  57 /*
  58  * BOOTP options
  59  */
  60 #define CONFIG_BOOTP_BOOTFILESIZE
  61 #define CONFIG_BOOTP_BOOTPATH
  62 #define CONFIG_BOOTP_GATEWAY
  63 #define CONFIG_BOOTP_HOSTNAME
  64
  65
  66 /*
  67  * Command line configuration.
  68  */
  69 #include <config_cmd_default.h>
  70
  71 #define CONFIG_CMD_CACHE
  72 #define CONFIG_CMD_DATE
  73 #define CONFIG_CMD_DHCP
  74 #define CONFIG_CMD_EEPROM
  75 #define CONFIG_CMD_ELF
  76 #define CONFIG_CMD_FAT
  77 #define CONFIG_CMD_I2C
  78 #define CONFIG_CMD_IDE
  79 #define CONFIG_CMD_IRQ
  80 #define CONFIG_CMD_JFFS2
  81 #define CONFIG_CMD_MII
  82 #define CONFIG_CMD_PCI
  83 #define CONFIG_CMD_PING
  84 #define CONFIG_CMD_REGINFO
  85 #define CONFIG_CMD_SAVES
  86 #define CONFIG_CMD_BSP
  87
  88 #if !defined(CONFIG_MIP405T)
  89     #define CONFIG_CMD_USB
  90 #endif
  91
  92
  93 #define  CONFIG_SYS_HUSH_PARSER
  94 /**************************************************************
  95  * I2C Stuff:
  96  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  97  * 0x53.
  98  * The Atmel EEPROM uses 16Bit addressing.
  99  ***************************************************************/
 100
 101 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 102 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 103 #define CONFIG_SYS_I2C_SPEED            50000   /* I2C speed and slave address */
 104 #define CONFIG_SYS_I2C_SLAVE            0x7F
 105
 106 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x53    /* EEPROM 24C128/256            */
 107 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
 108 /* mask of address bits that overflow into the "EEPROM chip address"    */
 109 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 110 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel 24C128/256 has     */
 111                                         /* 64 byte page write mode using*/
 112                                         /* last 6 bits of the address   */
 113 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 114
 115
 116 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 117 #define CONFIG_ENV_OFFSET               0x00000 /* environment starts at the beginning of the EEPROM */
 118 #define CONFIG_ENV_SIZE         0x00800 /* 2k bytes may be used for env vars */
 119
 120 /***************************************************************
 121  * Definitions for Serial Presence Detect EEPROM address
 122  * (to get SDRAM settings)
 123  ***************************************************************/
 124 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
 125 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
 126 */
 127 /**************************************************************
 128  * Environment definitions
 129  **************************************************************/
 130 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 131 #define CONFIG_BOOTDELAY        5
 132 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 133 /* #define CONFIG_BOOT_RETRY_TIME       -10     /XXX* feature is available but not enabled */
 134 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 135
 136 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 137 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 138
 139 #define CONFIG_IPADDR           10.0.0.100
 140 #define CONFIG_SERVERIP         10.0.0.1
 141 #define CONFIG_PREBOOT
 142 /***************************************************************
 143  * defines if the console is stored in the environment
 144  ***************************************************************/
 145 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
 146 /***************************************************************
 147  * defines if an overwrite_console function exists
 148  *************************************************************/
 149 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 150 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 151 /***************************************************************
 152  * defines if the overwrite_console should be stored in the
 153  * environment
 154  **************************************************************/
 155 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 156
 157 /**************************************************************
 158  * loads config
 159  *************************************************************/
 160 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 161 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 162
 163 #define CONFIG_MISC_INIT_R
 164 /***********************************************************
 165  * Miscellaneous configurable options
 166  **********************************************************/
 167 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 168 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 169 #if defined(CONFIG_CMD_KGDB)
 170 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 171 #else
 172 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 173 #endif
 174 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 175 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 176 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 177
 178 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 179 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 1 ... 12 MB in DRAM  */
 180
 181 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 182 #define CONFIG_SYS_NS16550
 183 #define CONFIG_SYS_NS16550_SERIAL
 184 #define CONFIG_SYS_NS16550_REG_SIZE     1
 185 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 186
 187 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 188 #define CONFIG_SYS_BASE_BAUD       916667
 189
 190 /* The following table includes the supported baudrates */
 191 #define CONFIG_SYS_BAUDRATE_TABLE       \
 192         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 193          57600, 115200, 230400, 460800, 921600 }
 194
 195 #define CONFIG_SYS_LOAD_ADDR    0x400000        /* default load address */
 196 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 197
 198 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 199
 200 /*-----------------------------------------------------------------------
 201  * PCI stuff
 202  *-----------------------------------------------------------------------
 203  */
 204 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 205 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 206 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 207
 208 #define CONFIG_PCI                      /* include pci support          */
 209 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 210 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 211 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 212                                         /* resource configuration       */
 213 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 214 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 215 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 216 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 217 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 218 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 219 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 220 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 221
 222 /*-----------------------------------------------------------------------
 223  * Start addresses for the final memory configuration
 224  * (Set up by the startup code)
 225  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 226  */
 227 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 228 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 230 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 231 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 232
 233 /*
 234  * For booting Linux, the board info and command line data
 235  * have to be in the first 8 MB of memory, since this is
 236  * the maximum mapped by the Linux kernel during initialization.
 237  */
 238 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 239 /*-----------------------------------------------------------------------
 240  * FLASH organization
 241  */
 242 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 243 #define CONFIG_SYS_FLASH_PROTECTION
 244 #define CONFIG_SYS_FLASH_EMPTY_INFO
 245
 246 #define CONFIG_SYS_FLASH_CFI
 247 #define CONFIG_FLASH_CFI_DRIVER
 248
 249 #define CONFIG_FLASH_SHOW_PROGRESS      45
 250
 251 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 252 #define CONFIG_SYS_MAX_FLASH_SECT       256
 253
 254 /*
 255  * JFFS2 partitions
 256  *
 257  */
 258 /* No command line, one static partition, whole device */
 259 #undef CONFIG_CMD_MTDPARTS
 260 #define CONFIG_JFFS2_DEV                "nor0"
 261 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 262 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 263
 264 /* mtdparts command line support */
 265 /* Note: fake mtd_id used, no linux mtd map file */
 266 /*
 267 #define CONFIG_CMD_MTDPARTS
 268 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 269 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 270 */
 271
 272 /*-----------------------------------------------------------------------
 273  * Logbuffer Configuration
 274  */
 275 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 276 /*-----------------------------------------------------------------------
 277  * Bootcountlimit Configuration
 278  */
 279 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 280
 281 /*-----------------------------------------------------------------------
 282  * POST Configuration
 283  */
 284 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 285 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 286                                  CONFIG_SYS_POST_CPU            | \
 287                                  CONFIG_SYS_POST_RTC            | \
 288                                  CONFIG_SYS_POST_I2C)
 289
 290 #endif
 291 /*
 292  * Init Memory Controller:
 293  */
 294 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 295 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 296 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 297 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 298
 299 #define CONFIG_BOARD_EARLY_INIT_F 1
 300 #define CONFIG_BOARD_EARLY_INIT_R
 301
 302 /* Peripheral Bus Mapping */
 303 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 304 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 305 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 306
 307 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 308 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 309
 310
 311 /*-----------------------------------------------------------------------
 312  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 313  */
 314 #define CONFIG_SYS_TEMP_STACK_OCM      1
 315 #define CONFIG_SYS_OCM_DATA_ADDR        0xF0000000
 316 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 317 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
 318 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
 319 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 320 /* reserve some memory for POST and BOOT limit info */
 321 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 322
 323 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 324 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 325 #endif
 326
 327 /***********************************************************************
 328  * External peripheral base address
 329  ***********************************************************************/
 330 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 331
 332 /***********************************************************************
 333  * Last Stage Init
 334  ***********************************************************************/
 335 #define CONFIG_LAST_STAGE_INIT
 336 /************************************************************
 337  * Ethernet Stuff
 338  ***********************************************************/
 339 #define CONFIG_PPC4xx_EMAC
 340 #define CONFIG_MII              1       /* MII PHY management           */
 341 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 342 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 343 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 344 /************************************************************
 345  * RTC
 346  ***********************************************************/
 347 #define CONFIG_RTC_MC146818
 348 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 349
 350 /************************************************************
 351  * IDE/ATA stuff
 352  ************************************************************/
 353 #if defined(CONFIG_MIP405T)
 354 #define CONFIG_SYS_IDE_MAXBUS           1   /* MIP405T has only one IDE bus     */
 355 #else
 356 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 357 #endif
 358
 359 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 360
 361 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
 362 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01F0          /* ide0 offste */
 363 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170          /* ide1 offset */
 364 #define CONFIG_SYS_ATA_DATA_OFFSET      0               /* data reg offset      */
 365 #define CONFIG_SYS_ATA_REG_OFFSET       0               /* reg offset */
 366 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200           /* alternate register offset */
 367
 368 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 369 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 370 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 371 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 372 #define CONFIG_SUPPORT_VFAT
 373 /************************************************************
 374  * ATAPI support (experimental)
 375  ************************************************************/
 376 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 377
 378 /************************************************************
 379  * DISK Partition support
 380  ************************************************************/
 381 #define CONFIG_DOS_PARTITION
 382 #define CONFIG_MAC_PARTITION
 383 #define CONFIG_ISO_PARTITION /* Experimental */
 384
 385 /************************************************************
 386  * Keyboard support
 387  ************************************************************/
 388 #undef CONFIG_ISA_KEYBOARD
 389
 390 /************************************************************
 391  * Video support
 392  ************************************************************/
 393 #define CONFIG_VIDEO                    /*To enable video controller support */
 394 #define CONFIG_VIDEO_CT69000
 395 #define CONFIG_CFB_CONSOLE
 396 #define CONFIG_VIDEO_LOGO
 397 #define CONFIG_CONSOLE_EXTRA_INFO
 398 #define CONFIG_VGA_AS_SINGLE_DEVICE
 399 #define CONFIG_VIDEO_SW_CURSOR
 400 #undef CONFIG_VIDEO_ONBOARD
 401 /************************************************************
 402  * USB support EXPERIMENTAL
 403  ************************************************************/
 404 #if !defined(CONFIG_MIP405T)
 405 #define CONFIG_USB_UHCI
 406 #define CONFIG_USB_KEYBOARD
 407 #define CONFIG_USB_STORAGE
 408
 409 /* Enable needed helper functions */
 410 #define CONFIG_SYS_STDIO_DEREGISTER             /* needs stdio_deregister */
 411 #endif
 412 /************************************************************
 413  * Debug support
 414  ************************************************************/
 415 #if defined(CONFIG_CMD_KGDB)
 416 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 417 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 418 #endif
 419
 420 /************************************************************
 421  * support BZIP2 compression
 422  ************************************************************/
 423 #define CONFIG_BZIP2            1
 424
 425 /************************************************************
 426  * Ident
 427  ************************************************************/
 428
 429 #define VERSION_TAG "released"
 430 #if !defined(CONFIG_MIP405T)
 431 #define CONFIG_ISO_STRING "MEV-10072-001"
 432 #else
 433 #define CONFIG_ISO_STRING "MEV-10082-001"
 434 #endif
 435
 436 #if !defined(CONFIG_BOOT_PCI)
 437 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 438 #else
 439 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
 440 #endif
 441
 442
 443 #endif  /* __CONFIG_H */