include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /***********************************************************
  32  * High Level Configuration Options
  33  * (easy to change)
  34  ***********************************************************/
  35 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  36 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  37 #define CONFIG_MIP405           1       /* ...on a MIP405 board         */
  38 /***********************************************************
  39  * Note that it may also be a MIP405T board which is a subset of the
  40  * MIP405
  41  ***********************************************************/
  42 /***********************************************************
  43  * WARNING:
  44  * CONFIG_BOOT_PCI is only used for first boot-up and should
  45  * NOT be enabled for production bootloader
  46  ***********************************************************/
  47 /*#define        CONFIG_BOOT_PCI         1*/
  48 /***********************************************************
  49  * Clock
  50  ***********************************************************/
  51 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  52
  53
  54 /*
  55  * BOOTP options
  56  */
  57 #define CONFIG_BOOTP_BOOTFILESIZE
  58 #define CONFIG_BOOTP_BOOTPATH
  59 #define CONFIG_BOOTP_GATEWAY
  60 #define CONFIG_BOOTP_HOSTNAME
  61
  62
  63 /*
  64  * Command line configuration.
  65  */
  66 #include <config_cmd_default.h>
  67
  68 #define CONFIG_CMD_CACHE
  69 #define CONFIG_CMD_DATE
  70 #define CONFIG_CMD_DHCP
  71 #define CONFIG_CMD_EEPROM
  72 #define CONFIG_CMD_ELF
  73 #define CONFIG_CMD_FAT
  74 #define CONFIG_CMD_I2C
  75 #define CONFIG_CMD_IDE
  76 #define CONFIG_CMD_IRQ
  77 #define CONFIG_CMD_JFFS2
  78 #define CONFIG_CMD_MII
  79 #define CONFIG_CMD_PCI
  80 #define CONFIG_CMD_PING
  81 #define CONFIG_CMD_REGINFO
  82 #define CONFIG_CMD_SAVES
  83 #define CONFIG_CMD_BSP
  84
  85 #if !defined(CONFIG_MIP405T)
  86     #define CONFIG_CMD_USB
  87     #define CONFIG_CMD_DOC
  88 #endif
  89
  90
  91 #define CFG_NAND_LEGACY
  92
  93 #define  CFG_HUSH_PARSER
  94 #define  CFG_PROMPT_HUSH_PS2 "> "
  95 /**************************************************************
  96  * I2C Stuff:
  97  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  98  * 0x53.
  99  * The Atmel EEPROM uses 16Bit addressing.
 100  ***************************************************************/
 101
 102 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 103 #define CFG_I2C_SPEED           50000   /* I2C speed and slave address */
 104 #define CFG_I2C_SLAVE           0x7F
 105
 106 #define CFG_I2C_EEPROM_ADDR     0x53    /* EEPROM 24C128/256            */
 107 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 108 /* mask of address bits that overflow into the "EEPROM chip address"    */
 109 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
 110 #define CFG_EEPROM_PAGE_WRITE_BITS 6    /* The Atmel 24C128/256 has     */
 111                                         /* 64 byte page write mode using*/
 112                                         /* last 6 bits of the address   */
 113 #define CFG_EEPROM_PAGE_WRITE_ENABLE    /* enable Page write */
 114 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 115
 116
 117 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 118 #define CFG_ENV_OFFSET          0x00000 /* environment starts at the beginning of the EEPROM */
 119 #define CFG_ENV_SIZE            0x00800 /* 2k bytes may be used for env vars */
 120
 121 /***************************************************************
 122  * Definitions for Serial Presence Detect EEPROM address
 123  * (to get SDRAM settings)
 124  ***************************************************************/
 125 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
 126 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
 127 */
 128 /**************************************************************
 129  * Environment definitions
 130  **************************************************************/
 131 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 132 #define CONFIG_BOOTDELAY        5
 133 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 134 /* #define CONFIG_BOOT_RETRY_TIME       -10     /XXX* feature is available but not enabled */
 135 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 136
 137 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 138 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 139
 140 #define CONFIG_IPADDR           10.0.0.100
 141 #define CONFIG_SERVERIP         10.0.0.1
 142 #define CONFIG_PREBOOT
 143 /***************************************************************
 144  * defines if the console is stored in the environment
 145  ***************************************************************/
 146 #define CFG_CONSOLE_IS_IN_ENV   /* stdin, stdout and stderr are in evironment */
 147 /***************************************************************
 148  * defines if an overwrite_console function exists
 149  *************************************************************/
 150 #define CFG_CONSOLE_OVERWRITE_ROUTINE
 151 #define CFG_CONSOLE_INFO_QUIET
 152 /***************************************************************
 153  * defines if the overwrite_console should be stored in the
 154  * environment
 155  **************************************************************/
 156 #undef CFG_CONSOLE_ENV_OVERWRITE
 157
 158 /**************************************************************
 159  * loads config
 160  *************************************************************/
 161 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 162 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 163
 164 #define CONFIG_MISC_INIT_R
 165 /***********************************************************
 166  * Miscellaneous configurable options
 167  **********************************************************/
 168 #define CFG_LONGHELP                    /* undef to save memory         */
 169 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 170 #if defined(CONFIG_CMD_KGDB)
 171 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 172 #else
 173 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 174 #endif
 175 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 176 #define CFG_MAXARGS     16              /* max number of command args   */
 177 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 178
 179 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 180 #define CFG_MEMTEST_END         0x0C00000       /* 1 ... 12 MB in DRAM  */
 181
 182 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 183 #define CFG_BASE_BAUD       916667
 184
 185 /* The following table includes the supported baudrates */
 186 #define CFG_BAUDRATE_TABLE      \
 187         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 188          57600, 115200, 230400, 460800, 921600 }
 189
 190 #define CFG_LOAD_ADDR   0x400000        /* default load address */
 191 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 192
 193 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 194
 195 /*-----------------------------------------------------------------------
 196  * PCI stuff
 197  *-----------------------------------------------------------------------
 198  */
 199 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 200 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 201 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 202
 203 #define CONFIG_PCI                      /* include pci support          */
 204 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 205 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 206                                         /* resource configuration       */
 207 #define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 208 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 209 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 210 #define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 211 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 212 #define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
 213 #define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
 214 #define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 215
 216 /*-----------------------------------------------------------------------
 217  * Start addresses for the final memory configuration
 218  * (Set up by the startup code)
 219  * Please note that CFG_SDRAM_BASE _must_ start at 0
 220  */
 221 #define CFG_SDRAM_BASE          0x00000000
 222 #define CFG_FLASH_BASE          0xFFF80000
 223 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 224 #define CFG_MONITOR_LEN         (512 * 1024)    /* Reserve 512 kB for Monitor   */
 225 #define CFG_MALLOC_LEN          (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 226
 227 /*
 228  * For booting Linux, the board info and command line data
 229  * have to be in the first 8 MB of memory, since this is
 230  * the maximum mapped by the Linux kernel during initialization.
 231  */
 232 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 233 /*-----------------------------------------------------------------------
 234  * FLASH organization
 235  */
 236 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 237 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 238
 239 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 240 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 241
 242 /*
 243  * JFFS2 partitions
 244  *
 245  */
 246 /* No command line, one static partition, whole device */
 247 #undef CONFIG_JFFS2_CMDLINE
 248 #define CONFIG_JFFS2_DEV                "nor0"
 249 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 250 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 251
 252 /* mtdparts command line support */
 253 /* Note: fake mtd_id used, no linux mtd map file */
 254 /*
 255 #define CONFIG_JFFS2_CMDLINE
 256 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 257 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 258 */
 259
 260 /*-----------------------------------------------------------------------
 261  * Cache Configuration
 262  */
 263 #define CFG_DCACHE_SIZE         0x4000  /* For AMCC 405GPr CPUs                 */
 264 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 265 #if defined(CONFIG_CMD_KGDB)
 266 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 267 #endif
 268
 269 /*-----------------------------------------------------------------------
 270  * Logbuffer Configuration
 271  */
 272 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 273 /*-----------------------------------------------------------------------
 274  * Bootcountlimit Configuration
 275  */
 276 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 277
 278 /*-----------------------------------------------------------------------
 279  * POST Configuration
 280  */
 281 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 282 #define CONFIG_POST             (CFG_POST_MEMORY        | \
 283                                  CFG_POST_CPU           | \
 284                                  CFG_POST_RTC           | \
 285                                  CFG_POST_I2C)
 286
 287 #endif
 288 /*
 289  * Init Memory Controller:
 290  */
 291 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 292 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 293 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 294 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 295
 296 #define CONFIG_BOARD_EARLY_INIT_F 1
 297
 298 /* Peripheral Bus Mapping */
 299 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 300 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 301 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 302
 303 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 304 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 305
 306
 307 /*-----------------------------------------------------------------------
 308  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 309  */
 310 #define CFG_TEMP_STACK_OCM      1
 311 #define CFG_OCM_DATA_ADDR       0xF0000000
 312 #define CFG_OCM_DATA_SIZE       0x1000
 313 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR       /* inside of On Chip SRAM    */
 314 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE       /* End of On Chip SRAM         */
 315 #define CFG_GBL_DATA_SIZE       64              /* size in bytes reserved for initial data */
 316 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 317 /* reserve some memory for POST and BOOT limit info */
 318 #define CFG_INIT_SP_OFFSET      (CFG_GBL_DATA_OFFSET - 32)
 319
 320 #ifdef  CONFIG_POST             /* reserve one word for POST Info */
 321 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 4)
 322 #endif
 323
 324 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 325 #define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 12)
 326 #endif
 327
 328 /*
 329  * Internal Definitions
 330  *
 331  * Boot Flags
 332  */
 333 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 334 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 335
 336
 337 /***********************************************************************
 338  * External peripheral base address
 339  ***********************************************************************/
 340 #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
 341
 342 /***********************************************************************
 343  * Last Stage Init
 344  ***********************************************************************/
 345 #define CONFIG_LAST_STAGE_INIT
 346 /************************************************************
 347  * Ethernet Stuff
 348  ***********************************************************/
 349 #define CONFIG_MII              1       /* MII PHY management           */
 350 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 351 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 352 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 353 /************************************************************
 354  * RTC
 355  ***********************************************************/
 356 #define CONFIG_RTC_MC146818
 357 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 358
 359 /************************************************************
 360  * IDE/ATA stuff
 361  ************************************************************/
 362 #if defined(CONFIG_MIP405T)
 363 #define CFG_IDE_MAXBUS          1   /* MIP405T has only one IDE bus     */
 364 #else
 365 #define CFG_IDE_MAXBUS          2   /* max. 2 IDE busses        */
 366 #endif
 367
 368 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 369
 370 #define CFG_ATA_BASE_ADDR       CFG_ISA_IO_BASE_ADDRESS /* base address */
 371 #define CFG_ATA_IDE0_OFFSET     0x01F0          /* ide0 offste */
 372 #define CFG_ATA_IDE1_OFFSET     0x0170          /* ide1 offset */
 373 #define CFG_ATA_DATA_OFFSET     0               /* data reg offset      */
 374 #define CFG_ATA_REG_OFFSET      0               /* reg offset */
 375 #define CFG_ATA_ALT_OFFSET      0x200           /* alternate register offset */
 376
 377 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 378 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 379 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 380 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 381 #define CONFIG_SUPPORT_VFAT
 382 /************************************************************
 383  * ATAPI support (experimental)
 384  ************************************************************/
 385 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 386
 387 /************************************************************
 388  * DISK Partition support
 389  ************************************************************/
 390 #define CONFIG_DOS_PARTITION
 391 #define CONFIG_MAC_PARTITION
 392 #define CONFIG_ISO_PARTITION /* Experimental */
 393
 394 /************************************************************
 395  * Disk-On-Chip configuration
 396  ************************************************************/
 397 #define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices            */
 398 #define CFG_DOC_SHORT_TIMEOUT
 399 #define CFG_DOC_SUPPORT_2000
 400 #define CFG_DOC_SUPPORT_MILLENNIUM
 401 /************************************************************
 402  * Keyboard support
 403  ************************************************************/
 404 #undef CONFIG_ISA_KEYBOARD
 405
 406 /************************************************************
 407  * Video support
 408  ************************************************************/
 409 #define CONFIG_VIDEO                    /*To enable video controller support */
 410 #define CONFIG_VIDEO_CT69000
 411 #define CONFIG_CFB_CONSOLE
 412 #define CONFIG_VIDEO_LOGO
 413 #define CONFIG_CONSOLE_EXTRA_INFO
 414 #define CONFIG_VGA_AS_SINGLE_DEVICE
 415 #define CONFIG_VIDEO_SW_CURSOR
 416 #undef CONFIG_VIDEO_ONBOARD
 417 /************************************************************
 418  * USB support EXPERIMENTAL
 419  ************************************************************/
 420 #if !defined(CONFIG_MIP405T)
 421 #define CONFIG_USB_UHCI
 422 #define CONFIG_USB_KEYBOARD
 423 #define CONFIG_USB_STORAGE
 424
 425 /* Enable needed helper functions */
 426 #define CFG_DEVICE_DEREGISTER           /* needs device_deregister */
 427 #endif
 428 /************************************************************
 429  * Debug support
 430  ************************************************************/
 431 #if defined(CONFIG_CMD_KGDB)
 432 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 433 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 434 #endif
 435
 436 /************************************************************
 437  * support BZIP2 compression
 438  ************************************************************/
 439 #define CONFIG_BZIP2            1
 440
 441 /************************************************************
 442  * Ident
 443  ************************************************************/
 444
 445 #define VERSION_TAG "released"
 446 #if !defined(CONFIG_MIP405T)
 447 #define CONFIG_ISO_STRING "MEV-10072-001"
 448 #else
 449 #define CONFIG_ISO_STRING "MEV-10082-001"
 450 #endif
 451
 452 #if !defined(CONFIG_BOOT_PCI)
 453 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 454 #else
 455 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
 456 #endif
 457
 458
 459 #endif  /* __CONFIG_H */