include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /***********************************************************
  16  * High Level Configuration Options
  17  * (easy to change)
  18  ***********************************************************/
  19 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  20 #define CONFIG_MIP405           1       /* ...on a MIP405 board         */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  23
  24 #define CONFIG_SYS_GENERIC_BOARD
  25
  26 /***********************************************************
  27  * Note that it may also be a MIP405T board which is a subset of the
  28  * MIP405
  29  ***********************************************************/
  30 /***********************************************************
  31  * WARNING:
  32  * CONFIG_BOOT_PCI is only used for first boot-up and should
  33  * NOT be enabled for production bootloader
  34  ***********************************************************/
  35 /*#define        CONFIG_BOOT_PCI         1*/
  36 /***********************************************************
  37  * Clock
  38  ***********************************************************/
  39 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  40
  41
  42 /*
  43  * BOOTP options
  44  */
  45 #define CONFIG_BOOTP_BOOTFILESIZE
  46 #define CONFIG_BOOTP_BOOTPATH
  47 #define CONFIG_BOOTP_GATEWAY
  48 #define CONFIG_BOOTP_HOSTNAME
  49
  50
  51 /*
  52  * Command line configuration.
  53  */
  54 #define CONFIG_CMD_CACHE
  55 #define CONFIG_CMD_DATE
  56 #define CONFIG_CMD_DHCP
  57 #define CONFIG_CMD_EEPROM
  58 #define CONFIG_CMD_ELF
  59 #define CONFIG_CMD_FAT
  60 #define CONFIG_CMD_I2C
  61 #define CONFIG_CMD_IDE
  62 #define CONFIG_CMD_IRQ
  63 #define CONFIG_CMD_JFFS2
  64 #define CONFIG_CMD_MII
  65 #define CONFIG_CMD_PCI
  66 #define CONFIG_CMD_PING
  67 #define CONFIG_CMD_REGINFO
  68 #define CONFIG_CMD_SAVES
  69 #define CONFIG_CMD_BSP
  70
  71 #if !defined(CONFIG_MIP405T)
  72     #define CONFIG_CMD_USB
  73 #endif
  74
  75
  76 #define  CONFIG_SYS_HUSH_PARSER
  77 /**************************************************************
  78  * I2C Stuff:
  79  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  80  * 0x53.
  81  * The Atmel EEPROM uses 16Bit addressing.
  82  ***************************************************************/
  83
  84 #define CONFIG_SYS_I2C
  85 #define CONFIG_SYS_I2C_PPC4XX
  86 #define CONFIG_SYS_I2C_PPC4XX_CH0
  87 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           50000
  88 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
  89
  90 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x53    /* EEPROM 24C128/256            */
  91 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
  92 /* mask of address bits that overflow into the "EEPROM chip address"    */
  93 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  94 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel 24C128/256 has     */
  95                                         /* 64 byte page write mode using*/
  96                                         /* last 6 bits of the address   */
  97 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
  98
  99
 100 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 101 #define CONFIG_ENV_OFFSET               0x00000 /* environment starts at the beginning of the EEPROM */
 102 #define CONFIG_ENV_SIZE         0x00800 /* 2k bytes may be used for env vars */
 103
 104 /***************************************************************
 105  * Definitions for Serial Presence Detect EEPROM address
 106  * (to get SDRAM settings)
 107  ***************************************************************/
 108 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
 109 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
 110 */
 111 /**************************************************************
 112  * Environment definitions
 113  **************************************************************/
 114 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 115 #define CONFIG_BOOTDELAY        5
 116 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 117 /* #define CONFIG_BOOT_RETRY_TIME       -10     /XXX* feature is available but not enabled */
 118 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 119
 120 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 121 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 122
 123 #define CONFIG_IPADDR           10.0.0.100
 124 #define CONFIG_SERVERIP         10.0.0.1
 125 #define CONFIG_PREBOOT
 126 /***************************************************************
 127  * defines if the console is stored in the environment
 128  ***************************************************************/
 129 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* stdin, stdout and stderr are in evironment */
 130 /***************************************************************
 131  * defines if an overwrite_console function exists
 132  *************************************************************/
 133 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 134 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 135 /***************************************************************
 136  * defines if the overwrite_console should be stored in the
 137  * environment
 138  **************************************************************/
 139 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 140
 141 /**************************************************************
 142  * loads config
 143  *************************************************************/
 144 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 145 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 146
 147 #define CONFIG_MISC_INIT_R
 148 /***********************************************************
 149  * Miscellaneous configurable options
 150  **********************************************************/
 151 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 152 #if defined(CONFIG_CMD_KGDB)
 153 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 154 #else
 155 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 156 #endif
 157 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 158 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 159 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 160
 161 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 162 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 1 ... 12 MB in DRAM  */
 163
 164 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 165 #define CONFIG_SYS_NS16550
 166 #define CONFIG_SYS_NS16550_SERIAL
 167 #define CONFIG_SYS_NS16550_REG_SIZE     1
 168 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 169
 170 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 171 #define CONFIG_SYS_BASE_BAUD       916667
 172
 173 /* The following table includes the supported baudrates */
 174 #define CONFIG_SYS_BAUDRATE_TABLE       \
 175         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 176          57600, 115200, 230400, 460800, 921600 }
 177
 178 #define CONFIG_SYS_LOAD_ADDR    0x400000        /* default load address */
 179 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 180
 181 /*-----------------------------------------------------------------------
 182  * PCI stuff
 183  *-----------------------------------------------------------------------
 184  */
 185 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 186 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 187 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 188
 189 #define CONFIG_PCI                      /* include pci support          */
 190 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 191 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 192 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 193                                         /* resource configuration       */
 194 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 195 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 196 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 197 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 198 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 199 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 200 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 201 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 202
 203 /*-----------------------------------------------------------------------
 204  * Start addresses for the final memory configuration
 205  * (Set up by the startup code)
 206  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 207  */
 208 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 209 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 210 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 211 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 212 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 213
 214 /*
 215  * For booting Linux, the board info and command line data
 216  * have to be in the first 8 MB of memory, since this is
 217  * the maximum mapped by the Linux kernel during initialization.
 218  */
 219 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 220 /*-----------------------------------------------------------------------
 221  * FLASH organization
 222  */
 223 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 224 #define CONFIG_SYS_FLASH_PROTECTION
 225 #define CONFIG_SYS_FLASH_EMPTY_INFO
 226
 227 #define CONFIG_SYS_FLASH_CFI
 228 #define CONFIG_FLASH_CFI_DRIVER
 229
 230 #define CONFIG_FLASH_SHOW_PROGRESS      45
 231
 232 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 233 #define CONFIG_SYS_MAX_FLASH_SECT       256
 234
 235 /*
 236  * JFFS2 partitions
 237  *
 238  */
 239 /* No command line, one static partition, whole device */
 240 #undef CONFIG_CMD_MTDPARTS
 241 #define CONFIG_JFFS2_DEV                "nor0"
 242 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 243 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 244
 245 /* mtdparts command line support */
 246 /* Note: fake mtd_id used, no linux mtd map file */
 247 /*
 248 #define CONFIG_CMD_MTDPARTS
 249 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 250 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 251 */
 252
 253 /*-----------------------------------------------------------------------
 254  * Logbuffer Configuration
 255  */
 256 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 257 /*-----------------------------------------------------------------------
 258  * Bootcountlimit Configuration
 259  */
 260 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 261
 262 /*-----------------------------------------------------------------------
 263  * POST Configuration
 264  */
 265 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 266 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | \
 267                                  CONFIG_SYS_POST_CPU            | \
 268                                  CONFIG_SYS_POST_RTC            | \
 269                                  CONFIG_SYS_POST_I2C)
 270
 271 #endif
 272 /*
 273  * Init Memory Controller:
 274  */
 275 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 276 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 277 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 278 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 279
 280 #define CONFIG_BOARD_EARLY_INIT_F 1
 281 #define CONFIG_BOARD_EARLY_INIT_R
 282
 283 /* Peripheral Bus Mapping */
 284 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 285 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 286 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 287
 288 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 289 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 290
 291
 292 /*-----------------------------------------------------------------------
 293  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 294  */
 295 #define CONFIG_SYS_TEMP_STACK_OCM      1
 296 #define CONFIG_SYS_OCM_DATA_ADDR        0xF0000000
 297 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 298 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
 299 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
 300 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 301 /* reserve some memory for POST and BOOT limit info */
 302 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 303
 304 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 305 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 306 #endif
 307
 308 /***********************************************************************
 309  * External peripheral base address
 310  ***********************************************************************/
 311 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
 312
 313 /***********************************************************************
 314  * Last Stage Init
 315  ***********************************************************************/
 316 #define CONFIG_LAST_STAGE_INIT
 317 /************************************************************
 318  * Ethernet Stuff
 319  ***********************************************************/
 320 #define CONFIG_PPC4xx_EMAC
 321 #define CONFIG_MII              1       /* MII PHY management           */
 322 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 323 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 324 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 325 /************************************************************
 326  * RTC
 327  ***********************************************************/
 328 #define CONFIG_RTC_MC146818
 329 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 330
 331 /************************************************************
 332  * IDE/ATA stuff
 333  ************************************************************/
 334 #if defined(CONFIG_MIP405T)
 335 #define CONFIG_SYS_IDE_MAXBUS           1   /* MIP405T has only one IDE bus     */
 336 #else
 337 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 338 #endif
 339
 340 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 341
 342 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
 343 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01F0          /* ide0 offste */
 344 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170          /* ide1 offset */
 345 #define CONFIG_SYS_ATA_DATA_OFFSET      0               /* data reg offset      */
 346 #define CONFIG_SYS_ATA_REG_OFFSET       0               /* reg offset */
 347 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200           /* alternate register offset */
 348
 349 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 350 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 351 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 352 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 353 #define CONFIG_SUPPORT_VFAT
 354 /************************************************************
 355  * ATAPI support (experimental)
 356  ************************************************************/
 357 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 358
 359 /************************************************************
 360  * DISK Partition support
 361  ************************************************************/
 362 #define CONFIG_DOS_PARTITION
 363 #define CONFIG_MAC_PARTITION
 364 #define CONFIG_ISO_PARTITION /* Experimental */
 365
 366 /************************************************************
 367  * Keyboard support
 368  ************************************************************/
 369 #undef CONFIG_ISA_KEYBOARD
 370
 371 /************************************************************
 372  * Video support
 373  ************************************************************/
 374 #define CONFIG_VIDEO                    /*To enable video controller support */
 375 #define CONFIG_VIDEO_CT69000
 376 #define CONFIG_CFB_CONSOLE
 377 #define CONFIG_VIDEO_LOGO
 378 #define CONFIG_CONSOLE_EXTRA_INFO
 379 #define CONFIG_VGA_AS_SINGLE_DEVICE
 380 #define CONFIG_VIDEO_SW_CURSOR
 381 #undef CONFIG_VIDEO_ONBOARD
 382 /************************************************************
 383  * USB support EXPERIMENTAL
 384  ************************************************************/
 385 #if !defined(CONFIG_MIP405T)
 386 #define CONFIG_USB_UHCI
 387 #define CONFIG_USB_KEYBOARD
 388 #define CONFIG_USB_STORAGE
 389
 390 /* Enable needed helper functions */
 391 #define CONFIG_SYS_STDIO_DEREGISTER             /* needs stdio_deregister */
 392 #endif
 393 /************************************************************
 394  * Debug support
 395  ************************************************************/
 396 #if defined(CONFIG_CMD_KGDB)
 397 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 398 #endif
 399
 400 /************************************************************
 401  * support BZIP2 compression
 402  ************************************************************/
 403 #define CONFIG_BZIP2            1
 404
 405 /************************************************************
 406  * Ident
 407  ************************************************************/
 408
 409 #define VERSION_TAG "released"
 410 #if !defined(CONFIG_MIP405T)
 411 #define CONFIG_ISO_STRING "MEV-10072-001"
 412 #else
 413 #define CONFIG_ISO_STRING "MEV-10082-001"
 414 #endif
 415
 416 #if !defined(CONFIG_BOOT_PCI)
 417 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 418 #else
 419 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
 420 #endif
 421
 422
 423 #endif  /* __CONFIG_H */