include/configs/MIP405.h

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /***********************************************************
  32  * High Level Configuration Options
  33  * (easy to change)
  34  ***********************************************************/
  35 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  36 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  37 #define CONFIG_MIP405           1       /* ...on a MIP405 board         */
  38 /***********************************************************
  39  * Note that it may also be a MIP405T board which is a subset of the
  40  * MIP405
  41  ***********************************************************/
  42 /***********************************************************
  43  * WARNING:
  44  * CONFIG_BOOT_PCI is only used for first boot-up and should
  45  * NOT be enabled for production bootloader
  46  ***********************************************************/
  47 /*#define        CONFIG_BOOT_PCI         1*/
  48 /***********************************************************
  49  * Clock
  50  ***********************************************************/
  51 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  52
  53 /***********************************************************
  54  * Command definitions
  55  ***********************************************************/
  56 #define MIP405_COMMON_CMDS \
  57                        (CONFIG_CMD_DFL  | \
  58                         CFG_CMD_CACHE   | \
  59                         CFG_CMD_DATE    | \
  60                         CFG_CMD_DHCP    | \
  61                         CFG_CMD_ECHO    | \
  62                         CFG_CMD_EEPROM  | \
  63                         CFG_CMD_ELF     | \
  64                         CFG_CMD_FAT     | \
  65                         CFG_CMD_I2C     | \
  66                         CFG_CMD_IDE     | \
  67                         CFG_CMD_IRQ     | \
  68                         CFG_CMD_JFFS2   | \
  69                         CFG_CMD_MII     | \
  70                         CFG_CMD_PCI     | \
  71                         CFG_CMD_PING    | \
  72                         CFG_CMD_REGINFO | \
  73                         CFG_CMD_SAVES   | \
  74                         CFG_CMD_BSP     )
  75
  76 #if defined(CONFIG_MIP405T)
  77 #define CONFIG_COMMANDS         \
  78                         MIP405_COMMON_CMDS
  79 #else
  80 #define CONFIG_COMMANDS         \
  81                         (MIP405_COMMON_CMDS | \
  82                         CFG_CMD_USB     | \
  83                         CFG_CMD_DOC     )
  84
  85 #endif
  86
  87 /* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
  88 #include <cmd_confdefs.h>
  89
  90 #define  CFG_HUSH_PARSER
  91 #define  CFG_PROMPT_HUSH_PS2 "> "
  92 /**************************************************************
  93  * I2C Stuff:
  94  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  95  * 0x53.
  96  * The Atmel EEPROM uses 16Bit addressing.
  97  ***************************************************************/
  98
  99 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 100 #define CFG_I2C_SPEED           50000   /* I2C speed and slave address */
 101 #define CFG_I2C_SLAVE           0x7F
 102
 103 #define CFG_I2C_EEPROM_ADDR     0x53    /* EEPROM 24C128/256            */
 104 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 105 /* mask of address bits that overflow into the "EEPROM chip address"    */
 106 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
 107 #define CFG_EEPROM_PAGE_WRITE_BITS 6    /* The Atmel 24C128/256 has     */
 108                                         /* 64 byte page write mode using*/
 109                                         /* last 6 bits of the address   */
 110 #define CFG_EEPROM_PAGE_WRITE_ENABLE    /* enable Page write */
 111 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 112
 113
 114 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 115 #define CFG_ENV_OFFSET          0x00000 /* environment starts at the beginning of the EEPROM */
 116 #define CFG_ENV_SIZE            0x00800 /* 2k bytes may be used for env vars */
 117
 118 /***************************************************************
 119  * Definitions for Serial Presence Detect EEPROM address
 120  * (to get SDRAM settings)
 121  ***************************************************************/
 122 /*#define SDRAM_EEPROM_WRITE_ADDRESS    0xA0
 123 #define SDRAM_EEPROM_READ_ADDRESS       0xA1
 124 */
 125 /**************************************************************
 126  * Environment definitions
 127  **************************************************************/
 128 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 129 #define CONFIG_BOOTDELAY        5
 130 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 131 #define CONFIG_BOOT_RETRY_TIME  -10     /* feature is avaiable but not enabled */
 132 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 133
 134 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 135 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 136
 137 #define CONFIG_IPADDR           10.0.0.100
 138 #define CONFIG_SERVERIP         10.0.0.1
 139 #define CONFIG_PREBOOT
 140 /***************************************************************
 141  * defines if the console is stored in the environment
 142  ***************************************************************/
 143 #define CFG_CONSOLE_IS_IN_ENV   /* stdin, stdout and stderr are in evironment */
 144 /***************************************************************
 145  * defines if an overwrite_console function exists
 146  *************************************************************/
 147 #define CFG_CONSOLE_OVERWRITE_ROUTINE
 148 #define CFG_CONSOLE_INFO_QUIET
 149 /***************************************************************
 150  * defines if the overwrite_console should be stored in the
 151  * environment
 152  **************************************************************/
 153 #undef CFG_CONSOLE_ENV_OVERWRITE
 154
 155 /**************************************************************
 156  * loads config
 157  *************************************************************/
 158 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 159 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 160
 161 #define CONFIG_MISC_INIT_R
 162 /***********************************************************
 163  * Miscellaneous configurable options
 164  **********************************************************/
 165 #define CFG_LONGHELP                    /* undef to save memory         */
 166 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 167 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 168 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 169 #else
 170 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 171 #endif
 172 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 173 #define CFG_MAXARGS     16              /* max number of command args   */
 174 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 175
 176 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 177 #define CFG_MEMTEST_END         0x0C00000       /* 1 ... 12 MB in DRAM  */
 178
 179 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 180 #define CFG_BASE_BAUD       916667
 181
 182 /* The following table includes the supported baudrates */
 183 #define CFG_BAUDRATE_TABLE      \
 184         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 185          57600, 115200, 230400, 460800, 921600 }
 186
 187 #define CFG_LOAD_ADDR   0x400000        /* default load address */
 188 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 189
 190 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 191
 192 /*-----------------------------------------------------------------------
 193  * PCI stuff
 194  *-----------------------------------------------------------------------
 195  */
 196 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 197 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 198 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 199
 200 #define CONFIG_PCI                      /* include pci support          */
 201 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 202 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 203                                         /* resource configuration       */
 204 #define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 205 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 206 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 207 #define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 208 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 209 #define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
 210 #define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
 211 #define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 212
 213 /*-----------------------------------------------------------------------
 214  * Start addresses for the final memory configuration
 215  * (Set up by the startup code)
 216  * Please note that CFG_SDRAM_BASE _must_ start at 0
 217  */
 218 #define CFG_SDRAM_BASE          0x00000000
 219 #define CFG_FLASH_BASE          0xFFF80000
 220 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 221 #define CFG_MONITOR_LEN         (512 * 1024)    /* Reserve 512 kB for Monitor   */
 222 #define CFG_MALLOC_LEN          (1024 * 1024)   /* Reserve 1024 kB for malloc() */
 223
 224 /*
 225  * For booting Linux, the board info and command line data
 226  * have to be in the first 8 MB of memory, since this is
 227  * the maximum mapped by the Linux kernel during initialization.
 228  */
 229 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 230 /*-----------------------------------------------------------------------
 231  * FLASH organization
 232  */
 233 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 234 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 235
 236 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 237 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 238
 239 /*
 240  * JFFS2 partitions
 241  *
 242  */
 243 /* No command line, one static partition, whole device */
 244 #undef CONFIG_JFFS2_CMDLINE
 245 #define CONFIG_JFFS2_DEV                "nor0"
 246 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 247 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 248
 249 /* mtdparts command line support */
 250 /* Note: fake mtd_id used, no linux mtd map file */
 251 /*
 252 #define CONFIG_JFFS2_CMDLINE
 253 #define MTDIDS_DEFAULT          "nor0=mip405-0"
 254 #define MTDPARTS_DEFAULT        "mtdparts=mip405-0:-(jffs2)"
 255 */
 256
 257 /*-----------------------------------------------------------------------
 258  * Cache Configuration
 259  */
 260 #define CFG_DCACHE_SIZE         0x4000  /* For IBM 405GPr CPUs                  */
 261 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 262 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 263 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 264 #endif
 265
 266 /*-----------------------------------------------------------------------
 267  * Logbuffer Configuration
 268  */
 269 #undef CONFIG_LOGBUFFER         /* supported but not enabled */
 270 /*-----------------------------------------------------------------------
 271  * Bootcountlimit Configuration
 272  */
 273 #undef CONFIG_BOOTCOUNT_LIMIT   /* supported but not enabled */
 274
 275 /*-----------------------------------------------------------------------
 276  * POST Configuration
 277  */
 278 #if 0 /* enable this if POST is desired (is supported but not enabled) */
 279 #define CONFIG_POST             (CFG_POST_MEMORY        | \
 280                                  CFG_POST_CPU           | \
 281                                  CFG_POST_RTC           | \
 282                                  CFG_POST_I2C)
 283
 284 #endif
 285 /*
 286  * Init Memory Controller:
 287  */
 288 #define FLASH_MAX_SIZE          0x00800000              /* 8MByte max */
 289 #define FLASH_BASE_PRELIM       0xFF800000  /* open the flash CS */
 290 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
 291 #define FLASH_SIZE_PRELIM        3  /* maximal flash FLASH size bank #0 */
 292
 293 #define CONFIG_BOARD_EARLY_INIT_F 1
 294
 295 /* Peripheral Bus Mapping */
 296 #define PER_PLD_ADDR            0xF4000000 /* smallest window is 1MByte 0x10 0000*/
 297 #define PER_UART0_ADDR          0xF4100000 /* smallest window is 1MByte 0x10 0000*/
 298 #define PER_UART1_ADDR          0xF4200000 /* smallest window is 1MByte 0x10 0000*/
 299
 300 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 301 #define CONFIG_PORT_ADDR        PER_PLD_ADDR + 5
 302
 303
 304 /*-----------------------------------------------------------------------
 305  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 306  */
 307 #define CFG_TEMP_STACK_OCM      1
 308 #define CFG_OCM_DATA_ADDR       0xF0000000
 309 #define CFG_OCM_DATA_SIZE       0x1000
 310 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR       /* inside of On Chip SRAM    */
 311 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE       /* End of On Chip SRAM         */
 312 #define CFG_GBL_DATA_SIZE       64              /* size in bytes reserved for initial data */
 313 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 314 /* reserve some memory for POST and BOOT limit info */
 315 #define CFG_INIT_SP_OFFSET      (CFG_GBL_DATA_OFFSET - 32)
 316
 317 #ifdef  CONFIG_POST             /* reserve one word for POST Info */
 318 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 4)
 319 #endif
 320
 321 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 322 #define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 12)
 323 #endif
 324
 325 /*
 326  * Internal Definitions
 327  *
 328  * Boot Flags
 329  */
 330 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 331 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 332
 333
 334 /***********************************************************************
 335  * External peripheral base address
 336  ***********************************************************************/
 337 #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
 338
 339 /***********************************************************************
 340  * Last Stage Init
 341  ***********************************************************************/
 342 #define CONFIG_LAST_STAGE_INIT
 343 /************************************************************
 344  * Ethernet Stuff
 345  ***********************************************************/
 346 #define CONFIG_MII              1       /* MII PHY management           */
 347 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 348 #define CONFIG_PHY_RESET_DELAY  300     /* Intel LXT971A needs this */
 349 #define CONFIG_PHY_CMD_DELAY    40      /* Intel LXT971A needs this */
 350 /************************************************************
 351  * RTC
 352  ***********************************************************/
 353 #define CONFIG_RTC_MC146818
 354 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 355
 356 /************************************************************
 357  * IDE/ATA stuff
 358  ************************************************************/
 359 #if defined(CONFIG_MIP405T)
 360 #define CFG_IDE_MAXBUS          1   /* MIP405T has only one IDE bus     */
 361 #else
 362 #define CFG_IDE_MAXBUS          2   /* max. 2 IDE busses        */
 363 #endif
 364
 365 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 366
 367 #define CFG_ATA_BASE_ADDR       CFG_ISA_IO_BASE_ADDRESS /* base address */
 368 #define CFG_ATA_IDE0_OFFSET     0x01F0          /* ide0 offste */
 369 #define CFG_ATA_IDE1_OFFSET     0x0170          /* ide1 offset */
 370 #define CFG_ATA_DATA_OFFSET     0               /* data reg offset      */
 371 #define CFG_ATA_REG_OFFSET      0               /* reg offset */
 372 #define CFG_ATA_ALT_OFFSET      0x200           /* alternate register offset */
 373
 374 #undef  CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
 375 #undef  CONFIG_IDE_LED         /* no led for ide supported     */
 376 #define CONFIG_IDE_RESET       /* reset for ide supported...    */
 377 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
 378 #define CONFIG_SUPPORT_VFAT
 379 /************************************************************
 380  * ATAPI support (experimental)
 381  ************************************************************/
 382 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 383
 384 /************************************************************
 385  * DISK Partition support
 386  ************************************************************/
 387 #define CONFIG_DOS_PARTITION
 388 #define CONFIG_MAC_PARTITION
 389 #define CONFIG_ISO_PARTITION /* Experimental */
 390
 391 /************************************************************
 392  * Disk-On-Chip configuration
 393  ************************************************************/
 394 #define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices            */
 395 #define CFG_DOC_SHORT_TIMEOUT
 396 #define CFG_DOC_SUPPORT_2000
 397 #define CFG_DOC_SUPPORT_MILLENNIUM
 398 /************************************************************
 399  * Keyboard support
 400  ************************************************************/
 401 #undef CONFIG_ISA_KEYBOARD
 402
 403 /************************************************************
 404  * Video support
 405  ************************************************************/
 406 #define CONFIG_VIDEO                    /*To enable video controller support */
 407 #define CONFIG_VIDEO_CT69000
 408 #define CONFIG_CFB_CONSOLE
 409 #define CONFIG_VIDEO_LOGO
 410 #define CONFIG_CONSOLE_EXTRA_INFO
 411 #define CONFIG_VGA_AS_SINGLE_DEVICE
 412 #define CONFIG_VIDEO_SW_CURSOR
 413 #undef CONFIG_VIDEO_ONBOARD
 414 /************************************************************
 415  * USB support EXPERIMENTAL
 416  ************************************************************/
 417 #if !defined(CONFIG_MIP405T)
 418 #define CONFIG_USB_UHCI
 419 #define CONFIG_USB_KEYBOARD
 420 #define CONFIG_USB_STORAGE
 421
 422 /* Enable needed helper functions */
 423 #define CFG_DEVICE_DEREGISTER           /* needs device_deregister */
 424 #endif
 425 /************************************************************
 426  * Debug support
 427  ************************************************************/
 428 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 429 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 430 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 431 #endif
 432
 433 /************************************************************
 434  * support BZIP2 compression
 435  ************************************************************/
 436 #define CONFIG_BZIP2            1
 437
 438 /************************************************************
 439  * Ident
 440  ************************************************************/
 441
 442 #define VERSION_TAG "released"
 443 #if !defined(CONFIG_MIP405T)
 444 #define CONFIG_ISO_STRING "MEV-10072-001"
 445 #else
 446 #define CONFIG_ISO_STRING "MEV-10082-001"
 447 #endif
 448
 449 #if !defined(CONFIG_BOOT_PCI)
 450 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 451 #else
 452 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
 453 #endif
 454
 455
 456 #endif  /* __CONFIG_H */