include/configs/MOUSSE.h

   1 /*
   2  * (C) Copyright 2000, 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2001
   6  * James F. Dougherty (jfd@cs.stanford.edu)
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  *
  29  * Configuration settings for the MOUSSE board.
  30  * See also: http://www.vooha.com/
  31  *
  32  */
  33
  34 /* ------------------------------------------------------------------------- */
  35
  36 /*
  37  * board/config.h - configuration options, board specific
  38  */
  39
  40 #ifndef __CONFIG_H
  41 #define __CONFIG_H
  42
  43 /*
  44  * High Level Configuration Options
  45  * (easy to change)
  46  */
  47
  48 #define CONFIG_MPC824X      1
  49 #define CONFIG_MPC8240      1
  50 #define CONFIG_MOUSSE       1
  51
  52 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  53
  54 #define CONFIG_SYS_ADDR_MAP_B      1
  55
  56 #define CONFIG_CONS_INDEX   1
  57 #define CONFIG_BAUDRATE     9600
  58 #if 1
  59 #define CONFIG_BOOTCOMMAND  "tftp 100000 vmlinux.img;bootm"    /* autoboot command */
  60 #else
  61 #define CONFIG_BOOTCOMMAND  "bootm ffe10000"
  62 #endif
  63 #define CONFIG_BOOTARGS      "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
  64 #define CONFIG_BOOTDELAY     3
  65
  66
  67 /*
  68  * BOOTP options
  69  */
  70 #define CONFIG_BOOTP_BOOTFILESIZE
  71 #define CONFIG_BOOTP_BOOTPATH
  72 #define CONFIG_BOOTP_GATEWAY
  73 #define CONFIG_BOOTP_HOSTNAME
  74
  75
  76 /*
  77  * Command line configuration.
  78  */
  79 #include <config_cmd_default.h>
  80
  81 #define CONFIG_CMD_ASKENV
  82 #define CONFIG_CMD_DATE
  83
  84
  85 #define CONFIG_ENV_OVERWRITE 1
  86 #define CONFIG_ETH_ADDR      "00:10:18:10:00:06"
  87
  88 #define CONFIG_DOS_PARTITION  1 /* MSDOS bootable partitiion support */
  89
  90 #include "../board/mousse/mousse.h"
  91
  92 /*
  93  * Miscellaneous configurable options
  94  */
  95 #undef CONFIG_SYS_LONGHELP                /* undef to save memory     */
  96 #define CONFIG_SYS_PROMPT      "=>"  /* Monitor Command Prompt   */
  97 #define CONFIG_SYS_CBSIZE      256        /* Console I/O Buffer Size  */
  98 #define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  99 #define CONFIG_SYS_MAXARGS     8           /* Max number of command args   */
 100
 101 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
 102 #define CONFIG_SYS_LOAD_ADDR   0x00100000  /* Default load address         */
 103
 104 /*-----------------------------------------------------------------------
 105  * Start addresses for the final memory configuration
 106  * (Set up by the startup code)
 107  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 108  */
 109 #define CONFIG_SYS_SDRAM_BASE      0x00000000
 110
 111 #ifdef DEBUG
 112 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_SDRAM_BASE
 113 #else
 114 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_FLASH_BASE
 115 #endif
 116
 117 #ifdef DEBUG
 118 #define CONFIG_SYS_MONITOR_LEN     (4 << 20)    /* lots of mem ... */
 119 #else
 120 #define CONFIG_SYS_MONITOR_LEN     (512 << 10)  /* 512K PLCC bootrom */
 121 #endif
 122 #define CONFIG_SYS_MALLOC_LEN      (2*(4096 << 10))    /* 2*4096kB for malloc()  */
 123
 124 #define CONFIG_SYS_MEMTEST_START   0x00004000   /* memtest works on      */
 125 #define CONFIG_SYS_MEMTEST_END     0x02000000   /* 0 ... 32 MB in DRAM   */
 126
 127
 128 #define CONFIG_SYS_EUMB_ADDR       0xFC000000
 129
 130 #define CONFIG_SYS_ISA_MEM         0xFD000000
 131 #define CONFIG_SYS_ISA_IO          0xFE000000
 132
 133 #define CONFIG_SYS_FLASH_BASE      0xFFF00000
 134 #define CONFIG_SYS_FLASH_SIZE      ((uint)(512 * 1024))
 135 #define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 136 #define FLASH_BASE0_PRELIM  0xFFF00000  /* 512K PLCC FLASH/AM29F040*/
 137 #define FLASH_BASE0_SIZE    0x80000     /* 512K */
 138 #define FLASH_BASE1_PRELIM  0xFFE10000  /* AMD 29LV160DB
 139                                            1MB - 64K FLASH0 SEG =960K
 140                                            (size=0xf0000)*/
 141
 142 #define CONFIG_SYS_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
 143
 144 /*
 145  * NS16550 Configuration
 146  */
 147 #define CONFIG_SYS_NS16550
 148 #define CONFIG_SYS_NS16550_SERIAL
 149
 150 #define CONFIG_SYS_NS16550_REG_SIZE     1
 151
 152 #define CONFIG_SYS_NS16550_CLK          18432000
 153
 154 #define CONFIG_SYS_NS16550_COM1 0xFFE08080
 155
 156 /*-----------------------------------------------------------------------
 157  * Definitions for initial stack pointer and data area (in DPRAM)
 158  */
 159 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
 160 #define CONFIG_SYS_INIT_RAM_SIZE   0x2F00  /* Size of used area in DPRAM  */
 161 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 162 #define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
 163
 164 /*
 165  * Low Level Configuration Settings
 166  * (address mappings, register initial values, etc.)
 167  * You should know what you are doing if you make changes here.
 168  * For the detail description refer to the MPC8240 user's manual.
 169  */
 170
 171 #define CONFIG_SYS_CLK_FREQ  33000000   /* external frequency to pll */
 172 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
 173 #define CONFIG_SYS_HZ               1000
 174
 175 #define CONFIG_SYS_ETH_DEV_FN       0x00
 176 #define CONFIG_SYS_ETH_IOBASE       0x00104000
 177
 178
 179         /* Bit-field values for MCCR1.
 180          */
 181 #define CONFIG_SYS_ROMNAL          8
 182 #define CONFIG_SYS_ROMFAL          8
 183
 184         /* Bit-field values for MCCR2.
 185          */
 186 #define CONFIG_SYS_REFINT          0xf5     /* Refresh interval               */
 187
 188         /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 189          */
 190 #define CONFIG_SYS_BSTOPRE         0x79
 191
 192 #ifdef INCLUDE_ECC
 193 #define USE_ECC                         1
 194 #else /* INCLUDE_ECC */
 195 #define USE_ECC                         0
 196 #endif /* INCLUDE_ECC */
 197
 198
 199         /* Bit-field values for MCCR3.
 200          */
 201 #define CONFIG_SYS_REFREC          8       /* Refresh to activate interval   */
 202 #define CONFIG_SYS_RDLAT           (4+USE_ECC)   /* Data latancy from read command */
 203
 204         /* Bit-field values for MCCR4.
 205          */
 206 #define CONFIG_SYS_PRETOACT        3       /* Precharge to activate interval */
 207 #define CONFIG_SYS_ACTTOPRE        5       /* Activate to Precharge interval */
 208 #define CONFIG_SYS_SDMODE_CAS_LAT  3       /* SDMODE CAS latancy             */
 209 #define CONFIG_SYS_SDMODE_WRAP     0       /* SDMODE wrap type               */
 210 #define CONFIG_SYS_SDMODE_BURSTLEN 2       /* SDMODE Burst length            */
 211 #define CONFIG_SYS_ACTORW          2
 212 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC)
 213
 214 /* Memory bank settings.
 215  * Only bits 20-29 are actually used from these vales to set the
 216  * start/end addresses. The upper two bits will always be 0, and the lower
 217  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 218  * address. Refer to the MPC8240 book.
 219  */
 220 #define CONFIG_SYS_RAM_SIZE        0x04000000  /* 64MB */
 221
 222
 223 #define CONFIG_SYS_BANK0_START     0x00000000
 224 #define CONFIG_SYS_BANK0_END       (CONFIG_SYS_RAM_SIZE - 1)
 225 #define CONFIG_SYS_BANK0_ENABLE    1
 226 #define CONFIG_SYS_BANK1_START     0x3ff00000
 227 #define CONFIG_SYS_BANK1_END       0x3fffffff
 228 #define CONFIG_SYS_BANK1_ENABLE    0
 229 #define CONFIG_SYS_BANK2_START     0x3ff00000
 230 #define CONFIG_SYS_BANK2_END       0x3fffffff
 231 #define CONFIG_SYS_BANK2_ENABLE    0
 232 #define CONFIG_SYS_BANK3_START     0x3ff00000
 233 #define CONFIG_SYS_BANK3_END       0x3fffffff
 234 #define CONFIG_SYS_BANK3_ENABLE    0
 235 #define CONFIG_SYS_BANK4_START     0x3ff00000
 236 #define CONFIG_SYS_BANK4_END       0x3fffffff
 237 #define CONFIG_SYS_BANK4_ENABLE    0
 238 #define CONFIG_SYS_BANK5_START     0x3ff00000
 239 #define CONFIG_SYS_BANK5_END       0x3fffffff
 240 #define CONFIG_SYS_BANK5_ENABLE    0
 241 #define CONFIG_SYS_BANK6_START     0x3ff00000
 242 #define CONFIG_SYS_BANK6_END       0x3fffffff
 243 #define CONFIG_SYS_BANK6_ENABLE    0
 244 #define CONFIG_SYS_BANK7_START     0x3ff00000
 245 #define CONFIG_SYS_BANK7_END       0x3fffffff
 246 #define CONFIG_SYS_BANK7_ENABLE    0
 247
 248 #define CONFIG_SYS_ODCR            0x7f
 249
 250
 251 #define CONFIG_SYS_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory
 252                                     see 8240 book for details*/
 253 #define PCI_MEM_SPACE1_START    0x80000000
 254 #define PCI_MEM_SPACE2_START    0xfd000000
 255
 256 /* IBAT/DBAT Configuration */
 257 /* Ram: 64MB, starts at address-0, r/w instruction/data */
 258 #define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 259 #define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 260 #define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
 261 #define CONFIG_SYS_DBAT0L      CONFIG_SYS_IBAT0L
 262
 263 /* MPLD/Port-X I/O Space : data and instruction read/write,  cache-inhibit */
 264 #define CONFIG_SYS_IBAT1U      (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 265 #if 0
 266 #define CONFIG_SYS_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10  | BATL_MEMCOHERENCE |\
 267                          BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
 268 #else
 269 #define CONFIG_SYS_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
 270 #endif
 271 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 272 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 273
 274 /* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
 275 #define CONFIG_SYS_IBAT2U       (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
 276 #define CONFIG_SYS_IBAT2L       (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
 277 #define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
 278 #define CONFIG_SYS_DBAT2L      CONFIG_SYS_IBAT2L
 279
 280 /* PCI Memory region 2: PCI Devices in 0xFD space */
 281 #define CONFIG_SYS_IBAT3U       (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
 282 #define CONFIG_SYS_IBAT3L       (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
 283 #define CONFIG_SYS_DBAT3U      CONFIG_SYS_IBAT3U
 284 #define CONFIG_SYS_DBAT3L      CONFIG_SYS_IBAT3L
 285
 286
 287 /*
 288  * For booting Linux, the board info and command line data
 289  * have to be in the first 8 MB of memory, since this is
 290  * the maximum mapped by the Linux kernel during initialization.
 291  */
 292 #define CONFIG_SYS_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
 293
 294 /*-----------------------------------------------------------------------
 295  * FLASH organization
 296  */
 297 #define CONFIG_SYS_MAX_FLASH_BANKS     3       /* Max number of flash banks         */
 298 #define CONFIG_SYS_MAX_FLASH_SECT      64      /* Max number of sectors in one bank */
 299
 300 #define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)   */
 301 #define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)   */
 302
 303 #if 0
 304 #define CONFIG_ENV_IS_IN_FLASH      1
 305 #define CONFIG_ENV_OFFSET          0x8000  /* Offset of the Environment Sector  */
 306 #define CONFIG_ENV_SIZE            0x4000  /* Size of the Environment Sector    */
 307 #else
 308 #define CONFIG_ENV_IS_IN_NVRAM          1
 309 #define CONFIG_ENV_ADDR            NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
 310 #define CONFIG_ENV_OFFSET          CONFIG_ENV_ADDR
 311 #define CONFIG_ENV_SIZE            NV_U_BOOT_ENV_SIZE /* 2K */
 312 #endif
 313 /*-----------------------------------------------------------------------
 314  * Cache Configuration
 315  */
 316 #define CONFIG_SYS_CACHELINE_SIZE  16
 317
 318 /* Localizations */
 319 #if 0
 320 #define CONFIG_ETHADDR          0:0:0:0:1:d
 321 #define CONFIG_IPADDR           172.16.40.113
 322 #define CONFIG_SERVERIP         172.16.40.111
 323 #else
 324 #define CONFIG_ETHADDR          0:0:0:0:1:d
 325 #define CONFIG_IPADDR           209.128.93.138
 326 #define CONFIG_SERVERIP         209.128.93.133
 327 #endif
 328
 329 /*-----------------------------------------------------------------------
 330  * PCI stuff
 331  *-----------------------------------------------------------------------
 332  */
 333 #define CONFIG_PCI                      /* include pci support                  */
 334 #undef CONFIG_PCI_PNP
 335
 336 #define CONFIG_NET_MULTI                /* Multi ethernet cards support         */
 337
 338 #define CONFIG_TULIP
 339
 340 #endif  /* __CONFIG_H */