include/configs/MPC8260ADS.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stuart Hughes <stuarth@lineo.com>
   4  * This file is based on similar values for other boards found in other
   5  * U-Boot config files, and some that I found in the mpc8260ads manual.
   6  *
   7  * Note: my board is a PILOT rev.
   8  * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
   9  *
  10  * (C) Copyright 2003-2004 Arabella Software Ltd.
  11  * Yuli Barcohen <yuli@arabellasw.com>
  12  * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
  13  * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
  14  * Ported to MPC8272ADS board.
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /*
  39  * High Level Configuration Options
  40  * (easy to change)
  41  */
  42
  43 #define CONFIG_MPC8260ADS       1       /* Motorola PQ2 ADS family board */
  44
  45 /* ADS flavours */
  46 #define CFG_8260ADS             1       /* MPC8260ADS */
  47 #define CFG_8266ADS             2       /* MPC8266ADS */
  48 #define CFG_PQ2FADS             3       /* PQ2FADS-ZU or PQ2FADS-VR */
  49 #define CFG_8272ADS             4       /* MPC8272ADS */
  50
  51 #ifndef CONFIG_ADSTYPE
  52 #define CONFIG_ADSTYPE          CFG_8260ADS
  53 #endif /* CONFIG_ADSTYPE */
  54
  55 #if CONFIG_ADSTYPE == CFG_8272ADS
  56 #define CONFIG_MPC8272          1
  57 #else
  58 #define CONFIG_MPC8260          1
  59 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
  60
  61 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  62
  63 /* allow serial and ethaddr to be overwritten */
  64 #define CONFIG_ENV_OVERWRITE
  65
  66 /*
  67  * select serial console configuration
  68  *
  69  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  70  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  71  * for SCC).
  72  *
  73  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  74  * defined elsewhere (for example, on the cogent platform, there are serial
  75  * ports on the motherboard which are used for the serial console - see
  76  * cogent/cma101/serial.[ch]).
  77  */
  78 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  79 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  80 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  81 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  82
  83 /*
  84  * select ethernet configuration
  85  *
  86  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  87  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  88  * for FCC)
  89  *
  90  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  91  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  92  * from CONFIG_COMMANDS to remove support for networking.
  93  */
  94 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
  95 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
  96 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  97
  98 #ifdef CONFIG_ETHER_ON_FCC
  99
 100 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 101
 102 #if   CONFIG_ETHER_INDEX == 1
 103
 104 # define CFG_PHY_ADDR           0
 105 # define CFG_CMXFCR_VALUE       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
 106 # define CFG_CMXFCR_MASK        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
 107
 108 #elif CONFIG_ETHER_INDEX == 2
 109
 110 #if CONFIG_ADSTYPE == CFG_8272ADS       /* RxCLK is CLK15, TxCLK is CLK16 */
 111 # define CFG_PHY_ADDR           3
 112 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
 113 #else                                   /* RxCLK is CLK13, TxCLK is CLK14 */
 114 # define CFG_PHY_ADDR           0
 115 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 116 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
 117
 118 # define CFG_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 119
 120 #endif  /* CONFIG_ETHER_INDEX */
 121
 122 #define CFG_CPMFCR_RAMTYPE      0               /* BDs and buffers on 60x bus */
 123 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
 124
 125 #define CONFIG_MII                      /* MII PHY management           */
 126 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 127 /*
 128  * GPIO pins used for bit-banged MII communications
 129  */
 130 #define MDIO_PORT       2               /* Port C */
 131
 132 #if CONFIG_ADSTYPE == CFG_8272ADS
 133 #define CFG_MDIO_PIN    0x00002000      /* PC18 */
 134 #define CFG_MDC_PIN     0x00001000      /* PC19 */
 135 #else
 136 #define CFG_MDIO_PIN    0x00400000      /* PC9  */
 137 #define CFG_MDC_PIN     0x00200000      /* PC10 */
 138 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
 139
 140 #define MDIO_ACTIVE     (iop->pdir |=  CFG_MDIO_PIN)
 141 #define MDIO_TRISTATE   (iop->pdir &= ~CFG_MDIO_PIN)
 142 #define MDIO_READ       ((iop->pdat &  CFG_MDIO_PIN) != 0)
 143
 144 #define MDIO(bit)       if(bit) iop->pdat |=  CFG_MDIO_PIN; \
 145                         else    iop->pdat &= ~CFG_MDIO_PIN
 146
 147 #define MDC(bit)        if(bit) iop->pdat |=  CFG_MDC_PIN; \
 148                         else    iop->pdat &= ~CFG_MDC_PIN
 149
 150 #define MIIDELAY        udelay(1)
 151
 152 #endif /* CONFIG_ETHER_ON_FCC */
 153
 154 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
 155 #undef CONFIG_SPD_EEPROM        /* On new boards, SDRAM is soldered */
 156 #else
 157 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 158 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
 159 #define CFG_I2C_SLAVE           0x7F
 160
 161 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 162 #define CONFIG_SPD_ADDR         0x50
 163 #endif
 164 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
 165
 166 #ifndef CONFIG_SDRAM_PBI
 167 #define CONFIG_SDRAM_PBI        0 /* By default, use bank-based interleaving */
 168 #endif
 169
 170 #ifndef CONFIG_8260_CLKIN
 171 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
 172 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 173 #else
 174 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 175 #endif
 176 #endif
 177
 178 #define CONFIG_BAUDRATE         115200
 179
 180 #define CFG_EXCLUDE              CFG_CMD_BEDBUG | \
 181                                  CFG_CMD_BMP    | \
 182                                  CFG_CMD_BSP    | \
 183                                  CFG_CMD_DATE   | \
 184                                  CFG_CMD_DOC    | \
 185                                  CFG_CMD_DTT    | \
 186                                  CFG_CMD_EEPROM | \
 187                                  CFG_CMD_ELF    | \
 188                                  CFG_CMD_EXT2   | \
 189                                  CFG_CMD_FAT    | \
 190                                  CFG_CMD_FDC    | \
 191                                  CFG_CMD_FDOS   | \
 192                                  CFG_CMD_HWFLOW | \
 193                                  CFG_CMD_IDE    | \
 194                                  CFG_CMD_KGDB   | \
 195                                  CFG_CMD_MMC    | \
 196                                  CFG_CMD_NAND   | \
 197                                  CFG_CMD_PCI    | \
 198                                  CFG_CMD_PCMCIA | \
 199                                  CFG_CMD_REISER | \
 200                                  CFG_CMD_SCSI   | \
 201                                  CFG_CMD_SPI    | \
 202                                  CFG_CMD_UNIVERSE | \
 203                                  CFG_CMD_USB    | \
 204                                  CFG_CMD_VFD    | \
 205                                  CFG_CMD_XIMG
 206
 207 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
 208 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 209                                  CFG_CMD_SDRAM  | \
 210                                  CFG_CMD_I2C    | \
 211                                  CFG_EXCLUDE    ) )
 212 #else
 213 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 214                                  CFG_EXCLUDE    ) )
 215 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
 216
 217 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 218 #include <cmd_confdefs.h>
 219
 220 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds */
 221 #define CONFIG_BOOTCOMMAND      "bootm fff80000"        /* autoboot command */
 222 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2"
 223
 224 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 225 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 226 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 227 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 228 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 229 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 230 #endif
 231
 232 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 233 #undef  CONFIG_WATCHDOG /* disable platform specific watchdog */
 234
 235 /*
 236  * Miscellaneous configurable options
 237  */
 238 #define CFG_HUSH_PARSER
 239 #define CFG_PROMPT_HUSH_PS2 "> "
 240 #define CFG_LONGHELP                    /* undef to save memory     */
 241 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt   */
 242 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 243 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size  */
 244 #else
 245 #define CFG_CBSIZE      256                     /* Console I/O Buffer Size  */
 246 #endif
 247 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 248 #define CFG_MAXARGS     16                      /* max number of command args   */
 249 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 250
 251 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 252 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 253
 254 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 255
 256 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 257
 258 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 259
 260 #define CFG_FLASH_BASE          0xff800000
 261 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 262 #define CFG_MAX_FLASH_SECT      32      /* max num of sects on one chip */
 263 #define CFG_FLASH_SIZE          8
 264 #define CFG_FLASH_ERASE_TOUT    8000    /* Timeout for Flash Erase (in ms)    */
 265 #define CFG_FLASH_WRITE_TOUT    5       /* Timeout for Flash Write (in ms)    */
 266 #define CFG_FLASH_LOCK_TOUT     5       /* Timeout for Flash Set Lock Bit (in ms) */
 267 #define CFG_FLASH_UNLOCK_TOUT   10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 268 #define CFG_FLASH_PROTECTION            /* "Real" (hardware) sectors protection */
 269
 270 #define CFG_JFFS2_FIRST_SECTOR  1
 271 #define CFG_JFFS2_LAST_SECTOR   27
 272 #define CFG_JFFS2_SORT_FRAGMENTS
 273 #define CFG_JFFS_CUSTOM_PART
 274
 275 /* this is stuff came out of the Motorola docs */
 276 #define CFG_DEFAULT_IMMR        0x0F010000
 277
 278 #define CFG_IMMR                0xF0000000
 279 #define CFG_BCSR                0xF4500000
 280 #define CFG_SDRAM_BASE          0x00000000
 281 #define CFG_LSDRAM_BASE         0xFD000000
 282
 283 #define RS232EN_1               0x02000002
 284 #define RS232EN_2               0x01000001
 285 #define FETHIEN1                0x08000008
 286 #define FETH1_RST               0x04000004
 287 #define FETHIEN2                0x10000000
 288 #define FETH2_RST               0x08000000
 289 #define BCSR_PCI_MODE           0x01000000
 290
 291 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 292 #define CFG_INIT_RAM_END        0x2000  /* End of used area in DPRAM    */
 293 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 294 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 295 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 296
 297
 298 /* 0x0EA28205 */
 299 #define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                       |\
 300                             ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
 301                             ( HRCW_BMS | HRCW_APPC10 )                      |\
 302                             ( HRCW_MODCK_H0101 )                             \
 303                         )
 304 /* no slaves */
 305 #define CFG_HRCW_SLAVE1 0
 306 #define CFG_HRCW_SLAVE2 0
 307 #define CFG_HRCW_SLAVE3 0
 308 #define CFG_HRCW_SLAVE4 0
 309 #define CFG_HRCW_SLAVE5 0
 310 #define CFG_HRCW_SLAVE6 0
 311 #define CFG_HRCW_SLAVE7 0
 312
 313 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 314 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 315
 316 #define CFG_MONITOR_BASE    TEXT_BASE
 317 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 318 #   define CFG_RAMBOOT
 319 #endif
 320
 321 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 322 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 323
 324 #ifdef CONFIG_BZIP2
 325 #define CFG_MALLOC_LEN          (4096 << 10)    /* Reserve 4 MB for malloc()    */
 326 #else
 327 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 KB for malloc()  */
 328 #endif /* CONFIG_BZIP2 */
 329
 330 #ifndef CFG_RAMBOOT
 331 #  define CFG_ENV_IS_IN_FLASH   1
 332 #  define CFG_ENV_SECT_SIZE     0x40000
 333 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
 334 #else
 335 #  define CFG_ENV_IS_IN_NVRAM   1
 336 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 337 #  define CFG_ENV_SIZE          0x200
 338 #endif /* CFG_RAMBOOT */
 339
 340
 341 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 342 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 343 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 344 #endif
 345
 346
 347 #define CFG_HID0_INIT           0
 348 #define CFG_HID0_FINAL          (HID0_ICE | HID0_IFEM | HID0_ABE )
 349
 350 #define CFG_HID2                0
 351
 352 #define CFG_SYPCR               0xFFFFFFC3
 353 #define CFG_BCR                 0x100C0000
 354 #define CFG_SIUMCR              0x0A200000
 355 #define CFG_SCCR                SCCR_DFBRG01
 356 #define CFG_BR0_PRELIM          CFG_FLASH_BASE | 0x00001801
 357 #define CFG_OR0_PRELIM          0xFF800876
 358 #define CFG_BR1_PRELIM          CFG_BCSR | 0x00001801
 359 #define CFG_OR1_PRELIM          0xFFFF8010
 360
 361 #define CFG_RMR                 RMR_CSRE
 362 #define CFG_TMCNTSC             (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 363 #define CFG_PISCR               (PISCR_PS|PISCR_PTF|PISCR_PTE)
 364 #define CFG_RCCR                0
 365
 366 #if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS)
 367 #undef CFG_LSDRAM_BASE          /* No local bus SDRAM on these boards */
 368 #endif /* CONFIG_ADSTYPE == CFG_8266ADS */
 369
 370 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 371 #define CFG_OR2                 0xFE002EC0
 372 #define CFG_PSDMR               0x824B36A3
 373 #define CFG_PSRT                0x13
 374 #define CFG_LSDMR               0x828737A3
 375 #define CFG_LSRT                0x13
 376 #define CFG_MPTPR               0x2800
 377 #elif CONFIG_ADSTYPE == CFG_8272ADS
 378 #define CFG_OR2                 0xFC002CC0
 379 #define CFG_PSDMR               0x834E24A3
 380 #define CFG_PSRT                0x13
 381 #define CFG_MPTPR               0x2800
 382 #else
 383 #define CFG_OR2                 0xFF000CA0
 384 #define CFG_PSDMR               0x016EB452
 385 #define CFG_PSRT                0x21
 386 #define CFG_LSDMR               0x0086A522
 387 #define CFG_LSRT                0x21
 388 #define CFG_MPTPR               0x1900
 389 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 390
 391 #define CFG_RESET_ADDRESS       0x04400000
 392
 393 #endif /* __CONFIG_H */