include/configs/MPC8260ADS.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stuart Hughes <stuarth@lineo.com>
   4  * This file is based on similar values for other boards found in other
   5  * U-Boot config files, and some that I found in the mpc8260ads manual.
   6  *
   7  * Note: my board is a PILOT rev.
   8  * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
   9  *
  10  * (C) Copyright 2003 Arabella Software Ltd.
  11  * Yuli Barcohen <yuli@arabellasw.com>
  12  * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
  13  * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
  14  *
  15  * See file CREDITS for list of people who contributed to this
  16  * project.
  17  *
  18  * This program is free software; you can redistribute it and/or
  19  * modify it under the terms of the GNU General Public License as
  20  * published by the Free Software Foundation; either version 2 of
  21  * the License, or (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31  * MA 02111-1307 USA
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /*
  38  * High Level Configuration Options
  39  * (easy to change)
  40  */
  41
  42 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
  43 #define CONFIG_MPC8260ADS       1       /* ...on motorola ads board */
  44
  45 /* ADS flavours */
  46 #define CFG_8260ADS             1       /* MPC8260ADS */
  47 #define CFG_8266ADS             2       /* MPC8266ADS */
  48 #define CFG_PQ2FADS             3       /* PQ2FADS-ZU or PQ2FADS-VR */
  49
  50 #ifndef CONFIG_ADSTYPE
  51 #define CONFIG_ADSTYPE          CFG_8260ADS
  52 #endif /* CONFIG_ADSTYPE */
  53
  54 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  55
  56 /* allow serial and ethaddr to be overwritten */
  57 #define CONFIG_ENV_OVERWRITE
  58
  59 /*
  60  * select serial console configuration
  61  *
  62  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  63  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  64  * for SCC).
  65  *
  66  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  67  * defined elsewhere (for example, on the cogent platform, there are serial
  68  * ports on the motherboard which are used for the serial console - see
  69  * cogent/cma101/serial.[ch]).
  70  */
  71 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  72 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  73 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  74 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  75
  76 /*
  77  * select ethernet configuration
  78  *
  79  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  80  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  81  * for FCC)
  82  *
  83  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  84  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  85  * from CONFIG_COMMANDS to remove support for networking.
  86  */
  87 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
  88 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
  89 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  90
  91 #ifdef CONFIG_ETHER_ON_FCC
  92
  93 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
  94
  95 #if (CONFIG_ETHER_INDEX == 2)
  96 /*
  97  * - Rx-CLK is CLK13
  98  * - Tx-CLK is CLK14
  99  * - Select bus for bd/buffers (see 28-13)
 100  * - Full duplex
 101  */
 102 # define CFG_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 103 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 104 # define CFG_CPMFCR_RAMTYPE     0
 105 # define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
 106
 107 #endif  /* CONFIG_ETHER_INDEX */
 108
 109 #define CONFIG_MII                      /* MII PHY management           */
 110 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 111 /*
 112  * GPIO pins used for bit-banged MII communications
 113  */
 114 #define MDIO_PORT       2               /* Port C */
 115 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 116 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 117 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 118
 119 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 120                         else    iop->pdat &= ~0x00400000
 121
 122 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 123                         else    iop->pdat &= ~0x00200000
 124
 125 #define MIIDELAY        udelay(1)
 126
 127 #endif /* CONFIG_ETHER_ON_FCC */
 128
 129 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 130 #undef CONFIG_SPD_EEPROM        /* On PQ2FADS-ZU, SDRAM is soldered  */
 131 #else
 132 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 133 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
 134 #define CFG_I2C_SLAVE           0x7F
 135
 136 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 137 #define CONFIG_SPD_ADDR         0x50
 138 #endif
 139 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 140
 141 #ifndef CONFIG_SDRAM_PBI
 142 #define CONFIG_SDRAM_PBI        0 /* By default, use bank-based interleaving */
 143 #endif
 144
 145 #ifndef CONFIG_8260_CLKIN
 146 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 147 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 148 #else
 149 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 150 #endif
 151 #endif
 152
 153 #define CONFIG_BAUDRATE         115200
 154
 155 #define CFG_EXCLUDE              CFG_CMD_BEDBUG | \
 156                                  CFG_CMD_BMP    | \
 157                                  CFG_CMD_BSP    | \
 158                                  CFG_CMD_DATE   | \
 159                                  CFG_CMD_DOC    | \
 160                                  CFG_CMD_DTT    | \
 161                                  CFG_CMD_EEPROM | \
 162                                  CFG_CMD_ELF    | \
 163                                  CFG_CMD_FAT    | \
 164                                  CFG_CMD_FDC    | \
 165                                  CFG_CMD_FDOS   | \
 166                                  CFG_CMD_HWFLOW | \
 167                                  CFG_CMD_IDE    | \
 168                                  CFG_CMD_KGDB   | \
 169                                  CFG_CMD_MMC    | \
 170                                  CFG_CMD_NAND   | \
 171                                  CFG_CMD_PCI    | \
 172                                  CFG_CMD_PCMCIA | \
 173                                 CFG_CMD_REISER  | \
 174                                  CFG_CMD_SCSI   | \
 175                                  CFG_CMD_SPI    | \
 176                                  CFG_CMD_USB    | \
 177                                  CFG_CMD_VFD
 178
 179 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 180 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 181                                  CFG_CMD_SDRAM  | \
 182                                  CFG_CMD_I2C    | \
 183                                  CFG_EXCLUDE    ) )
 184 #else
 185 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 186                                  CFG_EXCLUDE    ) )
 187 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 188
 189 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 190 #include <cmd_confdefs.h>
 191
 192 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 193 #define CONFIG_BOOTCOMMAND      "bootm 100000"  /* autoboot command */
 194 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 195
 196 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 197 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 198 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 199 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 200 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 201 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 202 #endif
 203
 204 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 205 #undef  CONFIG_WATCHDOG /* disable platform specific watchdog */
 206
 207 /*
 208  * Miscellaneous configurable options
 209  */
 210 #define CFG_HUSH_PARSER
 211 #define CFG_PROMPT_HUSH_PS2 "> "
 212 #define CFG_LONGHELP                    /* undef to save memory     */
 213 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt   */
 214 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 215 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size  */
 216 #else
 217 #define CFG_CBSIZE      256                     /* Console I/O Buffer Size  */
 218 #endif
 219 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 220 #define CFG_MAXARGS     16                      /* max number of command args   */
 221 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 222
 223 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 224 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 225
 226 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 227
 228 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 229
 230 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 231
 232 #define CFG_FLASH_BASE          0xff800000
 233 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 234 #define CFG_MAX_FLASH_SECT      32      /* max num of sects on one chip */
 235 #define CFG_FLASH_SIZE          8
 236 #define CFG_FLASH_ERASE_TOUT    8000    /* Timeout for Flash Erase (in ms)    */
 237 #define CFG_FLASH_WRITE_TOUT    5       /* Timeout for Flash Write (in ms)    */
 238 #define CFG_FLASH_LOCK_TOUT     5       /* Timeout for Flash Set Lock Bit (in ms) */
 239 #define CFG_FLASH_UNLOCK_TOUT   10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 240 #define CFG_FLASH_PROTECTION            /* "Real" (hardware) sectors protection */
 241
 242 #define CFG_JFFS2_FIRST_SECTOR  1
 243 #define CFG_JFFS2_LAST_SECTOR   27
 244 #define CFG_JFFS2_SORT_FRAGMENTS
 245 #define CFG_JFFS_CUSTOM_PART
 246
 247 /* this is stuff came out of the Motorola docs */
 248 #define CFG_DEFAULT_IMMR        0x0F010000
 249
 250 #define CFG_IMMR                0xF0000000
 251 #define CFG_BCSR                0xF4500000
 252 #define CFG_SDRAM_BASE          0x00000000
 253 #define CFG_LSDRAM_BASE         0xFD000000
 254
 255 #define RS232EN_1               0x02000002
 256 #define RS232EN_2               0x01000001
 257 #define FETHIEN1                0x08000008
 258 #define FETH1_RST               0x04000004
 259 #define FETHIEN2                0x01000000
 260 #define FETH2_RST               0x08000000
 261 #define BCSR_PCI_MODE           0x01000000
 262
 263 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 264 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 265 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 266 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 267 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 268
 269
 270 /* 0x0EA28205 */
 271 #define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                       |\
 272                             ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
 273                             ( HRCW_BMS | HRCW_APPC10 )                      |\
 274                             ( HRCW_MODCK_H0101 )                             \
 275                         )
 276
 277 /* no slaves */
 278 #define CFG_HRCW_SLAVE1 0
 279 #define CFG_HRCW_SLAVE2 0
 280 #define CFG_HRCW_SLAVE3 0
 281 #define CFG_HRCW_SLAVE4 0
 282 #define CFG_HRCW_SLAVE5 0
 283 #define CFG_HRCW_SLAVE6 0
 284 #define CFG_HRCW_SLAVE7 0
 285
 286 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 287 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 288
 289 #define CFG_MONITOR_BASE    TEXT_BASE
 290 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 291 #   define CFG_RAMBOOT
 292 #endif
 293
 294 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 295 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 296
 297 #ifdef CONFIG_BZIP2
 298 #define CFG_MALLOC_LEN          (4096 << 10)    /* Reserve 4 MB for malloc()    */
 299 #else
 300 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 KB for malloc()  */
 301 #endif /* CONFIG_BZIP2 */
 302
 303 #ifndef CFG_RAMBOOT
 304 #  define CFG_ENV_IS_IN_FLASH   1
 305 #  define CFG_ENV_SECT_SIZE     0x40000
 306 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
 307 #else
 308 #  define CFG_ENV_IS_IN_NVRAM   1
 309 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 310 #  define CFG_ENV_SIZE          0x200
 311 #endif /* CFG_RAMBOOT */
 312
 313
 314 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 315 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 316 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 317 #endif
 318
 319
 320 #define CFG_HID0_INIT           0
 321 #define CFG_HID0_FINAL          (HID0_ICE | HID0_IFEM | HID0_ABE )
 322
 323 #define CFG_HID2                0
 324
 325 #define CFG_SYPCR               0xFFFFFFC3
 326 #define CFG_BCR                 0x100C0000
 327 #define CFG_SIUMCR              0x0A200000
 328 #define CFG_SCCR                SCCR_DFBRG01
 329 #define CFG_BR0_PRELIM          CFG_FLASH_BASE | 0x00001801
 330 #define CFG_OR0_PRELIM          0xFF800876
 331 #define CFG_BR1_PRELIM          CFG_BCSR | 0x00001801
 332 #define CFG_OR1_PRELIM          0xFFFF8010
 333
 334 #define CFG_RMR                 RMR_CSRE
 335 #define CFG_TMCNTSC             (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 336 #define CFG_PISCR               (PISCR_PS|PISCR_PTF|PISCR_PTE)
 337 #define CFG_RCCR                0
 338
 339 #if CONFIG_ADSTYPE == CFG_8266ADS
 340 #undef CFG_LSDRAM_BASE          /* No local bus SDRAM on MPC8266ADS */
 341 #endif /* CONFIG_ADSTYPE == CFG_8266ADS */
 342
 343 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 344 #define CFG_OR2                 0xFE002EC0
 345 #define CFG_PSDMR               0x824B36A3
 346 #define CFG_PSRT                0x13
 347 #define CFG_LSDMR               0x828737A3
 348 #define CFG_LSRT                0x13
 349 #define CFG_MPTPR               0x2800
 350 #else
 351 #define CFG_OR2                 0xFF000CA0
 352 #define CFG_PSDMR               0x016EB452
 353 #define CFG_PSRT                0x21
 354 #define CFG_LSDMR               0x0086A522
 355 #define CFG_LSRT                0x21
 356 #define CFG_MPTPR               0x1900
 357 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 358
 359 #define CFG_RESET_ADDRESS       0x04400000
 360
 361 #endif /* __CONFIG_H */