include/configs/MPC8260ADS.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stuart Hughes <stuarth@lineo.com>
   4  * This file is based on similar values for other boards found in other
   5  * U-Boot config files, and some that I found in the mpc8260ads manual.
   6  *
   7  * Note: my board is a PILOT rev.
   8  * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
   9  *
  10  * (C) Copyright 2003-2004 Arabella Software Ltd.
  11  * Yuli Barcohen <yuli@arabellasw.com>
  12  * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
  13  * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
  14  * Ported to MPC8272ADS board.
  15  *
  16  * Copyright (c) 2005 MontaVista Software, Inc.
  17  * Vitaly Bordug <vbordug@ru.mvista.com>
  18  * Added support for PCI bridge on MPC8272ADS
  19  *
  20  * Copyright (C) Freescale Semiconductor, Inc. 2006-2009.
  21  *
  22  * See file CREDITS for list of people who contributed to this
  23  * project.
  24  *
  25  * This program is free software; you can redistribute it and/or
  26  * modify it under the terms of the GNU General Public License as
  27  * published by the Free Software Foundation; either version 2 of
  28  * the License, or (at your option) any later version.
  29  *
  30  * This program is distributed in the hope that it will be useful,
  31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  33  * GNU General Public License for more details.
  34  *
  35  * You should have received a copy of the GNU General Public License
  36  * along with this program; if not, write to the Free Software
  37  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  38  * MA 02111-1307 USA
  39  */
  40
  41 #ifndef __CONFIG_H
  42 #define __CONFIG_H
  43
  44 /*
  45  * High Level Configuration Options
  46  * (easy to change)
  47  */
  48
  49 #define CONFIG_MPC8260ADS       1       /* Motorola PQ2 ADS family board */
  50
  51 #define CONFIG_CPM2             1       /* Has a CPM2 */
  52
  53 /*
  54  * Figure out if we are booting low via flash HRCW or high via the BCSR.
  55  */
  56 #if (TEXT_BASE != 0xFFF00000)           /* Boot low (flash HRCW) */
  57 #   define CONFIG_SYS_LOWBOOT           1
  58 #endif
  59
  60 /* ADS flavours */
  61 #define CONFIG_SYS_8260ADS              1       /* MPC8260ADS */
  62 #define CONFIG_SYS_8266ADS              2       /* MPC8266ADS */
  63 #define CONFIG_SYS_PQ2FADS              3       /* PQ2FADS-ZU or PQ2FADS-VR */
  64 #define CONFIG_SYS_8272ADS              4       /* MPC8272ADS */
  65
  66 #ifndef CONFIG_ADSTYPE
  67 #define CONFIG_ADSTYPE          CONFIG_SYS_8260ADS
  68 #endif /* CONFIG_ADSTYPE */
  69
  70 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
  71 #define CONFIG_MPC8272          1
  72 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
  73 /*
  74  * Actually MPC8275, but the code is littered with ifdefs that
  75  * apply to both, or which use this ifdef to assume board-specific
  76  * details. :-(
  77  */
  78 #define CONFIG_MPC8272          1
  79 #else
  80 #define CONFIG_MPC8260          1
  81 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
  82
  83 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  84 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy()             */
  85
  86 /* allow serial and ethaddr to be overwritten */
  87 #define CONFIG_ENV_OVERWRITE
  88
  89 /*
  90  * select serial console configuration
  91  *
  92  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  93  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  94  * for SCC).
  95  *
  96  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  97  * defined elsewhere (for example, on the cogent platform, there are serial
  98  * ports on the motherboard which are used for the serial console - see
  99  * cogent/cma101/serial.[ch]).
 100  */
 101 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
 102 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
 103 #undef  CONFIG_CONS_NONE                /* define if console on something else */
 104 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 105
 106 /*
 107  * select ethernet configuration
 108  *
 109  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 110  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 111  * for FCC)
 112  *
 113  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 114  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 115  */
 116 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
 117 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
 118 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 119
 120 #ifdef CONFIG_ETHER_ON_FCC
 121
 122 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 123
 124 #if   CONFIG_ETHER_INDEX == 1
 125
 126 # define CONFIG_SYS_PHY_ADDR            0
 127 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
 128 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
 129
 130 #elif CONFIG_ETHER_INDEX == 2
 131
 132 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS        /* RxCLK is CLK15, TxCLK is CLK16 */
 133 # define CONFIG_SYS_PHY_ADDR            3
 134 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
 135 #else                                   /* RxCLK is CLK13, TxCLK is CLK14 */
 136 # define CONFIG_SYS_PHY_ADDR            0
 137 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 138 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 139
 140 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 141
 142 #endif  /* CONFIG_ETHER_INDEX */
 143
 144 #define CONFIG_SYS_CPMFCR_RAMTYPE       0               /* BDs and buffers on 60x bus */
 145 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
 146
 147 #define CONFIG_MII                      /* MII PHY management           */
 148 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 149 /*
 150  * GPIO pins used for bit-banged MII communications
 151  */
 152 #define MDIO_PORT       2               /* Port C */
 153 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 154                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 155 #define MDC_DECLARE     MDIO_DECLARE
 156
 157 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 158 #define CONFIG_SYS_MDIO_PIN     0x00002000      /* PC18 */
 159 #define CONFIG_SYS_MDC_PIN      0x00001000      /* PC19 */
 160 #else
 161 #define CONFIG_SYS_MDIO_PIN     0x00400000      /* PC9  */
 162 #define CONFIG_SYS_MDC_PIN      0x00200000      /* PC10 */
 163 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 164
 165 #define MDIO_ACTIVE     (iop->pdir |=  CONFIG_SYS_MDIO_PIN)
 166 #define MDIO_TRISTATE   (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
 167 #define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 168
 169 #define MDIO(bit)       if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
 170                         else    iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 171
 172 #define MDC(bit)        if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
 173                         else    iop->pdat &= ~CONFIG_SYS_MDC_PIN
 174
 175 #define MIIDELAY        udelay(1)
 176
 177 #endif /* CONFIG_ETHER_ON_FCC */
 178
 179 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 180 #undef CONFIG_SPD_EEPROM        /* On new boards, SDRAM is soldered */
 181 #else
 182 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 183 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 184 #define CONFIG_SYS_I2C_SLAVE            0x7F
 185
 186 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 187 #define CONFIG_SPD_ADDR         0x50
 188 #endif
 189 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
 190
 191 /*PCI*/
 192 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 193 #define CONFIG_PCI
 194 #define CONFIG_PCI_PNP
 195 #define CONFIG_PCI_BOOTDELAY 0
 196 #define CONFIG_PCI_SCAN_SHOW
 197 #endif
 198
 199 #ifndef CONFIG_SDRAM_PBI
 200 #define CONFIG_SDRAM_PBI        0 /* By default, use bank-based interleaving */
 201 #endif
 202
 203 #ifndef CONFIG_8260_CLKIN
 204 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 205 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 206 #else
 207 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 208 #endif
 209 #endif
 210
 211 #define CONFIG_BAUDRATE         115200
 212
 213 #define CONFIG_OF_LIBFDT        1
 214 #define CONFIG_OF_BOARD_SETUP   1
 215 #if defined(CONFIG_OF_LIBFDT)
 216 #define OF_TBCLK                (bd->bi_busfreq / 4)
 217 #endif
 218
 219 /*
 220  * BOOTP options
 221  */
 222 #define CONFIG_BOOTP_BOOTFILESIZE
 223 #define CONFIG_BOOTP_BOOTPATH
 224 #define CONFIG_BOOTP_GATEWAY
 225 #define CONFIG_BOOTP_HOSTNAME
 226
 227
 228 /*
 229  * Command line configuration.
 230  */
 231 #include <config_cmd_default.h>
 232
 233 #define CONFIG_CMD_ASKENV
 234 #define CONFIG_CMD_CACHE
 235 #define CONFIG_CMD_CDP
 236 #define CONFIG_CMD_DHCP
 237 #define CONFIG_CMD_DIAG
 238 #define CONFIG_CMD_I2C
 239 #define CONFIG_CMD_IMMAP
 240 #define CONFIG_CMD_IRQ
 241 #define CONFIG_CMD_JFFS2
 242 #define CONFIG_CMD_MII
 243 #define CONFIG_CMD_PCI
 244 #define CONFIG_CMD_PING
 245 #define CONFIG_CMD_PORTIO
 246 #define CONFIG_CMD_REGINFO
 247 #define CONFIG_CMD_SAVES
 248 #define CONFIG_CMD_SDRAM
 249
 250 #undef CONFIG_CMD_XIMG
 251
 252 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 253     #undef CONFIG_CMD_SDRAM
 254     #undef CONFIG_CMD_I2C
 255
 256 #elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 257     #undef CONFIG_CMD_SDRAM
 258     #undef CONFIG_CMD_I2C
 259
 260 #else
 261     #undef CONFIG_CMD_PCI
 262
 263 #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
 264
 265
 266 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds */
 267 #define CONFIG_BOOTCOMMAND      "bootm fff80000"        /* autoboot command */
 268 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2"
 269
 270 #if defined(CONFIG_CMD_KGDB)
 271 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 272 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 273 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 274 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 275 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 276 #endif
 277
 278 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 279 #undef  CONFIG_WATCHDOG /* disable platform specific watchdog */
 280
 281 /*
 282  * Miscellaneous configurable options
 283  */
 284 #define CONFIG_SYS_HUSH_PARSER
 285 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 286 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 287 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt   */
 288 #if defined(CONFIG_CMD_KGDB)
 289 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size  */
 290 #else
 291 #define CONFIG_SYS_CBSIZE       256                     /* Console I/O Buffer Size  */
 292 #endif
 293 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 294 #define CONFIG_SYS_MAXARGS      16                      /* max number of command args   */
 295 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 296
 297 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 298 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 299
 300 #define CONFIG_SYS_LOAD_ADDR            0x400000        /* default load address */
 301
 302 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 303
 304 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 305
 306 #define CONFIG_SYS_FLASH_BASE           0xff800000
 307 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 308 #define CONFIG_SYS_MAX_FLASH_SECT       32      /* max num of sects on one chip */
 309 #define CONFIG_SYS_FLASH_SIZE           8
 310 #define CONFIG_SYS_FLASH_ERASE_TOUT     8000    /* Timeout for Flash Erase (in ms)    */
 311 #define CONFIG_SYS_FLASH_WRITE_TOUT     5       /* Timeout for Flash Write (in ms)    */
 312 #define CONFIG_SYS_FLASH_LOCK_TOUT      5       /* Timeout for Flash Set Lock Bit (in ms) */
 313 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 314 #define CONFIG_SYS_FLASH_PROTECTION             /* "Real" (hardware) sectors protection */
 315
 316 /*
 317  * JFFS2 partitions
 318  *
 319  * Note: fake mtd_id used, no linux mtd map file
 320  */
 321 #define MTDIDS_DEFAULT          "nor0=mpc8260ads-0"
 322 #define MTDPARTS_DEFAULT        "mtdparts=mpc8260ads-0:-@1m(jffs2)"
 323 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 324
 325 /* this is stuff came out of the Motorola docs */
 326 #ifndef CONFIG_SYS_LOWBOOT
 327 #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
 328 #endif
 329
 330 #define CONFIG_SYS_IMMR         0xF0000000
 331 #define CONFIG_SYS_BCSR         0xF4500000
 332 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 333 #define CONFIG_SYS_PCI_INT              0xF8200000
 334 #endif
 335 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 336 #define CONFIG_SYS_LSDRAM_BASE          0xFD000000
 337
 338 #define RS232EN_1               0x02000002
 339 #define RS232EN_2               0x01000001
 340 #define FETHIEN1                0x08000008
 341 #define FETH1_RST               0x04000004
 342 #define FETHIEN2                0x10000000
 343 #define FETH2_RST               0x08000000
 344 #define BCSR_PCI_MODE           0x01000000
 345
 346 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 347 #define CONFIG_SYS_INIT_RAM_END 0x2000  /* End of used area in DPRAM    */
 348 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 349 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 350 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 351
 352 #ifdef CONFIG_SYS_LOWBOOT
 353 /* PQ2FADS flash HRCW = 0x0EB4B645 */
 354 #define CONFIG_SYS_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                        |\
 355                             ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 )    |\
 356                             ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
 357                             ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )             \
 358                         )
 359 #else
 360 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
 361 #define CONFIG_SYS_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                        |\
 362                             ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
 363                             ( HRCW_BMS | HRCW_APPC10 )                      |\
 364                             ( HRCW_MODCK_H0101 )                             \
 365                         )
 366 #endif
 367 /* no slaves */
 368 #define CONFIG_SYS_HRCW_SLAVE1 0
 369 #define CONFIG_SYS_HRCW_SLAVE2 0
 370 #define CONFIG_SYS_HRCW_SLAVE3 0
 371 #define CONFIG_SYS_HRCW_SLAVE4 0
 372 #define CONFIG_SYS_HRCW_SLAVE5 0
 373 #define CONFIG_SYS_HRCW_SLAVE6 0
 374 #define CONFIG_SYS_HRCW_SLAVE7 0
 375
 376 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 377 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 378
 379 #define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 380 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 381 #   define CONFIG_SYS_RAMBOOT
 382 #endif
 383
 384 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 385 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 386
 387 #ifdef CONFIG_BZIP2
 388 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 389 #else
 390 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 KB for malloc()  */
 391 #endif /* CONFIG_BZIP2 */
 392
 393 #ifndef CONFIG_SYS_RAMBOOT
 394 #  define CONFIG_ENV_IS_IN_FLASH        1
 395 #  define CONFIG_ENV_SECT_SIZE  0x40000
 396 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
 397 #else
 398 #  define CONFIG_ENV_IS_IN_NVRAM        1
 399 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 400 #  define CONFIG_ENV_SIZE               0x200
 401 #endif /* CONFIG_SYS_RAMBOOT */
 402
 403 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU */
 404 #if defined(CONFIG_CMD_KGDB)
 405 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 406 #endif
 407
 408 #define CONFIG_SYS_HID0_INIT            0
 409 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE )
 410
 411 #define CONFIG_SYS_HID2         0
 412
 413 #define CONFIG_SYS_SYPCR                0xFFFFFFC3
 414 #define CONFIG_SYS_BCR                  0x100C0000
 415 #define CONFIG_SYS_SIUMCR               0x0A200000
 416 #define CONFIG_SYS_SCCR         SCCR_DFBRG01
 417 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00001801)
 418 #define CONFIG_SYS_OR0_PRELIM           0xFF800876
 419 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR | 0x00001801)
 420 #define CONFIG_SYS_OR1_PRELIM           0xFFFF8010
 421
 422 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
 423
 424 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 425 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PCI_INT | 0x1801)   /* PCI interrupt controller */
 426 #define CONFIG_SYS_OR3_PRELIM   0xFFFF8010
 427 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
 428 #define CONFIG_SYS_BR8_PRELIM   (CONFIG_SYS_PCI_INT | 0x1801)   /* PCI interrupt controller */
 429 #define CONFIG_SYS_OR8_PRELIM   0xFFFF8010
 430 #endif
 431
 432 #define CONFIG_SYS_RMR                  RMR_CSRE
 433 #define CONFIG_SYS_TMCNTSC              (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 434 #define CONFIG_SYS_PISCR                (PISCR_PS|PISCR_PTF|PISCR_PTE)
 435 #define CONFIG_SYS_RCCR         0
 436
 437 #if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
 438 #undef CONFIG_SYS_LSDRAM_BASE           /* No local bus SDRAM on these boards */
 439 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
 440
 441 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
 442 #define CONFIG_SYS_OR2                  0xFE002EC0
 443 #define CONFIG_SYS_PSDMR                0x824B36A3
 444 #define CONFIG_SYS_PSRT         0x13
 445 #define CONFIG_SYS_LSDMR                0x828737A3
 446 #define CONFIG_SYS_LSRT         0x13
 447 #define CONFIG_SYS_MPTPR                0x2800
 448 #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 449 #define CONFIG_SYS_OR2                  0xFC002CC0
 450 #define CONFIG_SYS_PSDMR                0x834E24A3
 451 #define CONFIG_SYS_PSRT         0x13
 452 #define CONFIG_SYS_MPTPR                0x2800
 453 #else
 454 #define CONFIG_SYS_OR2                  0xFF000CA0
 455 #define CONFIG_SYS_PSDMR                0x016EB452
 456 #define CONFIG_SYS_PSRT         0x21
 457 #define CONFIG_SYS_LSDMR                0x0086A522
 458 #define CONFIG_SYS_LSRT         0x21
 459 #define CONFIG_SYS_MPTPR                0x1900
 460 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
 461
 462 #define CONFIG_SYS_RESET_ADDRESS        0x04400000
 463
 464 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 465
 466 /* PCI Memory map (if different from default map */
 467 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE           /* Local base */
 468 #define CONFIG_SYS_PCI_SLV_MEM_BUS              0x00000000              /* PCI base */
 469 #define CONFIG_SYS_PICMR0_MASK_ATTRIB   (PICMR_MASK_512MB | PICMR_ENABLE | \
 470                                  PICMR_PREFETCH_EN)
 471
 472 /*
 473  * These are the windows that allow the CPU to access PCI address space.
 474  * All three PCI master windows, which allow the CPU to access PCI
 475  * prefetch, non prefetch, and IO space (see below), must all fit within
 476  * these windows.
 477  */
 478
 479 /*
 480  * Master window that allows the CPU to access PCI Memory (prefetch).
 481  * This window will be setup with the second set of Outbound ATU registers
 482  * in the bridge.
 483  */
 484
 485 #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL   0x80000000          /* Local base */
 486 #define CONFIG_SYS_PCI_MSTR_MEM_BUS     0x80000000          /* PCI base   */
 487 #define CONFIG_SYS_CPU_PCI_MEM_START    PCI_MSTR_MEM_LOCAL
 488 #define CONFIG_SYS_PCI_MSTR_MEM_SIZE    0x20000000          /* 512MB */
 489 #define CONFIG_SYS_POCMR0_MASK_ATTRIB   (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 490
 491 /*
 492  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 493  * This window will be setup with the second set of Outbound ATU registers
 494  * in the bridge.
 495  */
 496
 497 #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
 498 #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
 499 #define CONFIG_SYS_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
 500 #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
 501 #define CONFIG_SYS_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 502
 503 /*
 504  * Master window that allows the CPU to access PCI IO space.
 505  * This window will be setup with the first set of Outbound ATU registers
 506  * in the bridge.
 507  */
 508
 509 #define CONFIG_SYS_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
 510 #define CONFIG_SYS_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
 511 #define CONFIG_SYS_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
 512 #define CONFIG_SYS_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
 513 #define CONFIG_SYS_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
 514
 515
 516 /* PCIBR0 - for PCI IO*/
 517 #define CONFIG_SYS_PCI_MSTR0_LOCAL              CONFIG_SYS_PCI_MSTR_IO_LOCAL            /* Local base */
 518 #define CONFIG_SYS_PCIMSK0_MASK         ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U)     /* Size of window */
 519 /* PCIBR1 - prefetch and non-prefetch regions joined together */
 520 #define CONFIG_SYS_PCI_MSTR1_LOCAL              CONFIG_SYS_PCI_MSTR_MEM_LOCAL
 521 #define CONFIG_SYS_PCIMSK1_MASK         ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
 522
 523 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
 524
 525 #define CONFIG_HAS_ETH0
 526
 527 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 528 #define CONFIG_HAS_ETH1
 529 #endif
 530
 531 #define CONFIG_NETDEV eth0
 532 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
 533
 534 #define XMK_STR(x)      #x
 535 #define MK_STR(x)       XMK_STR(x)
 536
 537 #define CONFIG_EXTRA_ENV_SETTINGS \
 538         "netdev=" MK_STR(CONFIG_NETDEV) "\0"                            \
 539         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 540                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 541                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 542                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 543                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 544                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 545         "fdtaddr=400000\0"                                              \
 546         "console=ttyCPM0\0"                                             \
 547         "setbootargs=setenv bootargs "                                  \
 548                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 549         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 550                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 551                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 552
 553 #define CONFIG_NFSBOOTCOMMAND                                           \
 554         "setenv rootdev /dev/nfs;"                                      \
 555         "run setipargs;"                                                \
 556         "tftp $loadaddr $bootfile;"                                     \
 557         "tftp $fdtaddr $fdtfile;"                                       \
 558         "bootm $loadaddr - $fdtaddr"
 559
 560 #define CONFIG_RAMBOOTCOMMAND                                           \
 561         "setenv rootdev /dev/ram;"                                      \
 562         "run setbootargs;"                                              \
 563         "tftp $ramdiskaddr $ramdiskfile;"                               \
 564         "tftp $loadaddr $bootfile;"                                     \
 565         "tftp $fdtaddr $fdtfile;"                                       \
 566         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 567
 568 #undef MK_STR
 569 #undef XMK_STR
 570
 571 #endif /* __CONFIG_H */