include/configs/MPC8260ADS.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stuart Hughes <stuarth@lineo.com>
   4  * This file is based on similar values for other boards found in other
   5  * U-Boot config files, and some that I found in the mpc8260ads manual.
   6  *
   7  * Note: my board is a PILOT rev.
   8  * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
   9  *
  10  * (C) Copyright 2003-2004 Arabella Software Ltd.
  11  * Yuli Barcohen <yuli@arabellasw.com>
  12  * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
  13  * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
  14  * Ported to MPC8272ADS board.
  15  *
  16  * Copyright (c) 2005 MontaVista Software, Inc.
  17  * Vitaly Bordug <vbordug@ru.mvista.com>
  18  * Added support for PCI bridge on MPC8272ADS
  19  *
  20  * See file CREDITS for list of people who contributed to this
  21  * project.
  22  *
  23  * This program is free software; you can redistribute it and/or
  24  * modify it under the terms of the GNU General Public License as
  25  * published by the Free Software Foundation; either version 2 of
  26  * the License, or (at your option) any later version.
  27  *
  28  * This program is distributed in the hope that it will be useful,
  29  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  31  * GNU General Public License for more details.
  32  *
  33  * You should have received a copy of the GNU General Public License
  34  * along with this program; if not, write to the Free Software
  35  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  36  * MA 02111-1307 USA
  37  */
  38
  39 #ifndef __CONFIG_H
  40 #define __CONFIG_H
  41
  42 /*
  43  * High Level Configuration Options
  44  * (easy to change)
  45  */
  46
  47 #define CONFIG_MPC8260ADS       1       /* Motorola PQ2 ADS family board */
  48
  49 #define CONFIG_CPM2             1       /* Has a CPM2 */
  50
  51 /*
  52  * Figure out if we are booting low via flash HRCW or high via the BCSR.
  53  */
  54 #if (TEXT_BASE != 0xFFF00000)           /* Boot low (flash HRCW) */
  55 #   define CFG_LOWBOOT          1
  56 #endif
  57
  58
  59 /* ADS flavours */
  60 #define CFG_8260ADS             1       /* MPC8260ADS */
  61 #define CFG_8266ADS             2       /* MPC8266ADS */
  62 #define CFG_PQ2FADS             3       /* PQ2FADS-ZU or PQ2FADS-VR */
  63 #define CFG_8272ADS             4       /* MPC8272ADS */
  64
  65 #ifndef CONFIG_ADSTYPE
  66 #define CONFIG_ADSTYPE          CFG_8260ADS
  67 #endif /* CONFIG_ADSTYPE */
  68
  69 #if CONFIG_ADSTYPE == CFG_8272ADS
  70 #define CONFIG_MPC8272          1
  71 #else
  72 #define CONFIG_MPC8260          1
  73 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
  74
  75 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  76
  77 /* allow serial and ethaddr to be overwritten */
  78 #define CONFIG_ENV_OVERWRITE
  79
  80 /*
  81  * select serial console configuration
  82  *
  83  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  84  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  85  * for SCC).
  86  *
  87  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  88  * defined elsewhere (for example, on the cogent platform, there are serial
  89  * ports on the motherboard which are used for the serial console - see
  90  * cogent/cma101/serial.[ch]).
  91  */
  92 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  93 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  94 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  95 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  96
  97 /*
  98  * select ethernet configuration
  99  *
 100  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 101  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 102  * for FCC)
 103  *
 104  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 105  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 106  * from CONFIG_COMMANDS to remove support for networking.
 107  */
 108 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
 109 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
 110 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 111
 112 #ifdef CONFIG_ETHER_ON_FCC
 113
 114 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 115
 116 #if   CONFIG_ETHER_INDEX == 1
 117
 118 # define CFG_PHY_ADDR           0
 119 # define CFG_CMXFCR_VALUE       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
 120 # define CFG_CMXFCR_MASK        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
 121
 122 #elif CONFIG_ETHER_INDEX == 2
 123
 124 #if CONFIG_ADSTYPE == CFG_8272ADS       /* RxCLK is CLK15, TxCLK is CLK16 */
 125 # define CFG_PHY_ADDR           3
 126 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
 127 #else                                   /* RxCLK is CLK13, TxCLK is CLK14 */
 128 # define CFG_PHY_ADDR           0
 129 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 130 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
 131
 132 # define CFG_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 133
 134 #endif  /* CONFIG_ETHER_INDEX */
 135
 136 #define CFG_CPMFCR_RAMTYPE      0               /* BDs and buffers on 60x bus */
 137 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
 138
 139 #define CONFIG_MII                      /* MII PHY management           */
 140 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 141 /*
 142  * GPIO pins used for bit-banged MII communications
 143  */
 144 #define MDIO_PORT       2               /* Port C */
 145
 146 #if CONFIG_ADSTYPE == CFG_8272ADS
 147 #define CFG_MDIO_PIN    0x00002000      /* PC18 */
 148 #define CFG_MDC_PIN     0x00001000      /* PC19 */
 149 #else
 150 #define CFG_MDIO_PIN    0x00400000      /* PC9  */
 151 #define CFG_MDC_PIN     0x00200000      /* PC10 */
 152 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
 153
 154 #define MDIO_ACTIVE     (iop->pdir |=  CFG_MDIO_PIN)
 155 #define MDIO_TRISTATE   (iop->pdir &= ~CFG_MDIO_PIN)
 156 #define MDIO_READ       ((iop->pdat &  CFG_MDIO_PIN) != 0)
 157
 158 #define MDIO(bit)       if(bit) iop->pdat |=  CFG_MDIO_PIN; \
 159                         else    iop->pdat &= ~CFG_MDIO_PIN
 160
 161 #define MDC(bit)        if(bit) iop->pdat |=  CFG_MDC_PIN; \
 162                         else    iop->pdat &= ~CFG_MDC_PIN
 163
 164 #define MIIDELAY        udelay(1)
 165
 166 #endif /* CONFIG_ETHER_ON_FCC */
 167
 168 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
 169 #undef CONFIG_SPD_EEPROM        /* On new boards, SDRAM is soldered */
 170 #else
 171 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 172 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
 173 #define CFG_I2C_SLAVE           0x7F
 174
 175 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 176 #define CONFIG_SPD_ADDR         0x50
 177 #endif
 178 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
 179
 180 /*PCI*/
 181 #ifdef CONFIG_MPC8272
 182 #define CONFIG_PCI
 183 #define CONFIG_PCI_PNP
 184 #define CONFIG_PCI_BOOTDELAY 0
 185 #define CONFIG_PCI_SCAN_SHOW
 186 #endif
 187
 188
 189 #ifndef CONFIG_SDRAM_PBI
 190 #define CONFIG_SDRAM_PBI        0 /* By default, use bank-based interleaving */
 191 #endif
 192
 193 #ifndef CONFIG_8260_CLKIN
 194 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
 195 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 196 #else
 197 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 198 #endif
 199 #endif
 200
 201 #define CONFIG_BAUDRATE         115200
 202
 203 #define CFG_EXCLUDE             CFG_CMD_BEDBUG  | \
 204                                 CFG_CMD_BMP     | \
 205                                 CFG_CMD_BSP     | \
 206                                 CFG_CMD_DATE    | \
 207                                 CFG_CMD_DISPLAY | \
 208                                 CFG_CMD_DOC     | \
 209                                 CFG_CMD_DTT     | \
 210                                 CFG_CMD_EEPROM  | \
 211                                 CFG_CMD_ELF     | \
 212                                 CFG_CMD_EXT2    | \
 213                                 CFG_CMD_FAT     | \
 214                                 CFG_CMD_FDC     | \
 215                                 CFG_CMD_FDOS    | \
 216                                 CFG_CMD_HWFLOW  | \
 217                                 CFG_CMD_IDE     | \
 218                                 CFG_CMD_KGDB    | \
 219                                 CFG_CMD_MMC     | \
 220                                 CFG_CMD_NAND    | \
 221                                 CFG_CMD_PCMCIA  | \
 222                                 CFG_CMD_REISER  | \
 223                                 CFG_CMD_SCSI    | \
 224                                 CFG_CMD_SPI     | \
 225                                 CFG_CMD_SNTP    | \
 226                                 CFG_CMD_UNIVERSE | \
 227                                 CFG_CMD_USB     | \
 228                                 CFG_CMD_VFD     | \
 229                                 CFG_CMD_XIMG
 230
 231 #if CONFIG_ADSTYPE == CFG_8272ADS
 232 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 233                                  CFG_CMD_SDRAM  | \
 234                                  CFG_CMD_I2C    | \
 235                                  CFG_EXCLUDE    ) )
 236 #elif CONFIG_ADSTYPE >= CFG_PQ2FADS
 237 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 238                                  CFG_CMD_SDRAM  | \
 239                                  CFG_CMD_I2C    | \
 240                                  CFG_CMD_PCI    | \
 241                                  CFG_EXCLUDE    ) )
 242 #else
 243 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 244                                  CMD_CFG_PCI    | \
 245                                  CFG_EXCLUDE    ) )
 246 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
 247
 248 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 249 #include <cmd_confdefs.h>
 250
 251 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds */
 252 #define CONFIG_BOOTCOMMAND      "bootm fff80000"        /* autoboot command */
 253 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2"
 254
 255 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 256 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 257 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 258 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 259 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 260 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 261 #endif
 262
 263 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 264 #undef  CONFIG_WATCHDOG /* disable platform specific watchdog */
 265
 266 /*
 267  * Miscellaneous configurable options
 268  */
 269 #define CFG_HUSH_PARSER
 270 #define CFG_PROMPT_HUSH_PS2 "> "
 271 #define CFG_LONGHELP                    /* undef to save memory     */
 272 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt   */
 273 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 274 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size  */
 275 #else
 276 #define CFG_CBSIZE      256                     /* Console I/O Buffer Size  */
 277 #endif
 278 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 279 #define CFG_MAXARGS     16                      /* max number of command args   */
 280 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 281
 282 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 283 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 284
 285 #define CFG_LOAD_ADDR           0x400000        /* default load address */
 286
 287 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 288
 289 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 290
 291 #define CFG_FLASH_BASE          0xff800000
 292 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 293 #define CFG_MAX_FLASH_SECT      32      /* max num of sects on one chip */
 294 #define CFG_FLASH_SIZE          8
 295 #define CFG_FLASH_ERASE_TOUT    8000    /* Timeout for Flash Erase (in ms)    */
 296 #define CFG_FLASH_WRITE_TOUT    5       /* Timeout for Flash Write (in ms)    */
 297 #define CFG_FLASH_LOCK_TOUT     5       /* Timeout for Flash Set Lock Bit (in ms) */
 298 #define CFG_FLASH_UNLOCK_TOUT   10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 299 #define CFG_FLASH_PROTECTION            /* "Real" (hardware) sectors protection */
 300
 301 /*
 302  * JFFS2 partitions
 303  *
 304  * Note: fake mtd_id used, no linux mtd map file
 305  */
 306 #define MTDIDS_DEFAULT          "nor0=mpc8260ads-0"
 307 #define MTDPARTS_DEFAULT        "mtdparts=mpc8260ads-0:-@1m(jffs2)"
 308 #define CFG_JFFS2_SORT_FRAGMENTS
 309
 310 /* this is stuff came out of the Motorola docs */
 311 #ifndef CFG_LOWBOOT
 312 #define CFG_DEFAULT_IMMR        0x0F010000
 313 #endif
 314
 315 #define CFG_IMMR                0xF0000000
 316 #define CFG_BCSR                0xF4500000
 317 #if CONFIG_ADSTYPE == CFG_8272ADS
 318 #define CFG_PCI_INT             0xF8200000
 319 #endif
 320 #define CFG_SDRAM_BASE          0x00000000
 321 #define CFG_LSDRAM_BASE         0xFD000000
 322
 323 #define RS232EN_1               0x02000002
 324 #define RS232EN_2               0x01000001
 325 #define FETHIEN1                0x08000008
 326 #define FETH1_RST               0x04000004
 327 #define FETHIEN2                0x10000000
 328 #define FETH2_RST               0x08000000
 329 #define BCSR_PCI_MODE           0x01000000
 330
 331 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 332 #define CFG_INIT_RAM_END        0x2000  /* End of used area in DPRAM    */
 333 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 334 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 335 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 336
 337
 338 #ifdef CFG_LOWBOOT
 339 /* PQ2FADS flash HRCW = 0x0EB4B645 */
 340 #define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                       |\
 341                             ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 )    |\
 342                             ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
 343                             ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )             \
 344                         )
 345 #else
 346 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
 347 #define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                       |\
 348                             ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
 349                             ( HRCW_BMS | HRCW_APPC10 )                      |\
 350                             ( HRCW_MODCK_H0101 )                             \
 351                         )
 352 #endif
 353 /* no slaves */
 354 #define CFG_HRCW_SLAVE1 0
 355 #define CFG_HRCW_SLAVE2 0
 356 #define CFG_HRCW_SLAVE3 0
 357 #define CFG_HRCW_SLAVE4 0
 358 #define CFG_HRCW_SLAVE5 0
 359 #define CFG_HRCW_SLAVE6 0
 360 #define CFG_HRCW_SLAVE7 0
 361
 362 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 363 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 364
 365 #define CFG_MONITOR_BASE    TEXT_BASE
 366 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 367 #   define CFG_RAMBOOT
 368 #endif
 369
 370 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 371 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 372
 373 #ifdef CONFIG_BZIP2
 374 #define CFG_MALLOC_LEN          (4096 << 10)    /* Reserve 4 MB for malloc()    */
 375 #else
 376 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 KB for malloc()  */
 377 #endif /* CONFIG_BZIP2 */
 378
 379 #ifndef CFG_RAMBOOT
 380 #  define CFG_ENV_IS_IN_FLASH   1
 381 #  define CFG_ENV_SECT_SIZE     0x40000
 382 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
 383 #else
 384 #  define CFG_ENV_IS_IN_NVRAM   1
 385 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 386 #  define CFG_ENV_SIZE          0x200
 387 #endif /* CFG_RAMBOOT */
 388
 389
 390 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 391 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 392 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 393 #endif
 394
 395
 396 #define CFG_HID0_INIT           0
 397 #define CFG_HID0_FINAL          (HID0_ICE | HID0_IFEM | HID0_ABE )
 398
 399 #define CFG_HID2                0
 400
 401 #define CFG_SYPCR               0xFFFFFFC3
 402 #define CFG_BCR                 0x100C0000
 403 #define CFG_SIUMCR              0x0A200000
 404 #define CFG_SCCR                SCCR_DFBRG01
 405 #define CFG_BR0_PRELIM          CFG_FLASH_BASE | 0x00001801
 406 #define CFG_OR0_PRELIM          0xFF800876
 407 #define CFG_BR1_PRELIM          CFG_BCSR | 0x00001801
 408 #define CFG_OR1_PRELIM          0xFFFF8010
 409
 410 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
 411
 412 #if CONFIG_ADSTYPE == CFG_8272ADS
 413 #define CFG_BR3_PRELIM  (CFG_PCI_INT | 0x1801)  /* PCI interrupt controller */
 414 #define CFG_OR3_PRELIM  0xFFFF8010
 415 #endif
 416
 417 #define CFG_RMR                 RMR_CSRE
 418 #define CFG_TMCNTSC             (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 419 #define CFG_PISCR               (PISCR_PS|PISCR_PTF|PISCR_PTE)
 420 #define CFG_RCCR                0
 421
 422 #if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS)
 423 #undef CFG_LSDRAM_BASE          /* No local bus SDRAM on these boards */
 424 #endif /* CONFIG_ADSTYPE == CFG_8266ADS */
 425
 426 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 427 #define CFG_OR2                 0xFE002EC0
 428 #define CFG_PSDMR               0x824B36A3
 429 #define CFG_PSRT                0x13
 430 #define CFG_LSDMR               0x828737A3
 431 #define CFG_LSRT                0x13
 432 #define CFG_MPTPR               0x2800
 433 #elif CONFIG_ADSTYPE == CFG_8272ADS
 434 #define CFG_OR2                 0xFC002CC0
 435 #define CFG_PSDMR               0x834E24A3
 436 #define CFG_PSRT                0x13
 437 #define CFG_MPTPR               0x2800
 438 #else
 439 #define CFG_OR2                 0xFF000CA0
 440 #define CFG_PSDMR               0x016EB452
 441 #define CFG_PSRT                0x21
 442 #define CFG_LSDMR               0x0086A522
 443 #define CFG_LSRT                0x21
 444 #define CFG_MPTPR               0x1900
 445 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 446
 447 #define CFG_RESET_ADDRESS       0x04400000
 448
 449 #if CONFIG_ADSTYPE == CFG_8272ADS
 450
 451 /* PCI Memory map (if different from default map */
 452 #define CFG_PCI_SLV_MEM_LOCAL   CFG_SDRAM_BASE          /* Local base */
 453 #define CFG_PCI_SLV_MEM_BUS             0x00000000              /* PCI base */
 454 #define CFG_PICMR0_MASK_ATTRIB  (PICMR_MASK_512MB | PICMR_ENABLE | \
 455                                  PICMR_PREFETCH_EN)
 456
 457 /*
 458  * These are the windows that allow the CPU to access PCI address space.
 459  * All three PCI master windows, which allow the CPU to access PCI
 460  * prefetch, non prefetch, and IO space (see below), must all fit within
 461  * these windows.
 462  */
 463
 464
 465
 466 /*
 467  * Master window that allows the CPU to access PCI Memory (prefetch).
 468  * This window will be setup with the second set of Outbound ATU registers
 469  * in the bridge.
 470  */
 471
 472 #define CFG_PCI_MSTR_MEM_LOCAL  0x80000000          /* Local base */
 473 #define CFG_PCI_MSTR_MEM_BUS    0x80000000          /* PCI base   */
 474 #define CFG_CPU_PCI_MEM_START   PCI_MSTR_MEM_LOCAL
 475 #define CFG_PCI_MSTR_MEM_SIZE   0x20000000          /* 512MB */
 476 #define CFG_POCMR0_MASK_ATTRIB  (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 477
 478 /*
 479  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 480  * This window will be setup with the second set of Outbound ATU registers
 481  * in the bridge.
 482  */
 483
 484 #define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
 485 #define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
 486 #define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
 487 #define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
 488 #define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 489
 490 /*
 491  * Master window that allows the CPU to access PCI IO space.
 492  * This window will be setup with the first set of Outbound ATU registers
 493  * in the bridge.
 494  */
 495
 496 #define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
 497 #define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
 498 #define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
 499 #define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
 500 #define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
 501
 502
 503 /* PCIBR0 - for PCI IO*/
 504 #define CFG_PCI_MSTR0_LOCAL             CFG_PCI_MSTR_IO_LOCAL           /* Local base */
 505 #define CFG_PCIMSK0_MASK                ~(CFG_PCI_MSTR_IO_SIZE - 1U)    /* Size of window */
 506 /* PCIBR1 - prefetch and non-prefetch regions joined together */
 507 #define CFG_PCI_MSTR1_LOCAL             CFG_PCI_MSTR_MEM_LOCAL
 508 #define CFG_PCIMSK1_MASK                ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
 509
 510 #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
 511
 512 #endif /* __CONFIG_H */