include/configs/MPC8260ADS.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stuart Hughes <stuarth@lineo.com>
   4  * This file is based on similar values for other boards found in other
   5  * U-Boot config files, and some that I found in the mpc8260ads manual.
   6  *
   7  * Note: my board is a PILOT rev.
   8  * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36
  37 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
  38 #define CONFIG_MPC8260ADS       1       /* ...on motorola ads board */
  39
  40 #define CONFIG_BOARD_PRE_INIT   1       /* Call board_pre_init  */
  41
  42 /* allow serial and ethaddr to be overwritten */
  43 #define CONFIG_ENV_OVERWRITE
  44
  45 /*
  46  * select serial console configuration
  47  *
  48  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  49  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  50  * for SCC).
  51  *
  52  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  53  * defined elsewhere (for example, on the cogent platform, there are serial
  54  * ports on the motherboard which are used for the serial console - see
  55  * cogent/cma101/serial.[ch]).
  56  */
  57 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  58 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  59 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  60 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  61
  62 /*
  63  * select ethernet configuration
  64  *
  65  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  66  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  67  * for FCC)
  68  *
  69  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  70  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  71  * from CONFIG_COMMANDS to remove support for networking.
  72  */
  73 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
  74 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
  75 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  76
  77 #ifdef CONFIG_ETHER_ON_FCC
  78
  79 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
  80
  81 #if (CONFIG_ETHER_INDEX == 2)
  82 /*
  83  * - Rx-CLK is CLK13
  84  * - Tx-CLK is CLK14
  85  * - Select bus for bd/buffers (see 28-13)
  86  * - Full duplex
  87  */
  88 # define CFG_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  89 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  90 # define CFG_CPMFCR_RAMTYPE     0
  91 # define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
  92
  93 #endif  /* CONFIG_ETHER_INDEX */
  94
  95 #define CONFIG_MII                      /* MII PHY management           */
  96 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
  97 /*
  98  * GPIO pins used for bit-banged MII communications
  99  */
 100 #define MDIO_PORT       2               /* Port C */
 101 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 102 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 103 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 104
 105 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 106                         else    iop->pdat &= ~0x00400000
 107
 108 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 109                         else    iop->pdat &= ~0x00200000
 110
 111 #define MIIDELAY        udelay(1)
 112
 113 #endif /* CONFIG_ETHER_ON_FCC */
 114
 115 /* other options */
 116 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 117 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 118 #define CFG_I2C_SLAVE           0x7F
 119
 120 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 121 #define CONFIG_SPD_ADDR         0x50
 122 #endif
 123
 124 #ifndef CONFIG_SDRAM_PBI
 125 #define CONFIG_SDRAM_PBI        1 /* By default, use page-based interleaving */
 126 #endif
 127
 128 #ifndef CONFIG_8260_CLKIN
 129 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 130 #endif
 131 #define CONFIG_BAUDRATE         115200
 132
 133 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 134                                  CFG_CMD_BEDBUG | \
 135                                  CFG_CMD_BMP    | \
 136                                  CFG_CMD_BSP    | \
 137                                  CFG_CMD_DATE   | \
 138                                  CFG_CMD_DOC    | \
 139                                  CFG_CMD_DTT    | \
 140                                  CFG_CMD_EEPROM | \
 141                                  CFG_CMD_ELF    | \
 142                                  CFG_CMD_FDC    | \
 143                                  CFG_CMD_FDOS   | \
 144                                  CFG_CMD_HWFLOW | \
 145                                  CFG_CMD_IDE    | \
 146                                  CFG_CMD_JFFS2  | \
 147                                  CFG_CMD_KGDB   | \
 148                                  CFG_CMD_NAND   | \
 149                                  CFG_CMD_MII    | \
 150                                  CFG_CMD_MMC    | \
 151                                  CFG_CMD_PCI    | \
 152                                  CFG_CMD_PCMCIA | \
 153                                  CFG_CMD_SCSI   | \
 154                                  CFG_CMD_SPI    | \
 155                                  CFG_CMD_VFD    | \
 156                                  CFG_CMD_USB    ) )
 157
 158 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 159 #include <cmd_confdefs.h>
 160
 161
 162 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 163 #define CONFIG_BOOTCOMMAND      "bootm 100000"  /* autoboot command */
 164 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 165
 166 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 167 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 168 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 169 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 170 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 171 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 172 #endif
 173
 174 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 175
 176 /*
 177  * Miscellaneous configurable options
 178  */
 179 #define CFG_LONGHELP                    /* undef to save memory     */
 180 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt   */
 181 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 182 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size  */
 183 #else
 184 #define CFG_CBSIZE      256                     /* Console I/O Buffer Size  */
 185 #endif
 186 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 187 #define CFG_MAXARGS     16                      /* max number of command args   */
 188 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 189
 190 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 191 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 192
 193 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 194
 195 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 196
 197 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 198
 199 #define CFG_FLASH_BASE          0xff800000
 200 #define FLASH_BASE              0xff800000
 201 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 202 #define CFG_MAX_FLASH_SECT      32      /* max num of sects on one chip */
 203 #define CFG_FLASH_SIZE          8
 204 #define CFG_FLASH_ERASE_TOUT    8000    /* Timeout for Flash Erase (in ms)    */
 205 #define CFG_FLASH_WRITE_TOUT    5       /* Timeout for Flash Write (in ms)    */
 206
 207 /* this is stuff came out of the Motorola docs */
 208 #define CFG_DEFAULT_IMMR        0x0F010000
 209
 210 #define CFG_IMMR                0xF0000000
 211 #define CFG_BCSR                0x04500000
 212 #define CFG_SDRAM_BASE          0x00000000
 213 #define CFG_LSDRAM_BASE         0x04000000
 214
 215 #define RS232EN_1               0x02000002
 216 #define RS232EN_2               0x01000001
 217 #define FETHIEN                 0x08000008
 218 #define FETH_RST                0x04000004
 219
 220 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 221 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 222 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 223 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 224 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 225
 226
 227 /* 0x0EA28205 */
 228 #define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                       |\
 229                             ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
 230                             ( HRCW_BMS | HRCW_APPC10 )                      |\
 231                             ( HRCW_MODCK_H0101 )                             \
 232                         )
 233
 234 /* no slaves */
 235 #define CFG_HRCW_SLAVE1 0
 236 #define CFG_HRCW_SLAVE2 0
 237 #define CFG_HRCW_SLAVE3 0
 238 #define CFG_HRCW_SLAVE4 0
 239 #define CFG_HRCW_SLAVE5 0
 240 #define CFG_HRCW_SLAVE6 0
 241 #define CFG_HRCW_SLAVE7 0
 242
 243 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 244 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 245
 246 #define CFG_MONITOR_BASE    TEXT_BASE
 247 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 248 #   define CFG_RAMBOOT
 249 #endif
 250
 251 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 252 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 253 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 254
 255 #ifndef CFG_RAMBOOT
 256 #  define CFG_ENV_IS_IN_FLASH   1
 257 #  define CFG_ENV_SECT_SIZE     0x40000
 258 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
 259 #else
 260 #  define CFG_ENV_IS_IN_NVRAM   1
 261 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 262 #  define CFG_ENV_SIZE          0x200
 263 #endif /* CFG_RAMBOOT */
 264
 265
 266 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 267 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 268 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 269 #endif
 270
 271
 272 #define CFG_HID0_INIT           0
 273 #define CFG_HID0_FINAL          (HID0_ICE | HID0_IFEM | HID0_ABE )
 274
 275 #define CFG_HID2                0
 276
 277 #define CFG_SYPCR               0xFFFFFFC3
 278 #define CFG_BCR                 0x100C0000
 279 #define CFG_SIUMCR              0x0A200000
 280 #define CFG_SCCR                0x00000000
 281 #define CFG_BR0_PRELIM          0xFF801801
 282 #define CFG_OR0_PRELIM          0xFF800836
 283 #define CFG_BR1_PRELIM          0x04501801
 284 #define CFG_OR1_PRELIM          0xFFFF8010
 285
 286 #define CFG_RMR                 0
 287 #define CFG_TMCNTSC             (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 288 #define CFG_PISCR               (PISCR_PS|PISCR_PTF|PISCR_PTE)
 289 #define CFG_RCCR                0
 290 #define CFG_PSDMR               0x016EB452
 291 #define CFG_MPTPR               0x00001900
 292 #define CFG_PSRT                0x00000021
 293
 294 #define CFG_RESET_ADDRESS       0x04400000
 295
 296 #endif /* __CONFIG_H */