include/configs/MPC8266ADS.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stuart Hughes <stuarth@lineo.com>
   4  * This file is based on similar values for other boards found in other
   5  * U-Boot config files, and some that I found in the mpc8260ads manual.
   6  *
   7  * Note: my board is a PILOT rev.
   8  * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
  31  */
  32
  33 /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  34    !!                                                                 !!
  35    !!  This configuration requires JP3 to be in position 1-2 to work  !!
  36    !!  To make it work for the default, the TEXT_BASE define in       !!
  37    !!  board/mpc8266ads/config.mk must be changed from 0xfe000000 to  !!
  38    !!  0xfff00000                                                     !!
  39    !!  The CFG_HRCW_MASTER define below must also be changed to match !!
  40    !!                                                                 !!
  41    !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  42  */
  43
  44 #ifndef __CONFIG_H
  45 #define __CONFIG_H
  46
  47 /*
  48  * High Level Configuration Options
  49  * (easy to change)
  50  */
  51
  52 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU       */
  53 #define CONFIG_MPC8266ADS       1       /* ...on motorola ADS board     */
  54 #define CONFIG_CPM2             1       /* Has a CPM2 */
  55
  56 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  57
  58 /* allow serial and ethaddr to be overwritten */
  59 #define CONFIG_ENV_OVERWRITE
  60
  61 /*
  62  * select serial console configuration
  63  *
  64  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  65  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  66  * for SCC).
  67  *
  68  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  69  * defined elsewhere (for example, on the cogent platform, there are serial
  70  * ports on the motherboard which are used for the serial console - see
  71  * cogent/cma101/serial.[ch]).
  72  */
  73 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  74 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  75 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  76 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  77
  78 /*
  79  * select ethernet configuration
  80  *
  81  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  82  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  83  * for FCC)
  84  *
  85  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  86  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  87  * from CONFIG_COMMANDS to remove support for networking.
  88  */
  89 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
  90 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
  91 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  92 #define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
  93 #define CONFIG_MII                      /* MII PHY management           */
  94 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
  95 /*
  96  * Port pins used for bit-banged MII communictions (if applicable).
  97  */
  98 #define MDIO_PORT       2       /* Port C */
  99 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 100 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 101 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 102
 103 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 104                         else    iop->pdat &= ~0x00400000
 105
 106 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 107                         else    iop->pdat &= ~0x00200000
 108
 109 #define MIIDELAY        udelay(1)
 110
 111 #if (CONFIG_ETHER_INDEX == 2)
 112
 113 /*
 114  * - Rx-CLK is CLK13
 115  * - Tx-CLK is CLK14
 116  * - Select bus for bd/buffers (see 28-13)
 117  * - Half duplex
 118  */
 119 # define CFG_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 120 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 121 # define CFG_CPMFCR_RAMTYPE     0
 122 # define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
 123
 124 #endif  /* CONFIG_ETHER_INDEX */
 125
 126 /* other options */
 127 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 128 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 129 #define CFG_I2C_SLAVE           0x7F
 130 #define CFG_I2C_EEPROM_ADDR_LEN 1
 131
 132 /* PCI */
 133 #define CONFIG_PCI
 134 #define CONFIG_PCI_PNP
 135 #define CONFIG_PCI_BOOTDELAY 0
 136 #undef CONFIG_PCI_SCAN_SHOW
 137
 138 /*-----------------------------------------------------------------------
 139  * Definitions for Serial Presence Detect EEPROM address
 140  * (to get SDRAM settings)
 141  */
 142 #define SPD_EEPROM_ADDRESS      0x50
 143
 144
 145 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 146 #define CONFIG_BAUDRATE         115200
 147
 148
 149 #define CONFIG_COMMANDS       ( CFG_CMD_ALL & ~( \
 150                                 CFG_CMD_BEDBUG  | \
 151                                 CFG_CMD_BMP     | \
 152                                 CFG_CMD_BSP     | \
 153                                 CFG_CMD_DATE    | \
 154                                 CFG_CMD_DHCP    | \
 155                                 CFG_CMD_DISPLAY | \
 156                                 CFG_CMD_DOC     | \
 157                                 CFG_CMD_DTT     | \
 158                                 CFG_CMD_EEPROM  | \
 159                                 CFG_CMD_ELF     | \
 160                                 CFG_CMD_EXT2    | \
 161                                 CFG_CMD_FDC     | \
 162                                 CFG_CMD_FDOS    | \
 163                                 CFG_CMD_HWFLOW  | \
 164                                 CFG_CMD_IDE     | \
 165                                 CFG_CMD_JFFS2   | \
 166                                 CFG_CMD_KGDB    | \
 167                                 CFG_CMD_MMC     | \
 168                                 CFG_CMD_NAND    | \
 169                                 CFG_CMD_PCMCIA  | \
 170                                 CFG_CMD_REISER  | \
 171                                 CFG_CMD_SCSI    | \
 172                                 CFG_CMD_SPI     | \
 173                                 CFG_CMD_SNTP    | \
 174                                 CFG_CMD_VFD     | \
 175                                 CFG_CMD_UNIVERSE | \
 176                                 CFG_CMD_USB     | \
 177                                 CFG_CMD_XIMG    ) )
 178
 179 /* Define a command string that is automatically executed when no character
 180  * is read on the console interface withing "Boot Delay" after reset.
 181  */
 182 #undef  CONFIG_BOOT_ROOT_INITRD         /* Use ram disk for the root file system */
 183 #define CONFIG_BOOT_ROOT_NFS            /* Use a NFS mounted root file system */
 184
 185 #ifdef CONFIG_BOOT_ROOT_INITRD
 186 #define CONFIG_BOOTCOMMAND \
 187         "version;" \
 188         "echo;" \
 189         "bootp;" \
 190         "setenv bootargs root=/dev/ram0 rw " \
 191         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 192         "bootm"
 193 #endif /* CONFIG_BOOT_ROOT_INITRD */
 194
 195 #ifdef CONFIG_BOOT_ROOT_NFS
 196 #define CONFIG_BOOTCOMMAND \
 197         "version;" \
 198         "echo;" \
 199         "bootp;" \
 200         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
 201         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
 202         "bootm"
 203 #endif /* CONFIG_BOOT_ROOT_NFS */
 204
 205 /* Add support for a few extra bootp options like:
 206  *      - File size
 207  *      - DNS
 208  */
 209 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
 210                                  CONFIG_BOOTP_BOOTFILESIZE | \
 211                                  CONFIG_BOOTP_DNS)
 212
 213 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 214 #include <cmd_confdefs.h>
 215
 216
 217 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 218
 219 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 220 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 221 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 222 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 223 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 224 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 225 #endif
 226
 227 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 228
 229 /*
 230  * Miscellaneous configurable options
 231  */
 232 #define CFG_LONGHELP                    /* undef to save memory     */
 233 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt   */
 234 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 235 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size  */
 236 #else
 237 #define CFG_CBSIZE      256                     /* Console I/O Buffer Size  */
 238 #endif
 239 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 240 #define CFG_MAXARGS     16                      /* max number of command args   */
 241 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 242
 243 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 244 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 245
 246 #undef CONFIG_CLOCKS_IN_MHZ             /* clocks passsed to Linux in MHz */
 247                                         /* for versions < 2.4.5-pre5    */
 248
 249 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 250
 251 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 252
 253 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 254
 255 #define CFG_FLASH_BASE          0xFE000000
 256 #define FLASH_BASE              0xFE000000
 257 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 258 #define CFG_MAX_FLASH_SECT      32      /* max num of sects on one chip */
 259 #define CFG_FLASH_SIZE          8
 260 #define CFG_FLASH_ERASE_TOUT    8000    /* Timeout for Flash Erase (in ms)    */
 261 #define CFG_FLASH_WRITE_TOUT    5       /* Timeout for Flash Write (in ms)    */
 262
 263 #undef  CFG_FLASH_CHECKSUM
 264
 265 /* this is stuff came out of the Motorola docs */
 266 /* Only change this if you also change the Hardware configuration Word */
 267 #define CFG_DEFAULT_IMMR        0x0F010000
 268
 269 /* Set IMMR to 0xF0000000 or above to boot Linux  */
 270 #define CFG_IMMR                0xF0000000
 271 #define CFG_BCSR                0xF8000000
 272 #define CFG_PCI_INT             0xF8200000      /* PCI interrupt controller */
 273
 274 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
 275  */
 276 /*#define CONFIG_VERY_BIG_RAM   1*/
 277
 278 /* What should be the base address of SDRAM DIMM and how big is
 279  * it (in Mbytes)?  This will normally auto-configure via the SPD.
 280 */
 281 #define CFG_SDRAM_BASE 0x00000000
 282 #define CFG_SDRAM_SIZE 16
 283
 284 #define SDRAM_SPD_ADDR 0x50
 285
 286
 287 /*-----------------------------------------------------------------------
 288  * BR2,BR3 - Base Register
 289  *     Ref: Section 10.3.1 on page 10-14
 290  * OR2,OR3 - Option Register
 291  *     Ref: Section 10.3.2 on page 10-16
 292  *-----------------------------------------------------------------------
 293  */
 294
 295 /* Bank 2,3 - SDRAM DIMM
 296  */
 297
 298 /* The BR2 is configured as follows:
 299  *
 300  *     - Base address of 0x00000000
 301  *     - 64 bit port size (60x bus only)
 302  *     - Data errors checking is disabled
 303  *     - Read and write access
 304  *     - SDRAM 60x bus
 305  *     - Access are handled by the memory controller according to MSEL
 306  *     - Not used for atomic operations
 307  *     - No data pipelining is done
 308  *     - Valid
 309  */
 310 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
 311                          BRx_PS_64                      |\
 312                          BRx_MS_SDRAM_P                 |\
 313                          BRx_V)
 314
 315 #define CFG_BR3_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
 316                          BRx_PS_64                      |\
 317                          BRx_MS_SDRAM_P                 |\
 318                          BRx_V)
 319
 320 /* With a 64 MB DIMM, the OR2 is configured as follows:
 321  *
 322  *     - 64 MB
 323  *     - 4 internal banks per device
 324  *     - Row start address bit is A8 with PSDMR[PBI] = 0
 325  *     - 12 row address lines
 326  *     - Back-to-back page mode
 327  *     - Internal bank interleaving within save device enabled
 328  */
 329 #if (CFG_SDRAM_SIZE == 64)
 330 #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM_SIZE)      |\
 331                          ORxS_BPD_4                     |\
 332                          ORxS_ROWST_PBI0_A8             |\
 333                          ORxS_NUMR_12)
 334 #elif (CFG_SDRAM_SIZE == 16)
 335 #define CFG_OR2_PRELIM  (0xFF000C80)
 336 #else
 337 #error "INVALID SDRAM CONFIGURATION"
 338 #endif
 339
 340 /*-----------------------------------------------------------------------
 341  * PSDMR - 60x Bus SDRAM Mode Register
 342  *     Ref: Section 10.3.3 on page 10-21
 343  *-----------------------------------------------------------------------
 344  */
 345
 346 #if (CFG_SDRAM_SIZE == 64)
 347 /* With a 64 MB DIMM, the PSDMR is configured as follows:
 348  *
 349  *     - Bank Based Interleaving,
 350  *     - Refresh Enable,
 351  *     - Address Multiplexing where A5 is output on A14 pin
 352  *       (A6 on A15, and so on),
 353  *     - use address pins A14-A16 as bank select,
 354  *     - A9 is output on SDA10 during an ACTIVATE command,
 355  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 356  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 357  *       is 3 clocks,
 358  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 359  *       2 clocks,
 360  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 361  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 362  *     - CAS Latency is 2.
 363  */
 364 #define CFG_PSDMR       (PSDMR_RFEN           |\
 365                          PSDMR_SDAM_A14_IS_A5 |\
 366                          PSDMR_BSMA_A14_A16   |\
 367                          PSDMR_SDA10_PBI0_A9  |\
 368                          PSDMR_RFRC_7_CLK     |\
 369                          PSDMR_PRETOACT_3W    |\
 370                          PSDMR_ACTTORW_2W     |\
 371                          PSDMR_LDOTOPRE_1C    |\
 372                          PSDMR_WRC_1C         |\
 373                          PSDMR_CL_2)
 374 #elif (CFG_SDRAM_SIZE == 16)
 375 /* With a 16 MB DIMM, the PSDMR is configured as follows:
 376  *
 377  *   configuration parameters found in Motorola documentation
 378  */
 379 #define CFG_PSDMR       (0x016EB452)
 380 #else
 381 #error "INVALID SDRAM CONFIGURATION"
 382 #endif
 383
 384
 385 #define RS232EN_1               0x02000002
 386 #define RS232EN_2               0x01000001
 387 #define FETHIEN                 0x08000008
 388 #define FETH_RST                0x04000004
 389
 390 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 391 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 392 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 393 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 394 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 395
 396
 397 /* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2)  */
 398 /* 0x0EB2B645 */
 399 #define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP )                              |\
 400                          ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 )           |\
 401                          ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 )  |\
 402                          ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )                   \
 403                         )
 404
 405 /* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3)  */
 406 /* #define CFG_HRCW_MASTER 0x0cb23645 */
 407
 408 /* This value should actually be situated in the first 256 bytes of the FLASH
 409         which on the standard MPC8266ADS board is at address 0xFF800000
 410         The linker script places it at 0xFFF00000 instead.
 411
 412         It still works, however, as long as the ADS board jumper JP3 is set to
 413         position 2-3 so the board is using the BCSR as Hardware Configuration Word
 414
 415         If you want to use the one defined here instead, ust copy the first 256 bytes from
 416         0xfff00000 to 0xff800000  (for 8MB flash)
 417
 418         - Rune
 419
 420 */
 421
 422 /* no slaves */
 423 #define CFG_HRCW_SLAVE1 0
 424 #define CFG_HRCW_SLAVE2 0
 425 #define CFG_HRCW_SLAVE3 0
 426 #define CFG_HRCW_SLAVE4 0
 427 #define CFG_HRCW_SLAVE5 0
 428 #define CFG_HRCW_SLAVE6 0
 429 #define CFG_HRCW_SLAVE7 0
 430
 431 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 432 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 433
 434 #define CFG_MONITOR_BASE    TEXT_BASE
 435 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 436 #   define CFG_RAMBOOT
 437 #endif
 438
 439 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 440 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 441 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 442
 443 #ifndef CFG_RAMBOOT
 444 #  define CFG_ENV_IS_IN_FLASH   1
 445 #    define CFG_ENV_ADDR        (CFG_MONITOR_BASE + 0x40000)
 446 #    define CFG_ENV_SECT_SIZE   0x40000
 447 #else
 448 #  define CFG_ENV_IS_IN_NVRAM   1
 449 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 450 #  define CFG_ENV_SIZE          0x200
 451 #endif /* CFG_RAMBOOT */
 452
 453
 454 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 455 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 456 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 457 #endif
 458
 459
 460 /*-----------------------------------------------------------------------
 461  * HIDx - Hardware Implementation-dependent Registers                    2-11
 462  *-----------------------------------------------------------------------
 463  * HID0 also contains cache control - initially enable both caches and
 464  * invalidate contents, then the final state leaves only the instruction
 465  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 466  * but Soft reset does not.
 467  *
 468  * HID1 has only read-only information - nothing to set.
 469  */
 470 /*#define CFG_HID0_INIT         0 */
 471 #define CFG_HID0_INIT   (HID0_ICE  |\
 472                          HID0_DCE  |\
 473                          HID0_ICFI |\
 474                          HID0_DCI  |\
 475                          HID0_IFEM |\
 476                          HID0_ABE)
 477
 478 #define CFG_HID0_FINAL          (HID0_ICE | HID0_IFEM | HID0_ABE )
 479
 480 #define CFG_HID2                0
 481
 482 #define CFG_SYPCR               0xFFFFFFC3
 483 #define CFG_BCR                 0x004C0000
 484 #define CFG_SIUMCR              0x4E64C000
 485 #define CFG_SCCR                0x00000000
 486
 487 /*      local bus memory map
 488  *
 489  *      0x00000000-0x03FFFFFF    64MB   SDRAM
 490  *      0x80000000-0x9FFFFFFF   512MB   outbound prefetchable PCI memory window
 491  *      0xA0000000-0xBFFFFFFF   512MB   outbound non-prefetchable PCI memory window
 492  *      0xF0000000-0xF001FFFF   128KB   MPC8266 internal memory
 493  *      0xF4000000-0xF7FFFFFF    64MB   outbound PCI I/O window
 494  *      0xF8000000-0xF8007FFF    32KB   BCSR
 495  *      0xF8100000-0xF8107FFF    32KB   ATM UNI
 496  *      0xF8200000-0xF8207FFF    32KB   PCI interrupt controller
 497  *      0xF8300000-0xF8307FFF    32KB   EEPROM
 498  *      0xFE000000-0xFFFFFFFF    32MB   flash
 499  */
 500 #define CFG_BR0_PRELIM  0xFE001801              /* flash */
 501 #define CFG_OR0_PRELIM  0xFE000836
 502 #define CFG_BR1_PRELIM  (CFG_BCSR | 0x1801)     /* BCSR */
 503 #define CFG_OR1_PRELIM  0xFFFF8010
 504 #define CFG_BR4_PRELIM  0xF8300801              /* EEPROM */
 505 #define CFG_OR4_PRELIM  0xFFFF8846
 506 #define CFG_BR5_PRELIM  0xF8100801              /* PM5350 ATM UNI */
 507 #define CFG_OR5_PRELIM  0xFFFF8E36
 508 #define CFG_BR8_PRELIM  (CFG_PCI_INT | 0x1801)  /* PCI interrupt controller */
 509 #define CFG_OR8_PRELIM  0xFFFF8010
 510
 511 #define CFG_RMR                 0x0001
 512 #define CFG_TMCNTSC             (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 513 #define CFG_PISCR               (PISCR_PS|PISCR_PTF|PISCR_PTE)
 514 #define CFG_RCCR                0
 515 #define CFG_MPTPR               0x00001900
 516 #define CFG_PSRT                0x00000021
 517
 518 /* This address must not exist */
 519 #define CFG_RESET_ADDRESS       0xFCFFFF00
 520
 521 /* PCI Memory map (if different from default map */
 522 #define CFG_PCI_SLV_MEM_LOCAL   CFG_SDRAM_BASE          /* Local base */
 523 #define CFG_PCI_SLV_MEM_BUS             0x00000000              /* PCI base */
 524 #define CFG_PICMR0_MASK_ATTRIB  (PICMR_MASK_512MB | PICMR_ENABLE | \
 525                                  PICMR_PREFETCH_EN)
 526
 527 /*
 528  * These are the windows that allow the CPU to access PCI address space.
 529  * All three PCI master windows, which allow the CPU to access PCI
 530  * prefetch, non prefetch, and IO space (see below), must all fit within
 531  * these windows.
 532  */
 533
 534 /* PCIBR0 */
 535 #define CFG_PCI_MSTR0_LOCAL             0x80000000              /* Local base */
 536 #define CFG_PCIMSK0_MASK                PCIMSK_1GB              /* Size of window */
 537 /* PCIBR1 */
 538 #define CFG_PCI_MSTR1_LOCAL             0xF4000000              /* Local base */
 539 #define CFG_PCIMSK1_MASK                PCIMSK_64MB             /* Size of window */
 540
 541 /*
 542  * Master window that allows the CPU to access PCI Memory (prefetch).
 543  * This window will be setup with the first set of Outbound ATU registers
 544  * in the bridge.
 545  */
 546
 547 #define CFG_PCI_MSTR_MEM_LOCAL  0x80000000                      /* Local base */
 548 #define CFG_PCI_MSTR_MEM_BUS    0x80000000                      /* PCI base   */
 549 #define CFG_CPU_PCI_MEM_START   PCI_MSTR_MEM_LOCAL
 550 #define CFG_PCI_MSTR_MEM_SIZE   0x20000000                      /* 512MB */
 551 #define CFG_POCMR0_MASK_ATTRIB  (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 552
 553 /*
 554  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 555  * This window will be setup with the second set of Outbound ATU registers
 556  * in the bridge.
 557  */
 558
 559 #define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000                  /* Local base */
 560 #define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000                  /* PCI base   */
 561 #define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
 562 #define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000                  /* 512MB */
 563 #define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 564
 565 /*
 566  * Master window that allows the CPU to access PCI IO space.
 567  * This window will be setup with the third set of Outbound ATU registers
 568  * in the bridge.
 569  */
 570
 571 #define CFG_PCI_MSTR_IO_LOCAL       0xF4000000                  /* Local base */
 572 #define CFG_PCI_MSTR_IO_BUS         0xF4000000                  /* PCI base   */
 573 #define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
 574 #define CFG_PCI_MSTR_IO_SIZE        0x04000000                  /* 64MB */
 575 #define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
 576
 577 /*
 578  * JFFS2 partitions
 579  *
 580  */
 581 /* No command line, one static partition, whole device */
 582 #undef CONFIG_JFFS2_CMDLINE
 583 #define CONFIG_JFFS2_DEV                "nor0"
 584 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 585 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 586
 587 /* mtdparts command line support */
 588 /*
 589 #define CONFIG_JFFS2_CMDLINE
 590 #define MTDIDS_DEFAULT          ""
 591 #define MTDPARTS_DEFAULT        ""
 592 */
 593
 594 #endif /* __CONFIG_H */