include/configs/MPC8313ERDB.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 /*
  23  * mpc8313epb board configuration file
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_E300             1
  33 #define CONFIG_MPC83XX          1
  34 #define CONFIG_MPC831X          1
  35 #define CONFIG_MPC8313          1
  36 #define CONFIG_MPC8313ERDB      1
  37
  38 #define CONFIG_PCI
  39 #define CONFIG_83XX_GENERIC_PCI
  40
  41 #ifdef CFG_66MHZ
  42 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  43 #elif defined(CFG_33MHZ)
  44 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
  45 #else
  46 #error Unknown oscillator frequency.
  47 #endif
  48
  49 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  50
  51 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
  52
  53 #define CFG_IMMR                0xE0000000
  54
  55 #define CFG_MEMTEST_START       0x00001000
  56 #define CFG_MEMTEST_END         0x07f00000
  57
  58 /* Early revs of this board will lock up hard when attempting
  59  * to access the PMC registers, unless a JTAG debugger is
  60  * connected, or some resistor modifications are made.
  61  */
  62 #define CFG_8313ERDB_BROKEN_PMC 1
  63
  64 #define CFG_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
  65 #define CFG_ACR_RPTCNT          3       /* Arbiter repeat count (0-7) */
  66
  67 /*
  68  * DDR Setup
  69  */
  70 #define CFG_DDR_BASE            0x00000000      /* DDR is system memory*/
  71 #define CFG_SDRAM_BASE          CFG_DDR_BASE
  72 #define CFG_DDR_SDRAM_BASE      CFG_DDR_BASE
  73
  74 /*
  75  * Manually set up DDR parameters, as this board does not
  76  * seem to have the SPD connected to I2C.
  77  */
  78 #define CFG_DDR_SIZE            128             /* MB */
  79 #define CFG_DDR_CONFIG          ( CSCONFIG_EN | CSCONFIG_AP \
  80                                 | 0x00040000 /* TODO */ \
  81                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
  82                                 /* 0x80840102 */
  83
  84 #define CFG_DDR_TIMING_3        0x00000000
  85 #define CFG_DDR_TIMING_0        ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
  86                                 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
  87                                 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
  88                                 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
  89                                 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
  90                                 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
  91                                 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
  92                                 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
  93                                 /* 0x00220802 */
  94 #define CFG_DDR_TIMING_1        ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
  95                                 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
  96                                 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
  97                                 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
  98                                 | (13 << TIMING_CFG1_REFREC_SHIFT ) \
  99                                 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
 100                                 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 101                                 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 102                                 /* 0x3935d322 */
 103 #define CFG_DDR_TIMING_2        ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 104                                 | (31 << TIMING_CFG2_CPO_SHIFT ) \
 105                                 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 106                                 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 107                                 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 108                                 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 109                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 110                                 /* 0x0f9048ca */ /* P9-45,may need tuning */
 111 #define CFG_DDR_INTERVAL        ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 112                                 | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 113                                 /* 0x03200064 */
 114 #if defined(CONFIG_DDR_2T_TIMING)
 115 #define CFG_SDRAM_CFG           ( SDRAM_CFG_SREN \
 116                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 117                                 | SDRAM_CFG_2T_EN \
 118                                 | SDRAM_CFG_DBW_32 )
 119 #else
 120 #define CFG_SDRAM_CFG           ( SDRAM_CFG_SREN \
 121                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 122                                 | SDRAM_CFG_32_BE )
 123                                 /* 0x43080000 */
 124 #endif
 125 #define CFG_SDRAM_CFG2          0x00401000;
 126 /* set burst length to 8 for 32-bit data path */
 127 #define CFG_DDR_MODE            ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
 128                                 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
 129                                 /* 0x44400232 */
 130 #define CFG_DDR_MODE_2          0x8000C000;
 131
 132 #define CFG_DDR_CLK_CNTL        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 133                                 /*0x02000000*/
 134 #define CFG_DDRCDR_VALUE        ( DDRCDR_EN \
 135                                 | DDRCDR_PZ_NOMZ \
 136                                 | DDRCDR_NZ_NOMZ \
 137                                 | DDRCDR_M_ODR )
 138
 139 /*
 140  * FLASH on the Local Bus
 141  */
 142 #define CFG_FLASH_CFI                           /* use the Common Flash Interface */
 143 #define CFG_FLASH_CFI_DRIVER                    /* use the CFI driver */
 144 #define CFG_FLASH_BASE          0xFE000000      /* start of FLASH   */
 145 #define CFG_FLASH_SIZE          8               /* flash size in MB */
 146 #define CFG_FLASH_EMPTY_INFO                    /* display empty sectors */
 147 #define CFG_FLASH_USE_BUFFER_WRITE              /* buffer up multiple bytes */
 148
 149 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE |       /* flash Base address */ \
 150                                 (2 << BR_PS_SHIFT) |    /* 16 bit port size */ \
 151                                 BR_V)                   /* valid */
 152 #define CFG_OR0_PRELIM          ( 0xFF000000            /* 16 MByte */ \
 153                                 | OR_GPCM_XACS \
 154                                 | OR_GPCM_SCY_9 \
 155                                 | OR_GPCM_EHTR \
 156                                 | OR_GPCM_EAD )
 157                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
 158 #define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE  /* window base at flash base */
 159 #define CFG_LBLAWAR0_PRELIM     0x80000017      /* 16 MB window size */
 160
 161 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 162 #define CFG_MAX_FLASH_SECT      135             /* sectors per device */
 163
 164 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 165 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 166
 167 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 168
 169 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 170 #define CFG_RAMBOOT
 171 #endif
 172
 173 #define CFG_INIT_RAM_LOCK       1
 174 #define CFG_INIT_RAM_ADDR       0xFD000000      /* Initial RAM address */
 175 #define CFG_INIT_RAM_END        0x1000          /* End of used area in RAM*/
 176
 177 #define CFG_GBL_DATA_SIZE       0x100           /* num bytes initial data */
 178 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 179 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 180
 181 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 182 #define CFG_MALLOC_LEN          (512 * 1024)    /* Reserved for malloc */
 183
 184 /*
 185  * Local Bus LCRR and LBCR regs
 186  */
 187 #define CFG_LCRR        LCRR_EADC_1 | LCRR_CLKDIV_2     /* 0x00010002 */
 188 #define CFG_LBC_LBCR    ( 0x00040000 /* TODO */ \
 189                         | (0xFF << LBCR_BMT_SHIFT) \
 190                         | 0xF ) /* 0x0004ff0f */
 191
 192 #define CFG_LBC_MRTPR   0x20000000  /*TODO */   /* LB refresh timer prescal, 266MHz/32 */
 193
 194 /* drivers/nand/nand.c */
 195 #define CFG_NAND_BASE           0xE2800000      /* 0xF0000000 */
 196 #define CFG_MAX_NAND_DEVICE     1
 197 #define NAND_MAX_CHIPS          1
 198 #define CONFIG_MTD_NAND_VERIFY_WRITE
 199
 200 #define CFG_BR1_PRELIM          ( CFG_NAND_BASE \
 201                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 202                                 | BR_PS_8               /* Port Size = 8 bit */ \
 203                                 | BR_MS_FCM             /* MSEL = FCM */ \
 204                                 | BR_V )                /* valid */
 205 #define CFG_OR1_PRELIM          ( 0xFFFF8000            /* length 32K */ \
 206                                 | OR_FCM_CSCT \
 207                                 | OR_FCM_CST \
 208                                 | OR_FCM_CHT \
 209                                 | OR_FCM_SCY_1 \
 210                                 | OR_FCM_TRLX \
 211                                 | OR_FCM_EHTR )
 212                                 /* 0xFFFF8396 */
 213 #define CFG_LBLAWBAR1_PRELIM    CFG_NAND_BASE
 214 #define CFG_LBLAWAR1_PRELIM     0x8000000E      /* 32KB  */
 215
 216 #define CFG_VSC7385_BASE        0xF0000000
 217
 218 #define CONFIG_VSC7385_ENET                     /* VSC7385 ethernet support */
 219 #define CFG_BR2_PRELIM          0xf0000801      /* VSC7385 Base address */
 220 #define CFG_OR2_PRELIM          0xfffe09ff      /* VSC7385, 128K bytes*/
 221 #define CFG_LBLAWBAR2_PRELIM    CFG_VSC7385_BASE/* Access window base at VSC7385 base */
 222 #define CFG_LBLAWAR2_PRELIM     0x80000010      /* Access window size 128K */
 223
 224 /* local bus read write buffer mapping */
 225 #define CFG_BR3_PRELIM          0xFA000801      /* map at 0xFA000000 */
 226 #define CFG_OR3_PRELIM          0xFFFF8FF7      /* 32kB */
 227 #define CFG_LBLAWBAR3_PRELIM    0xFA000000
 228 #define CFG_LBLAWAR3_PRELIM     0x8000000E      /* 32KB  */
 229
 230 /* pass open firmware flat tree */
 231 #define CONFIG_OF_LIBFDT        1
 232 #define CONFIG_OF_BOARD_SETUP   1
 233
 234 #define OF_CPU                  "PowerPC,8313@0"
 235 #define OF_SOC                  "soc8313@e0000000"
 236 #define OF_TBCLK                (bd->bi_busfreq / 4)
 237 #define OF_STDOUT_PATH          "/soc8313@e0000000/serial@4500"
 238
 239 /*
 240  * Serial Port
 241  */
 242 #define CONFIG_CONS_INDEX       1
 243 #define CFG_NS16550
 244 #define CFG_NS16550_SERIAL
 245 #define CFG_NS16550_REG_SIZE    1
 246 #define CFG_NS16550_CLK         get_bus_freq(0)
 247
 248 #define CFG_BAUDRATE_TABLE      \
 249         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 250
 251 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
 252 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 253
 254 /* Use the HUSH parser */
 255 #define CFG_HUSH_PARSER
 256 #define CFG_PROMPT_HUSH_PS2 "> "
 257
 258 /* I2C */
 259 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 260 #define CONFIG_FSL_I2C
 261 #define CONFIG_I2C_MULTI_BUS
 262 #define CONFIG_I2C_CMD_TREE
 263 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 264 #define CFG_I2C_SLAVE           0x7F
 265 #define CFG_I2C_NOPROBES        {{0,0x69}} /* Don't probe these addrs */
 266 #define CFG_I2C_OFFSET          0x3000
 267 #define CFG_I2C2_OFFSET         0x3100
 268
 269 /* TSEC */
 270 #define CFG_TSEC1_OFFSET        0x24000
 271 #define CFG_TSEC1               (CFG_IMMR+CFG_TSEC1_OFFSET)
 272 #define CFG_TSEC2_OFFSET        0x25000
 273 #define CFG_TSEC2               (CFG_IMMR+CFG_TSEC2_OFFSET)
 274 #define CONFIG_NET_MULTI
 275
 276 /*
 277  * General PCI
 278  * Addresses are mapped 1-1.
 279  */
 280 #define CFG_PCI1_MEM_BASE       0x80000000
 281 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 282 #define CFG_PCI1_MEM_SIZE       0x10000000      /* 256M */
 283 #define CFG_PCI1_MMIO_BASE      0x90000000
 284 #define CFG_PCI1_MMIO_PHYS      CFG_PCI1_MMIO_BASE
 285 #define CFG_PCI1_MMIO_SIZE      0x10000000      /* 256M */
 286 #define CFG_PCI1_IO_BASE        0x00000000
 287 #define CFG_PCI1_IO_PHYS        0xE2000000
 288 #define CFG_PCI1_IO_SIZE        0x00100000      /* 1M */
 289
 290 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 291 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 292
 293 /*
 294  * TSEC configuration
 295  */
 296 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 297
 298 #ifndef CONFIG_NET_MULTI
 299 #define CONFIG_NET_MULTI                1
 300 #endif
 301
 302 #define CONFIG_GMII                     1       /* MII PHY management */
 303 #define CONFIG_TSEC1            1
 304
 305 #define CONFIG_TSEC1_NAME       "TSEC0"
 306 #define CONFIG_TSEC2            1
 307 #define CONFIG_TSEC2_NAME       "TSEC1"
 308 #define TSEC1_PHY_ADDR                  0x1c
 309 #define TSEC2_PHY_ADDR                  4
 310 #define TSEC1_FLAGS                     TSEC_GIGABIT
 311 #define TSEC2_FLAGS                     TSEC_GIGABIT
 312 #define TSEC1_PHYIDX                    0
 313 #define TSEC2_PHYIDX                    0
 314
 315 /* Options are: TSEC[0-1] */
 316 #define CONFIG_ETHPRIME                 "TSEC1"
 317
 318 /*
 319  * Configure on-board RTC
 320  */
 321 #define CONFIG_RTC_DS1337
 322 #define CFG_I2C_RTC_ADDR                0x68
 323
 324 /*
 325  * Environment
 326  */
 327 #ifndef CFG_RAMBOOT
 328         #define CFG_ENV_IS_IN_FLASH     1
 329         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 330         #define CFG_ENV_SECT_SIZE       0x10000 /* 64K(one sector) for env */
 331         #define CFG_ENV_SIZE            0x2000
 332
 333 /* Address and size of Redundant Environment Sector */
 334 #else
 335         #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only */
 336         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
 337         #define CFG_ENV_SIZE            0x2000
 338 #endif
 339
 340 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 341 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 342
 343 /*
 344  * BOOTP options
 345  */
 346 #define CONFIG_BOOTP_BOOTFILESIZE
 347 #define CONFIG_BOOTP_BOOTPATH
 348 #define CONFIG_BOOTP_GATEWAY
 349 #define CONFIG_BOOTP_HOSTNAME
 350
 351
 352 /*
 353  * Command line configuration.
 354  */
 355 #include <config_cmd_default.h>
 356
 357 #define CONFIG_CMD_PING
 358 #define CONFIG_CMD_DHCP
 359 #define CONFIG_CMD_I2C
 360 #define CONFIG_CMD_MII
 361 #define CONFIG_CMD_DATE
 362 #define CONFIG_CMD_PCI
 363
 364 #if defined(CFG_RAMBOOT)
 365     #undef CONFIG_CMD_ENV
 366     #undef CONFIG_CMD_LOADS
 367 #endif
 368
 369 #define CONFIG_CMDLINE_EDITING 1
 370
 371
 372 /*
 373  * Miscellaneous configurable options
 374  */
 375 #define CFG_LONGHELP                    /* undef to save memory */
 376 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 377 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 378 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 379
 380 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 381 #define CFG_MAXARGS     16              /* max number of command args */
 382 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 383 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 384
 385 /*
 386  * For booting Linux, the board info and command line data
 387  * have to be in the first 8 MB of memory, since this is
 388  * the maximum mapped by the Linux kernel during initialization.
 389  */
 390 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 391
 392 /* Cache Configuration */
 393 #define CFG_DCACHE_SIZE         16384
 394 #define CFG_CACHELINE_SIZE      32
 395 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value*/
 396
 397 #define CFG_RCWH_PCIHOST 0x80000000     /* PCIHOST  */
 398
 399 #ifdef CFG_66MHZ
 400
 401 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
 402 /* 0x62040000 */
 403 #define CFG_HRCW_LOW (\
 404         0x20000000 /* reserved, must be set */ |\
 405         HRCWL_DDRCM |\
 406         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 407         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 408         HRCWL_CSB_TO_CLKIN_2X1 |\
 409         HRCWL_CORE_TO_CSB_2X1)
 410
 411 #elif defined(CFG_33MHZ)
 412
 413 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
 414 /* 0x65040000 */
 415 #define CFG_HRCW_LOW (\
 416         0x20000000 /* reserved, must be set */ |\
 417         HRCWL_DDRCM |\
 418         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 419         HRCWL_DDR_TO_SCB_CLK_2X1 |\
 420         HRCWL_CSB_TO_CLKIN_5X1 |\
 421         HRCWL_CORE_TO_CSB_2X1)
 422
 423 #endif
 424
 425 /* 0xa0606c00 */
 426 #define CFG_HRCW_HIGH (\
 427         HRCWH_PCI_HOST |\
 428         HRCWH_PCI1_ARBITER_ENABLE |\
 429         HRCWH_CORE_ENABLE |\
 430         HRCWH_FROM_0X00000100 |\
 431         HRCWH_BOOTSEQ_DISABLE |\
 432         HRCWH_SW_WATCHDOG_DISABLE |\
 433         HRCWH_ROM_LOC_LOCAL_16BIT |\
 434         HRCWH_RL_EXT_LEGACY |\
 435         HRCWH_TSEC1M_IN_RGMII |\
 436         HRCWH_TSEC2M_IN_RGMII |\
 437         HRCWH_BIG_ENDIAN |\
 438         HRCWH_LALE_NORMAL)
 439
 440 /* System IO Config */
 441 #define CFG_SICRH       (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 442 #define CFG_SICRL       SICRL_USBDR                     /* Enable Internal USB Phy  */
 443
 444 #define CFG_HID0_INIT   0x000000000
 445 #define CFG_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
 446                          HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 447
 448 #define CFG_HID2 HID2_HBE
 449
 450 /* DDR @ 0x00000000 */
 451 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10)
 452 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 453
 454 /* PCI @ 0x80000000 */
 455 #define CFG_IBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_10)
 456 #define CFG_IBAT1U      (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 457 #define CFG_IBAT2L      (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 458 #define CFG_IBAT2U      (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 459
 460 /* PCI2 not supported on 8313 */
 461 #define CFG_IBAT3L      (0)
 462 #define CFG_IBAT3U      (0)
 463 #define CFG_IBAT4L      (0)
 464 #define CFG_IBAT4U      (0)
 465
 466 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 467 #define CFG_IBAT5L      (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 468 #define CFG_IBAT5U      (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 469
 470 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 471 #define CFG_IBAT6L      (0xF0000000 | BATL_PP_10)
 472 #define CFG_IBAT6U      (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 473
 474 #define CFG_IBAT7L      (0)
 475 #define CFG_IBAT7U      (0)
 476
 477 #define CFG_DBAT0L      CFG_IBAT0L
 478 #define CFG_DBAT0U      CFG_IBAT0U
 479 #define CFG_DBAT1L      CFG_IBAT1L
 480 #define CFG_DBAT1U      CFG_IBAT1U
 481 #define CFG_DBAT2L      CFG_IBAT2L
 482 #define CFG_DBAT2U      CFG_IBAT2U
 483 #define CFG_DBAT3L      CFG_IBAT3L
 484 #define CFG_DBAT3U      CFG_IBAT3U
 485 #define CFG_DBAT4L      CFG_IBAT4L
 486 #define CFG_DBAT4U      CFG_IBAT4U
 487 #define CFG_DBAT5L      CFG_IBAT5L
 488 #define CFG_DBAT5U      CFG_IBAT5U
 489 #define CFG_DBAT6L      CFG_IBAT6L
 490 #define CFG_DBAT6U      CFG_IBAT6U
 491 #define CFG_DBAT7L      CFG_IBAT7L
 492 #define CFG_DBAT7U      CFG_IBAT7U
 493
 494 /*
 495  * Internal Definitions
 496  *
 497  * Boot Flags
 498  */
 499 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 500 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 501
 502 /*
 503  * Environment Configuration
 504  */
 505 #define CONFIG_ENV_OVERWRITE
 506
 507 #define CONFIG_ETHADDR          00:E0:0C:00:95:01
 508 #define CONFIG_HAS_ETH1
 509 #define CONFIG_HAS_ETH0
 510 #define CONFIG_ETH1ADDR         00:E0:0C:00:95:02
 511
 512 #define CONFIG_IPADDR           10.0.0.2
 513 #define CONFIG_SERVERIP         10.0.0.1
 514 #define CONFIG_GATEWAYIP        10.0.0.1
 515 #define CONFIG_NETMASK          255.0.0.0
 516 #define CONFIG_NETDEV           eth1
 517
 518 #define CONFIG_HOSTNAME         mpc8313erdb
 519 #define CONFIG_ROOTPATH         /nfs/root/path
 520 #define CONFIG_BOOTFILE         uImage
 521 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 522 #define CONFIG_FDTFILE          mpc8313erdb.dtb
 523
 524 #define CONFIG_LOADADDR         200000  /* default location for tftp and bootm */
 525 #define CONFIG_BOOTDELAY        -1      /* -1 disables auto-boot */
 526 #define CONFIG_BAUDRATE         115200
 527
 528 #define XMK_STR(x)      #x
 529 #define MK_STR(x)       XMK_STR(x)
 530
 531 #define CONFIG_EXTRA_ENV_SETTINGS \
 532         "netdev=" MK_STR(CONFIG_NETDEV) "\0"                            \
 533         "ethprime=TSEC1\0"                                              \
 534         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 535         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 536                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 537                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 538                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 539                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 540                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 541         "fdtaddr=400000\0"                                              \
 542         "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"                          \
 543         "console=ttyS0\0"                                               \
 544         "setbootargs=setenv bootargs "                                  \
 545                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 546         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
 547                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 548                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 549
 550 #define CONFIG_NFSBOOTCOMMAND                                           \
 551         "setenv rootdev /dev/nfs;"                                      \
 552         "run setbootargs;"                                                      \
 553         "run setipargs;"                                                        \
 554         "tftp $loadaddr $bootfile;"                                     \
 555         "tftp $fdtaddr $fdtfile;"                                       \
 556         "bootm $loadaddr - $fdtaddr"
 557
 558 #define CONFIG_RAMBOOTCOMMAND                                           \
 559         "setenv rootdev /dev/ram;"                                      \
 560         "run setbootargs;"                                              \
 561         "tftp $ramdiskaddr $ramdiskfile;"                               \
 562         "tftp $loadaddr $bootfile;"                                     \
 563         "tftp $fdtaddr $fdtfile;"                                       \
 564         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 565
 566 #undef MK_STR
 567 #undef XMK_STR
 568
 569 #endif  /* __CONFIG_H */