include/configs/MPC8315ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_E300             1 /* E300 family */
  32 #define CONFIG_MPC83XX          1 /* MPC83xx family */
  33 #define CONFIG_MPC831X          1 /* MPC831x CPU family */
  34 #define CONFIG_MPC8315          1 /* MPC8315 CPU specific */
  35 #define CONFIG_MPC8315ERDB      1 /* MPC8315ERDB board specific */
  36
  37 /*
  38  * System Clock Setup
  39  */
  40 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  41 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  42
  43 /*
  44  * Hardware Reset Configuration Word
  45  * if CLKIN is 66.66MHz, then
  46  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
  47  */
  48 #define CFG_HRCW_LOW (\
  49         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  50         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  51         HRCWL_SVCOD_DIV_2 |\
  52         HRCWL_CSB_TO_CLKIN_2X1 |\
  53         HRCWL_CORE_TO_CSB_3X1)
  54 #define CFG_HRCW_HIGH (\
  55         HRCWH_PCI_HOST |\
  56         HRCWH_PCI1_ARBITER_ENABLE |\
  57         HRCWH_CORE_ENABLE |\
  58         HRCWH_FROM_0X00000100 |\
  59         HRCWH_BOOTSEQ_DISABLE |\
  60         HRCWH_SW_WATCHDOG_DISABLE |\
  61         HRCWH_ROM_LOC_LOCAL_16BIT |\
  62         HRCWH_RL_EXT_LEGACY |\
  63         HRCWH_TSEC1M_IN_RGMII |\
  64         HRCWH_TSEC2M_IN_RGMII |\
  65         HRCWH_BIG_ENDIAN |\
  66         HRCWH_LALE_NORMAL)
  67
  68 /*
  69  * System IO Config
  70  */
  71 #define CFG_SICRH               0x00000000
  72 #define CFG_SICRL               0x00000000 /* 3.3V, no delay */
  73
  74 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  75
  76 /*
  77  * IMMR new address
  78  */
  79 #define CFG_IMMR                0xE0000000
  80
  81 /*
  82  * Arbiter Setup
  83  */
  84 #define CFG_ACR_PIPE_DEP        3 /* Arbiter pipeline depth is 4 */
  85 #define CFG_ACR_RPTCNT          3 /* Arbiter repeat count is 4 */
  86 #define CFG_SPCR_TSECEP         3 /* eTSEC emergency priority is highest */
  87
  88 /*
  89  * DDR Setup
  90  */
  91 #define CFG_DDR_BASE            0x00000000 /* DDR is system memory */
  92 #define CFG_SDRAM_BASE          CFG_DDR_BASE
  93 #define CFG_DDR_SDRAM_BASE      CFG_DDR_BASE
  94 #define CFG_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  95 #define CFG_DDRCDR_VALUE        ( DDRCDR_EN \
  96                                 | DDRCDR_PZ_LOZ \
  97                                 | DDRCDR_NZ_LOZ \
  98                                 | DDRCDR_ODT \
  99                                 | DDRCDR_Q_DRN )
 100                                 /* 0x7b880001 */
 101 /*
 102  * Manually set up DDR parameters
 103  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 104  */
 105 #define CFG_DDR_SIZE            128 /* MB */
 106 #define CFG_DDR_CS0_BNDS        0x00000007
 107 #define CFG_DDR_CS0_CONFIG      ( CSCONFIG_EN \
 108                                 | 0x00010000  /* ODT_WR to CSn */ \
 109                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
 110                                 /* 0x80010102 */
 111 #define CFG_DDR_TIMING_3        0x00000000
 112 #define CFG_DDR_TIMING_0        ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 113                                 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 114                                 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 115                                 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
 116                                 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
 117                                 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
 118                                 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 119                                 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 120                                 /* 0x00220802 */
 121 #define CFG_DDR_TIMING_1        ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
 122                                 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 123                                 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
 124                                 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
 125                                 | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
 126                                 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
 127                                 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 128                                 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 129                                 /* 0x39356222 */
 130 #define CFG_DDR_TIMING_2        ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 131                                 | ( 4 << TIMING_CFG2_CPO_SHIFT ) \
 132                                 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 133                                 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 134                                 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 135                                 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 136                                 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 137                                 /* 0x121048c7 */
 138 #define CFG_DDR_INTERVAL        ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 139                                 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 140                                 /* 0x03600100 */
 141 #define CFG_DDR_SDRAM_CFG       ( SDRAM_CFG_SREN \
 142                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 143                                 | SDRAM_CFG_32_BE )
 144                                 /* 0x43080000 */
 145 #define CFG_DDR_SDRAM_CFG2      0x00401000 /* 1 posted refresh */
 146 #define CFG_DDR_MODE            ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
 147                                 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
 148                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 149 #define CFG_DDR_MODE2           0x00000000
 150
 151 /*
 152  * Memory test
 153  */
 154 #undef CFG_DRAM_TEST            /* memory test, takes time */
 155 #define CFG_MEMTEST_START       0x00040000 /* memtest region */
 156 #define CFG_MEMTEST_END         0x00140000
 157
 158 /*
 159  * The reserved memory
 160  */
 161 #define CFG_MONITOR_BASE        TEXT_BASE /* start of monitor */
 162
 163 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 164 #define CFG_RAMBOOT
 165 #else
 166 #undef CFG_RAMBOOT
 167 #endif
 168
 169 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 170 #define CFG_MALLOC_LEN          (512 * 1024) /* Reserved for malloc */
 171
 172 /*
 173  * Initial RAM Base Address Setup
 174  */
 175 #define CFG_INIT_RAM_LOCK       1
 176 #define CFG_INIT_RAM_ADDR       0xE6000000 /* Initial RAM address */
 177 #define CFG_INIT_RAM_END        0x1000 /* End of used area in RAM */
 178 #define CFG_GBL_DATA_SIZE       0x100 /* num bytes initial data */
 179 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 180
 181 /*
 182  * Local Bus Configuration & Clock Setup
 183  */
 184 #define CFG_LCRR                (LCRR_DBYP | LCRR_CLKDIV_2)
 185 #define CFG_LBC_LBCR            0x00040000
 186
 187 /*
 188  * FLASH on the Local Bus
 189  */
 190 #define CFG_FLASH_CFI           /* use the Common Flash Interface */
 191 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 192 #define CFG_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
 193
 194 #define CFG_FLASH_BASE          0xFE000000 /* FLASH base address */
 195 #define CFG_FLASH_SIZE          8 /* FLASH size is 8M */
 196 #define CFG_FLASH_PROTECTION    1               /* Use h/w Flash protection. */
 197
 198 #define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE /* Window base at flash base */
 199 #define CFG_LBLAWAR0_PRELIM     0x80000016 /* 8MB window size */
 200
 201 #define CFG_BR0_PRELIM          ( CFG_FLASH_BASE        /* Flash Base address */ \
 202                                 | (2 << BR_PS_SHIFT)    /* 16 bit port size */ \
 203                                 | BR_V )                /* valid */
 204 #define CFG_OR0_PRELIM          ( (~(CFG_FLASH_SIZE - 1) << 20) \
 205                                 | OR_UPM_XAM \
 206                                 | OR_GPCM_CSNT \
 207                                 | OR_GPCM_ACS_DIV2 \
 208                                 | OR_GPCM_XACS \
 209                                 | OR_GPCM_SCY_15 \
 210                                 | OR_GPCM_TRLX \
 211                                 | OR_GPCM_EHTR \
 212                                 | OR_GPCM_EAD )
 213
 214 #define CFG_MAX_FLASH_BANKS     1 /* number of banks */
 215 #define CFG_MAX_FLASH_SECT      135 /* 127 64KB sectors and 8 8KB top sectors per device */
 216
 217 #undef CFG_FLASH_CHECKSUM
 218 #define CFG_FLASH_ERASE_TOUT    60000 /* Flash Erase Timeout (ms) */
 219 #define CFG_FLASH_WRITE_TOUT    500 /* Flash Write Timeout (ms) */
 220
 221 /*
 222  * NAND Flash on the Local Bus
 223  */
 224 #define CFG_NAND_BASE           0xE0600000      /* 0xE0600000 */
 225 #define CFG_MAX_NAND_DEVICE     1
 226 #define NAND_MAX_CHIPS          1
 227 #define CONFIG_MTD_NAND_VERIFY_WRITE
 228
 229 #define CFG_BR1_PRELIM          ( CFG_NAND_BASE \
 230                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 231                                 | BR_PS_8               /* Port Size = 8 bit */ \
 232                                 | BR_MS_FCM             /* MSEL = FCM */ \
 233                                 | BR_V )                /* valid */
 234 #define CFG_OR1_PRELIM          ( 0xFFFF8000            /* length 32K */ \
 235                                 | OR_FCM_CSCT \
 236                                 | OR_FCM_CST \
 237                                 | OR_FCM_CHT \
 238                                 | OR_FCM_SCY_1 \
 239                                 | OR_FCM_TRLX \
 240                                 | OR_FCM_EHTR )
 241                                 /* 0xFFFF8396 */
 242
 243 #define CFG_LBLAWBAR1_PRELIM    CFG_NAND_BASE
 244 #define CFG_LBLAWAR1_PRELIM     0x8000000E      /* 32KB  */
 245
 246 /*
 247  * Serial Port
 248  */
 249 #define CONFIG_CONS_INDEX       1
 250 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 251 #define CFG_NS16550
 252 #define CFG_NS16550_SERIAL
 253 #define CFG_NS16550_REG_SIZE    1
 254 #define CFG_NS16550_CLK         get_bus_freq(0)
 255
 256 #define CFG_BAUDRATE_TABLE  \
 257         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 258
 259 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
 260 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 261
 262 /* Use the HUSH parser */
 263 #define CFG_HUSH_PARSER
 264 #ifdef CFG_HUSH_PARSER
 265 #define CFG_PROMPT_HUSH_PS2 "> "
 266 #endif
 267
 268 /* Pass open firmware flat tree */
 269 #define CONFIG_OF_LIBFDT        1
 270 #define CONFIG_OF_BOARD_SETUP   1
 271 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 272
 273 /* I2C */
 274 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 275 #define CONFIG_FSL_I2C
 276 #define CFG_I2C_SPEED           400000 /* I2C speed and slave address */
 277 #define CFG_I2C_SLAVE           0x7F
 278 #define CFG_I2C_NOPROBES        {0x51} /* Don't probe these addrs */
 279 #define CFG_I2C_OFFSET          0x3000
 280 #define CFG_I2C2_OFFSET         0x3100
 281
 282 /*
 283  * Board info - revision and where boot from
 284  */
 285 #define CFG_I2C_PCF8574A_ADDR   0x39
 286
 287 /*
 288  * Config on-board RTC
 289  */
 290 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 291 #define CFG_I2C_RTC_ADDR        0x68 /* at address 0x68 */
 292
 293 /*
 294  * General PCI
 295  * Addresses are mapped 1-1.
 296  */
 297 #define CFG_PCI_MEM_BASE        0x80000000
 298 #define CFG_PCI_MEM_PHYS        CFG_PCI_MEM_BASE
 299 #define CFG_PCI_MEM_SIZE        0x10000000 /* 256M */
 300 #define CFG_PCI_MMIO_BASE       0x90000000
 301 #define CFG_PCI_MMIO_PHYS       CFG_PCI_MMIO_BASE
 302 #define CFG_PCI_MMIO_SIZE       0x10000000 /* 256M */
 303 #define CFG_PCI_IO_BASE         0x00000000
 304 #define CFG_PCI_IO_PHYS         0xE0300000
 305 #define CFG_PCI_IO_SIZE         0x100000 /* 1M */
 306
 307 #define CFG_PCI_SLV_MEM_LOCAL   CFG_SDRAM_BASE
 308 #define CFG_PCI_SLV_MEM_BUS     0x00000000
 309 #define CFG_PCI_SLV_MEM_SIZE    0x80000000
 310
 311 #define CONFIG_PCI
 312 #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
 313
 314 #define CONFIG_NET_MULTI
 315 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 316
 317 #define CONFIG_EEPRO100
 318 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 319 #define CFG_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 320
 321 #ifndef CONFIG_NET_MULTI
 322 #define CONFIG_NET_MULTI        1
 323 #endif
 324
 325 #define CONFIG_HAS_FSL_DR_USB
 326
 327 /*
 328  * TSEC
 329  */
 330 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 331 #define CFG_TSEC1_OFFSET        0x24000
 332 #define CFG_TSEC1               (CFG_IMMR+CFG_TSEC1_OFFSET)
 333 #define CFG_TSEC2_OFFSET        0x25000
 334 #define CFG_TSEC2               (CFG_IMMR+CFG_TSEC2_OFFSET)
 335
 336 /*
 337  * TSEC ethernet configuration
 338  */
 339 #define CONFIG_MII              1 /* MII PHY management */
 340 #define CONFIG_TSEC1            1
 341 #define CONFIG_TSEC1_NAME       "eTSEC0"
 342 #define CONFIG_TSEC2            1
 343 #define CONFIG_TSEC2_NAME       "eTSEC1"
 344 #define TSEC1_PHY_ADDR          0
 345 #define TSEC2_PHY_ADDR          1
 346 #define TSEC1_PHYIDX            0
 347 #define TSEC2_PHYIDX            0
 348 #define TSEC1_FLAGS             TSEC_GIGABIT
 349 #define TSEC2_FLAGS             TSEC_GIGABIT
 350
 351 /* Options are: eTSEC[0-1] */
 352 #define CONFIG_ETHPRIME         "eTSEC1"
 353
 354 /*
 355  * SATA
 356  */
 357 #define CONFIG_LIBATA
 358 #define CONFIG_FSL_SATA
 359
 360 #define CFG_SATA_MAX_DEVICE     2
 361 #define CONFIG_SATA1
 362 #define CFG_SATA1_OFFSET        0x18000
 363 #define CFG_SATA1               (CFG_IMMR + CFG_SATA1_OFFSET)
 364 #define CFG_SATA1_FLAGS         FLAGS_DMA
 365 #define CONFIG_SATA2
 366 #define CFG_SATA2_OFFSET        0x19000
 367 #define CFG_SATA2               (CFG_IMMR + CFG_SATA2_OFFSET)
 368 #define CFG_SATA2_FLAGS         FLAGS_DMA
 369
 370 #ifdef CONFIG_FSL_SATA
 371 #define CONFIG_LBA48
 372 #define CONFIG_CMD_SATA
 373 #define CONFIG_DOS_PARTITION
 374 #define CONFIG_CMD_EXT2
 375 #endif
 376
 377 /*
 378  * Environment
 379  */
 380 #ifndef CFG_RAMBOOT
 381         #define CONFIG_ENV_IS_IN_FLASH  1
 382         #define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 383         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 384         #define CONFIG_ENV_SIZE         0x2000
 385 #else
 386         #define CFG_NO_FLASH            1       /* Flash is not usable now */
 387         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 388         #define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
 389         #define CONFIG_ENV_SIZE         0x2000
 390 #endif
 391
 392 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 393 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 394
 395 /*
 396  * BOOTP options
 397  */
 398 #define CONFIG_BOOTP_BOOTFILESIZE
 399 #define CONFIG_BOOTP_BOOTPATH
 400 #define CONFIG_BOOTP_GATEWAY
 401 #define CONFIG_BOOTP_HOSTNAME
 402
 403 /*
 404  * Command line configuration.
 405  */
 406 #include <config_cmd_default.h>
 407
 408 #define CONFIG_CMD_PING
 409 #define CONFIG_CMD_I2C
 410 #define CONFIG_CMD_MII
 411 #define CONFIG_CMD_DATE
 412 #define CONFIG_CMD_PCI
 413
 414 #if defined(CFG_RAMBOOT)
 415     #undef CONFIG_CMD_ENV
 416     #undef CONFIG_CMD_LOADS
 417 #endif
 418
 419 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 420
 421 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 422
 423 /*
 424  * Miscellaneous configurable options
 425  */
 426 #define CFG_LONGHELP            /* undef to save memory */
 427 #define CFG_LOAD_ADDR           0x2000000 /* default load address */
 428 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
 429
 430 #if defined(CONFIG_CMD_KGDB)
 431         #define CFG_CBSIZE      1024 /* Console I/O Buffer Size */
 432 #else
 433         #define CFG_CBSIZE      256 /* Console I/O Buffer Size */
 434 #endif
 435
 436 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 437 #define CFG_MAXARGS     16              /* max number of command args */
 438 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 439 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 440
 441 /*
 442  * For booting Linux, the board info and command line data
 443  * have to be in the first 8 MB of memory, since this is
 444  * the maximum mapped by the Linux kernel during initialization.
 445  */
 446 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 447
 448 /*
 449  * Core HID Setup
 450  */
 451 #define CFG_HID0_INIT           0x000000000
 452 #define CFG_HID0_FINAL          (HID0_ENABLE_MACHINE_CHECK | \
 453                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 454 #define CFG_HID2                HID2_HBE
 455
 456 /*
 457  * MMU Setup
 458  */
 459 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 460
 461 /* DDR: cache cacheable */
 462 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 463 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 464 #define CFG_DBAT0L      CFG_IBAT0L
 465 #define CFG_DBAT0U      CFG_IBAT0U
 466
 467 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 468 #define CFG_IBAT1L      (CFG_IMMR | BATL_PP_10 | \
 469                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 470 #define CFG_IBAT1U      (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
 471 #define CFG_DBAT1L      CFG_IBAT1L
 472 #define CFG_DBAT1U      CFG_IBAT1U
 473
 474 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 475 #define CFG_IBAT2L      (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 476 #define CFG_IBAT2U      (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
 477 #define CFG_DBAT2L      (CFG_FLASH_BASE | BATL_PP_10 | \
 478                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 479 #define CFG_DBAT2U      CFG_IBAT2U
 480
 481 /* Stack in dcache: cacheable, no memory coherence */
 482 #define CFG_IBAT3L      (CFG_INIT_RAM_ADDR | BATL_PP_10)
 483 #define CFG_IBAT3U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 484 #define CFG_DBAT3L      CFG_IBAT3L
 485 #define CFG_DBAT3U      CFG_IBAT3U
 486
 487 /* PCI MEM space: cacheable */
 488 #define CFG_IBAT4L      (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 489 #define CFG_IBAT4U      (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 490 #define CFG_DBAT4L      CFG_IBAT4L
 491 #define CFG_DBAT4U      CFG_IBAT4U
 492
 493 /* PCI MMIO space: cache-inhibit and guarded */
 494 #define CFG_IBAT5L      (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
 495                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 496 #define CFG_IBAT5U      (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 497 #define CFG_DBAT5L      CFG_IBAT5L
 498 #define CFG_DBAT5U      CFG_IBAT5U
 499
 500 #define CFG_IBAT6L      0
 501 #define CFG_IBAT6U      0
 502 #define CFG_DBAT6L      CFG_IBAT6L
 503 #define CFG_DBAT6U      CFG_IBAT6U
 504
 505 #define CFG_IBAT7L      0
 506 #define CFG_IBAT7U      0
 507 #define CFG_DBAT7L      CFG_IBAT7L
 508 #define CFG_DBAT7U      CFG_IBAT7U
 509
 510 /*
 511  * Internal Definitions
 512  *
 513  * Boot Flags
 514  */
 515 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 516 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 517
 518 #if defined(CONFIG_CMD_KGDB)
 519 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 520 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 521 #endif
 522
 523 /*
 524  * Environment Configuration
 525  */
 526
 527 #define CONFIG_ENV_OVERWRITE
 528
 529 #if defined(CONFIG_TSEC_ENET)
 530 #define CONFIG_HAS_ETH0
 531 #define CONFIG_ETHADDR          04:00:00:00:00:0A
 532 #define CONFIG_HAS_ETH1
 533 #define CONFIG_ETH1ADDR         04:00:00:00:00:0B
 534 #endif
 535
 536 #define CONFIG_BAUDRATE 115200
 537
 538 #define CONFIG_LOADADDR 500000  /* default location for tftp and bootm */
 539
 540 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 541 #undef CONFIG_BOOTARGS          /* the boot command will set bootargs */
 542
 543 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 544    "netdev=eth0\0"                                                      \
 545    "consoledev=ttyS0\0"                                                 \
 546    "ramdiskaddr=1000000\0"                                              \
 547    "ramdiskfile=ramfs.83xx\0"                                           \
 548    "fdtaddr=400000\0"                                                   \
 549    "fdtfile=mpc8315erdb.dtb\0"                                          \
 550    ""
 551
 552 #define CONFIG_NFSBOOTCOMMAND                                           \
 553    "setenv bootargs root=/dev/nfs rw "                                  \
 554       "nfsroot=$serverip:$rootpath "                                    \
 555       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 556       "console=$consoledev,$baudrate $othbootargs;"                     \
 557    "tftp $loadaddr $bootfile;"                                          \
 558    "tftp $fdtaddr $fdtfile;"                                            \
 559    "bootm $loadaddr - $fdtaddr"
 560
 561 #define CONFIG_RAMBOOTCOMMAND                                           \
 562    "setenv bootargs root=/dev/ram rw "                                  \
 563       "console=$consoledev,$baudrate $othbootargs;"                     \
 564    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 565    "tftp $loadaddr $bootfile;"                                          \
 566    "tftp $fdtaddr $fdtfile;"                                            \
 567    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 568
 569
 570 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 571
 572 #endif  /* __CONFIG_H */