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treewide: mem: Move mtest related defines to Kconfig
[thirdparty/u-boot.git] / include / configs / MPC832XEMDS.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 */
5
6 #ifndef __CONFIG_H
7 #define __CONFIG_H
8
9 /*
10 * High Level Configuration Options
11 */
12 #define CONFIG_E300 1 /* E300 family */
13
14 /*
15 * System IO Config
16 */
17 #define CONFIG_SYS_SICRL 0x00000000
18
19 /*
20 * DDR Setup
21 */
22 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
23 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
24
25 #undef CONFIG_SPD_EEPROM
26 #if defined(CONFIG_SPD_EEPROM)
27 /* Determine DDR configuration from I2C interface
28 */
29 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
30 #else
31 /* Manually set up DDR parameters
32 */
33 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
34 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
35 | CSCONFIG_AP \
36 | CSCONFIG_ODT_WR_CFG \
37 | CSCONFIG_ROW_BIT_13 \
38 | CSCONFIG_COL_BIT_10)
39 /* 0x80840102 */
40 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
41 | (0 << TIMING_CFG0_WRT_SHIFT) \
42 | (0 << TIMING_CFG0_RRT_SHIFT) \
43 | (0 << TIMING_CFG0_WWT_SHIFT) \
44 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
45 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
46 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
47 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
48 /* 0x00220802 */
49 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
50 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
51 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
52 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
53 | (13 << TIMING_CFG1_REFREC_SHIFT) \
54 | (3 << TIMING_CFG1_WRREC_SHIFT) \
55 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
56 | (2 << TIMING_CFG1_WRTORD_SHIFT))
57 /* 0x3935D322 */
58 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
59 | (31 << TIMING_CFG2_CPO_SHIFT) \
60 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
61 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
62 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
63 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
64 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
65 /* 0x0F9048CA */
66 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
67 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
68 /* 0x02000000 */
69 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
70 | (0x0232 << SDRAM_MODE_SD_SHIFT))
71 /* 0x44400232 */
72 #define CONFIG_SYS_DDR_MODE2 0x8000c000
73 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
74 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
75 /* 0x03200064 */
76 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
77 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
78 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
79 | SDRAM_CFG_32_BE)
80 /* 0x43080000 */
81 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
82 #endif
83
84 /*
85 * Memory test
86 */
87 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
88
89 /*
90 * The reserved memory
91 */
92 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
93
94 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
95 #define CONFIG_SYS_RAMBOOT
96 #else
97 #undef CONFIG_SYS_RAMBOOT
98 #endif
99
100 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
101 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
102 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
103
104 /*
105 * Initial RAM Base Address Setup
106 */
107 #define CONFIG_SYS_INIT_RAM_LOCK 1
108 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
109 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
110 #define CONFIG_SYS_GBL_DATA_OFFSET \
111 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
112
113 /*
114 * FLASH on the Local Bus
115 */
116 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
117 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
118
119
120 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
121 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
122
123 #undef CONFIG_SYS_FLASH_CHECKSUM
124
125 /*
126 * BCSR on the Local Bus
127 */
128 #define CONFIG_SYS_BCSR 0xF8000000
129 /* Access window base at BCSR base */
130
131
132 /*
133 * Windows to access PIB via local bus
134 */
135 /* PIB window base 0xF8008000 */
136 #define CONFIG_SYS_PIB_BASE 0xF8008000
137 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
138
139 /*
140 * CS2 on Local Bus, to PIB
141 */
142
143
144 /*
145 * CS3 on Local Bus, to PIB
146 */
147
148
149 /*
150 * Serial Port
151 */
152 #define CONFIG_SYS_NS16550_SERIAL
153 #define CONFIG_SYS_NS16550_REG_SIZE 1
154 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
155
156 #define CONFIG_SYS_BAUDRATE_TABLE \
157 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
158
159 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
160 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
161
162 /* I2C */
163 #define CONFIG_SYS_I2C
164 #define CONFIG_SYS_I2C_FSL
165 #define CONFIG_SYS_FSL_I2C_SPEED 400000
166 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
167 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
168 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
169
170 /*
171 * Config on-board RTC
172 */
173 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
174 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
175
176 /*
177 * General PCI
178 * Addresses are mapped 1-1.
179 */
180 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
181 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
182 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
183 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
184 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
185 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
186 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
187 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
188 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
189
190 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
191 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
192 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
193
194 #ifdef CONFIG_PCI
195 #define CONFIG_PCI_INDIRECT_BRIDGE
196
197 #define CONFIG_83XX_PCI_STREAMING
198
199 #undef CONFIG_EEPRO100
200 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
201 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
202
203 #endif /* CONFIG_PCI */
204
205 /*
206 * QE UEC ethernet configuration
207 */
208 #define CONFIG_UEC_ETH
209 #define CONFIG_ETHPRIME "UEC0"
210
211 #define CONFIG_UEC_ETH1 /* ETH3 */
212
213 #ifdef CONFIG_UEC_ETH1
214 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
215 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
216 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
217 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
218 #define CONFIG_SYS_UEC1_PHY_ADDR 3
219 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
220 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
221 #endif
222
223 #define CONFIG_UEC_ETH2 /* ETH4 */
224
225 #ifdef CONFIG_UEC_ETH2
226 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
227 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
228 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
229 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
230 #define CONFIG_SYS_UEC2_PHY_ADDR 4
231 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
232 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
233 #endif
234
235 /*
236 * Environment
237 */
238
239 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
240 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
241
242 /*
243 * BOOTP options
244 */
245 #define CONFIG_BOOTP_BOOTFILESIZE
246
247 /*
248 * Command line configuration.
249 */
250
251 #undef CONFIG_WATCHDOG /* watchdog disabled */
252
253 /*
254 * Miscellaneous configurable options
255 */
256 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
257
258 /*
259 * For booting Linux, the board info and command line data
260 * have to be in the first 256 MB of memory, since this is
261 * the maximum mapped by the Linux kernel during initialization.
262 */
263 /* Initial Memory map for Linux */
264 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
265 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
266
267 #if defined(CONFIG_CMD_KGDB)
268 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
269 #endif
270
271 /*
272 * Environment Configuration
273 */ #define CONFIG_ENV_OVERWRITE
274
275 #if defined(CONFIG_UEC_ETH)
276 #define CONFIG_HAS_ETH0
277 #define CONFIG_HAS_ETH1
278 #endif
279
280 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
281
282 #define CONFIG_EXTRA_ENV_SETTINGS \
283 "netdev=eth0\0" \
284 "consoledev=ttyS0\0" \
285 "ramdiskaddr=1000000\0" \
286 "ramdiskfile=ramfs.83xx\0" \
287 "fdtaddr=780000\0" \
288 "fdtfile=mpc832x_mds.dtb\0" \
289 ""
290
291 #define CONFIG_NFSBOOTCOMMAND \
292 "setenv bootargs root=/dev/nfs rw " \
293 "nfsroot=$serverip:$rootpath " \
294 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
295 "$netdev:off " \
296 "console=$consoledev,$baudrate $othbootargs;" \
297 "tftp $loadaddr $bootfile;" \
298 "tftp $fdtaddr $fdtfile;" \
299 "bootm $loadaddr - $fdtaddr"
300
301 #define CONFIG_RAMBOOTCOMMAND \
302 "setenv bootargs root=/dev/ram rw " \
303 "console=$consoledev,$baudrate $othbootargs;" \
304 "tftp $ramdiskaddr $ramdiskfile;" \
305 "tftp $loadaddr $bootfile;" \
306 "tftp $fdtaddr $fdtfile;" \
307 "bootm $loadaddr $ramdiskaddr $fdtaddr"
308
309 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
310
311 #endif /* __CONFIG_H */