include/configs/MPC8349EMDS.h

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * mpc8349emds board configuration file
  26  *
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 #undef DEBUG
  33
  34 /*
  35  * High Level Configuration Options
  36  */
  37 #define CONFIG_E300             1       /* E300 Family */
  38 #define CONFIG_MPC83XX          1       /* MPC83XX family */
  39 #define CONFIG_MPC834X          1       /* MPC834X family */
  40 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  41 #define CONFIG_MPC8349EMDS      1       /* MPC8349EMDS board specific */
  42
  43 #undef CONFIG_PCI
  44 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  45
  46 #define PCI_66M
  47 #ifdef PCI_66M
  48 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  49 #else
  50 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  51 #endif
  52
  53 #ifndef CONFIG_SYS_CLK_FREQ
  54 #ifdef PCI_66M
  55 #define CONFIG_SYS_CLK_FREQ     66000000
  56 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  57 #else
  58 #define CONFIG_SYS_CLK_FREQ     33000000
  59 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  60 #endif
  61 #endif
  62
  63 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
  64
  65 #define CFG_IMMR                0xE0000000
  66
  67 #undef CFG_DRAM_TEST                            /* memory test, takes time */
  68 #define CFG_MEMTEST_START       0x00000000      /* memtest region */
  69 #define CFG_MEMTEST_END         0x00100000
  70
  71 /*
  72  * DDR Setup
  73  */
  74 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  75 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  76 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  77
  78 /*
  79  * 32-bit data path mode.
  80  *
  81  * Please note that using this mode for devices with the real density of 64-bit
  82  * effectively reduces the amount of available memory due to the effect of
  83  * wrapping around while translating address to row/columns, for example in the
  84  * 256MB module the upper 128MB get aliased with contents of the lower
  85  * 128MB); normally this define should be used for devices with real 32-bit
  86  * data path.
  87  */
  88 #undef CONFIG_DDR_32BIT
  89
  90 #define CFG_DDR_BASE            0x00000000      /* DDR is system memory*/
  91 #define CFG_SDRAM_BASE          CFG_DDR_BASE
  92 #define CFG_DDR_SDRAM_BASE      CFG_DDR_BASE
  93 #define CFG_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
  94                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  95 #undef  CONFIG_DDR_2T_TIMING
  96
  97 /*
  98  * DDRCDR - DDR Control Driver Register
  99  */
 100 #define CFG_DDRCDR_VALUE        0x80080001
 101
 102 #if defined(CONFIG_SPD_EEPROM)
 103 /*
 104  * Determine DDR configuration from I2C interface.
 105  */
 106 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 107 #else
 108 /*
 109  * Manually set up DDR parameters
 110  */
 111 #define CFG_DDR_SIZE            256             /* MB */
 112 #if defined(CONFIG_DDR_II)
 113 #define CFG_DDRCDR              0x80080001
 114 #define CFG_DDR_CS2_BNDS        0x0000000f
 115 #define CFG_DDR_CS2_CONFIG      0x80330102
 116 #define CFG_DDR_TIMING_0        0x00220802
 117 #define CFG_DDR_TIMING_1        0x38357322
 118 #define CFG_DDR_TIMING_2        0x2f9048c8
 119 #define CFG_DDR_TIMING_3        0x00000000
 120 #define CFG_DDR_CLK_CNTL        0x02000000
 121 #define CFG_DDR_MODE            0x47d00432
 122 #define CFG_DDR_MODE2           0x8000c000
 123 #define CFG_DDR_INTERVAL        0x03cf0080
 124 #define CFG_DDR_SDRAM_CFG       0x43000000
 125 #define CFG_DDR_SDRAM_CFG2      0x00401000
 126 #else
 127 #define CFG_DDR_CONFIG          (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 128 #define CFG_DDR_TIMING_1        0x36332321
 129 #define CFG_DDR_TIMING_2        0x00000800      /* P9-45,may need tuning */
 130 #define CFG_DDR_CONTROL         0xc2000000      /* unbuffered,no DYN_PWR */
 131 #define CFG_DDR_INTERVAL        0x04060100      /* autocharge,no open page */
 132
 133 #if defined(CONFIG_DDR_32BIT)
 134 /* set burst length to 8 for 32-bit data path */
 135 #define CFG_DDR_MODE            0x00000023      /* DLL,normal,seq,4/2.5, 8 burst len */
 136 #else
 137 /* the default burst length is 4 - for 64-bit data path */
 138 #define CFG_DDR_MODE            0x00000022      /* DLL,normal,seq,4/2.5, 4 burst len */
 139 #endif
 140 #endif
 141 #endif
 142
 143 /*
 144  * SDRAM on the Local Bus
 145  */
 146 #define CFG_LBC_SDRAM_BASE      0xF0000000      /* Localbus SDRAM */
 147 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
 148
 149 /*
 150  * FLASH on the Local Bus
 151  */
 152 #define CFG_FLASH_CFI                           /* use the Common Flash Interface */
 153 #define CFG_FLASH_CFI_DRIVER                    /* use the CFI driver */
 154 #define CFG_FLASH_BASE          0xFE000000      /* start of FLASH   */
 155 #define CFG_FLASH_SIZE          32              /* max flash size in MB */
 156 /* #define CFG_FLASH_USE_BUFFER_WRITE */
 157
 158 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE |       /* flash Base address */ \
 159                                 (2 << BR_PS_SHIFT) |    /* 16 bit port size */   \
 160                                 BR_V)                   /* valid */
 161 #define CFG_OR0_PRELIM          ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 162                                 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 163                                 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 164 #define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE  /* window base at flash base */
 165 #define CFG_LBLAWAR0_PRELIM     0x80000018      /* 32 MB window size */
 166
 167 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 168 #define CFG_MAX_FLASH_SECT      256             /* max sectors per device */
 169
 170 #undef CFG_FLASH_CHECKSUM
 171 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 172 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 173
 174 #define CFG_MID_FLASH_JUMP      0x7F000000
 175 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 176
 177 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 178 #define CFG_RAMBOOT
 179 #else
 180 #undef  CFG_RAMBOOT
 181 #endif
 182
 183 /*
 184  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 185  */
 186 #define CFG_BCSR                0xE2400000
 187 #define CFG_LBLAWBAR1_PRELIM    CFG_BCSR                /* Access window base at BCSR base */
 188 #define CFG_LBLAWAR1_PRELIM     0x8000000E              /* Access window size 32K */
 189 #define CFG_BR1_PRELIM          (CFG_BCSR|0x00000801)   /* Port-size=8bit, MSEL=GPCM */
 190 #define CFG_OR1_PRELIM          0xFFFFE8F0              /* length 32K */
 191
 192 #define CONFIG_L1_INIT_RAM
 193 #define CFG_INIT_RAM_LOCK       1
 194 #define CFG_INIT_RAM_ADDR       0xFD000000              /* Initial RAM address */
 195 #define CFG_INIT_RAM_END        0x1000                  /* End of used area in RAM*/
 196
 197 #define CFG_GBL_DATA_SIZE       0x100                   /* num bytes initial data */
 198 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 199 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 200
 201 #define CFG_MONITOR_LEN         (256 * 1024)            /* Reserve 256 kB for Mon */
 202 #define CFG_MALLOC_LEN          (128 * 1024)            /* Reserved for malloc */
 203
 204 /*
 205  * Local Bus LCRR and LBCR regs
 206  *    LCRR:  DLL bypass, Clock divider is 4
 207  * External Local Bus rate is
 208  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 209  */
 210 #define CFG_LCRR        (LCRR_DBYP | LCRR_CLKDIV_4)
 211 #define CFG_LBC_LBCR    0x00000000
 212
 213 /*
 214  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 215  * if board has SRDAM on local bus, you can define CFG_LB_SDRAM
 216  */
 217 #undef CFG_LB_SDRAM
 218
 219 #ifdef CFG_LB_SDRAM
 220 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 221 /*
 222  * Base Register 2 and Option Register 2 configure SDRAM.
 223  * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 224  *
 225  * For BR2, need:
 226  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 227  *    port-size = 32-bits = BR2[19:20] = 11
 228  *    no parity checking = BR2[21:22] = 00
 229  *    SDRAM for MSEL = BR2[24:26] = 011
 230  *    Valid = BR[31] = 1
 231  *
 232  * 0    4    8    12   16   20   24   28
 233  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 234  *
 235  * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 236  * FIXME: the top 17 bits of BR2.
 237  */
 238
 239 #define CFG_BR2_PRELIM          0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
 240 #define CFG_LBLAWBAR2_PRELIM    0xF0000000
 241 #define CFG_LBLAWAR2_PRELIM     0x80000019 /* 64M */
 242
 243 /*
 244  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 245  *
 246  * For OR2, need:
 247  *    64MB mask for AM, OR2[0:7] = 1111 1100
 248  *                 XAM, OR2[17:18] = 11
 249  *    9 columns OR2[19-21] = 010
 250  *    13 rows   OR2[23-25] = 100
 251  *    EAD set for extra time OR[31] = 1
 252  *
 253  * 0    4    8    12   16   20   24   28
 254  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 255  */
 256
 257 #define CFG_OR2_PRELIM  0xFC006901
 258
 259 #define CFG_LBC_LSRT    0x32000000    /* LB sdram refresh timer, about 6us */
 260 #define CFG_LBC_MRTPR   0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 261
 262 /*
 263  * LSDMR masks
 264  */
 265 #define CFG_LBC_LSDMR_RFEN      (1 << (31 -  1))
 266 #define CFG_LBC_LSDMR_BSMA1516  (3 << (31 - 10))
 267 #define CFG_LBC_LSDMR_BSMA1617  (4 << (31 - 10))
 268 #define CFG_LBC_LSDMR_RFCR5     (3 << (31 - 16))
 269 #define CFG_LBC_LSDMR_RFCR8     (5 << (31 - 16))
 270 #define CFG_LBC_LSDMR_RFCR16    (7 << (31 - 16))
 271 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
 272 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
 273 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
 274 #define CFG_LBC_LSDMR_ACTTORW3  (3 << (31 - 22))
 275 #define CFG_LBC_LSDMR_ACTTORW7  (7 << (31 - 22))
 276 #define CFG_LBC_LSDMR_ACTTORW6  (6 << (31 - 22))
 277 #define CFG_LBC_LSDMR_BL8       (1 << (31 - 23))
 278 #define CFG_LBC_LSDMR_WRC2      (2 << (31 - 27))
 279 #define CFG_LBC_LSDMR_WRC3      (3 << (31 - 27))
 280 #define CFG_LBC_LSDMR_WRC4      (0 << (31 - 27))
 281 #define CFG_LBC_LSDMR_BUFCMD    (1 << (31 - 29))
 282 #define CFG_LBC_LSDMR_CL3       (3 << (31 - 31))
 283
 284 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
 285 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
 286 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
 287 #define CFG_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
 288 #define CFG_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
 289 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
 290 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
 291 #define CFG_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
 292
 293 #define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
 294                                 | CFG_LBC_LSDMR_BSMA1516        \
 295                                 | CFG_LBC_LSDMR_RFCR8           \
 296                                 | CFG_LBC_LSDMR_PRETOACT6       \
 297                                 | CFG_LBC_LSDMR_ACTTORW3        \
 298                                 | CFG_LBC_LSDMR_BL8             \
 299                                 | CFG_LBC_LSDMR_WRC3            \
 300                                 | CFG_LBC_LSDMR_CL3             \
 301                                 )
 302
 303 /*
 304  * SDRAM Controller configuration sequence.
 305  */
 306 #define CFG_LBC_LSDMR_1         ( CFG_LBC_LSDMR_COMMON \
 307                                 | CFG_LBC_LSDMR_OP_PCHALL)
 308 #define CFG_LBC_LSDMR_2         ( CFG_LBC_LSDMR_COMMON \
 309                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 310 #define CFG_LBC_LSDMR_3         ( CFG_LBC_LSDMR_COMMON \
 311                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 312 #define CFG_LBC_LSDMR_4         ( CFG_LBC_LSDMR_COMMON \
 313                                 | CFG_LBC_LSDMR_OP_MRW)
 314 #define CFG_LBC_LSDMR_5         ( CFG_LBC_LSDMR_COMMON \
 315                                 | CFG_LBC_LSDMR_OP_NORMAL)
 316 #endif
 317
 318 /*
 319  * Serial Port
 320  */
 321 #define CONFIG_CONS_INDEX     1
 322 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 323 #define CFG_NS16550
 324 #define CFG_NS16550_SERIAL
 325 #define CFG_NS16550_REG_SIZE    1
 326 #define CFG_NS16550_CLK         get_bus_freq(0)
 327
 328 #define CFG_BAUDRATE_TABLE  \
 329         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 330
 331 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
 332 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 333
 334 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 335 /* Use the HUSH parser */
 336 #define CFG_HUSH_PARSER
 337 #ifdef  CFG_HUSH_PARSER
 338 #define CFG_PROMPT_HUSH_PS2 "> "
 339 #endif
 340
 341 /* pass open firmware flat tree */
 342 #define CONFIG_OF_FLAT_TREE     1
 343 #define CONFIG_OF_BOARD_SETUP   1
 344
 345 /* maximum size of the flat tree (8K) */
 346 #define OF_FLAT_TREE_MAX_SIZE   8192
 347
 348 #define OF_CPU                  "PowerPC,8349@0"
 349 #define OF_SOC                  "soc8349@e0000000"
 350 #define OF_TBCLK                (bd->bi_busfreq / 4)
 351 #define OF_STDOUT_PATH          "/soc8349@e0000000/serial@4500"
 352
 353 /* I2C */
 354 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 355 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
 356 #define CONFIG_FSL_I2C
 357 #define CONFIG_I2C_MULTI_BUS
 358 #define CONFIG_I2C_CMD_TREE
 359 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 360 #define CFG_I2C_SLAVE           0x7F
 361 #define CFG_I2C_NOPROBES        {{0,0x69}}      /* Don't probe these addrs */
 362 #define CFG_I2C_OFFSET          0x3000
 363 #define CFG_I2C2_OFFSET         0x3100
 364
 365 /* TSEC */
 366 #define CFG_TSEC1_OFFSET 0x24000
 367 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
 368 #define CFG_TSEC2_OFFSET 0x25000
 369 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
 370
 371 /* USB */
 372 #define CFG_USE_MPC834XSYS_USB_PHY      1 /* Use SYS board PHY */
 373
 374 /*
 375  * General PCI
 376  * Addresses are mapped 1-1.
 377  */
 378 #define CFG_PCI1_MEM_BASE       0x80000000
 379 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 380 #define CFG_PCI1_MEM_SIZE       0x10000000      /* 256M */
 381 #define CFG_PCI1_MMIO_BASE      0x90000000
 382 #define CFG_PCI1_MMIO_PHYS      CFG_PCI1_MMIO_BASE
 383 #define CFG_PCI1_MMIO_SIZE      0x10000000      /* 256M */
 384 #define CFG_PCI1_IO_BASE        0x00000000
 385 #define CFG_PCI1_IO_PHYS        0xE2000000
 386 #define CFG_PCI1_IO_SIZE        0x00100000      /* 1M */
 387
 388 #define CFG_PCI2_MEM_BASE       0xA0000000
 389 #define CFG_PCI2_MEM_PHYS       CFG_PCI2_MEM_BASE
 390 #define CFG_PCI2_MEM_SIZE       0x10000000      /* 256M */
 391 #define CFG_PCI2_MMIO_BASE      0xB0000000
 392 #define CFG_PCI2_MMIO_PHYS      CFG_PCI2_MMIO_BASE
 393 #define CFG_PCI2_MMIO_SIZE      0x10000000      /* 256M */
 394 #define CFG_PCI2_IO_BASE        0x00000000
 395 #define CFG_PCI2_IO_PHYS        0xE2100000
 396 #define CFG_PCI2_IO_SIZE        0x00100000      /* 1M */
 397
 398 #if defined(CONFIG_PCI)
 399
 400 #define PCI_ONE_PCI1
 401 #if defined(PCI_64BIT)
 402 #undef PCI_ALL_PCI1
 403 #undef PCI_TWO_PCI1
 404 #undef PCI_ONE_PCI1
 405 #endif
 406
 407 #define CONFIG_NET_MULTI
 408 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 409
 410 #undef CONFIG_EEPRO100
 411 #undef CONFIG_TULIP
 412
 413 #if !defined(CONFIG_PCI_PNP)
 414         #define PCI_ENET0_IOADDR        0xFIXME
 415         #define PCI_ENET0_MEMADDR       0xFIXME
 416         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 417 #endif
 418
 419 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 420 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 421
 422 #endif  /* CONFIG_PCI */
 423
 424 /*
 425  * TSEC configuration
 426  */
 427 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 428
 429 #if defined(CONFIG_TSEC_ENET)
 430 #ifndef CONFIG_NET_MULTI
 431 #define CONFIG_NET_MULTI        1
 432 #endif
 433
 434 #define CONFIG_GMII             1       /* MII PHY management */
 435 #define CONFIG_MPC83XX_TSEC1    1
 436 #define CONFIG_MPC83XX_TSEC1_NAME       "TSEC0"
 437 #define CONFIG_MPC83XX_TSEC2    1
 438 #define CONFIG_MPC83XX_TSEC2_NAME       "TSEC1"
 439 #define TSEC1_PHY_ADDR          0
 440 #define TSEC2_PHY_ADDR          1
 441 #define TSEC1_PHYIDX            0
 442 #define TSEC2_PHYIDX            0
 443
 444 /* Options are: TSEC[0-1] */
 445 #define CONFIG_ETHPRIME         "TSEC0"
 446
 447 #endif  /* CONFIG_TSEC_ENET */
 448
 449 /*
 450  * Configure on-board RTC
 451  */
 452 #define CONFIG_RTC_DS1374                       /* use ds1374 rtc via i2c       */
 453 #define CFG_I2C_RTC_ADDR                0x68    /* at address 0x68              */
 454
 455 /*
 456  * Environment
 457  */
 458 #ifndef CFG_RAMBOOT
 459         #define CFG_ENV_IS_IN_FLASH     1
 460         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 461         #define CFG_ENV_SECT_SIZE       0x20000 /* 128K(one sector) for env */
 462         #define CFG_ENV_SIZE            0x2000
 463
 464 /* Address and size of Redundant Environment Sector     */
 465 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 466 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 467
 468 #else
 469         #define CFG_NO_FLASH            1       /* Flash is not usable now */
 470         #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only */
 471         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
 472         #define CFG_ENV_SIZE            0x2000
 473 #endif
 474
 475 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 476 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 477
 478 #if defined(CFG_RAMBOOT)
 479 #if defined(CONFIG_PCI)
 480 #define  CONFIG_COMMANDS        ((CONFIG_CMD_DFL        \
 481                                  | CFG_CMD_PING         \
 482                                  | CFG_CMD_PCI          \
 483                                  | CFG_CMD_I2C          \
 484                                  | CFG_CMD_DATE)        \
 485                                 &                       \
 486                                  ~(CFG_CMD_ENV          \
 487                                   | CFG_CMD_LOADS))
 488 #else
 489 #define  CONFIG_COMMANDS        ((CONFIG_CMD_DFL        \
 490                                  | CFG_CMD_PING         \
 491                                  | CFG_CMD_I2C          \
 492                                  | CFG_CMD_DATE)        \
 493                                 &                       \
 494                                  ~(CFG_CMD_ENV          \
 495                                   | CFG_CMD_LOADS))
 496 #endif
 497 #else
 498 #if defined(CONFIG_PCI)
 499 #define  CONFIG_COMMANDS        (CONFIG_CMD_DFL         \
 500                                 | CFG_CMD_PCI           \
 501                                 | CFG_CMD_PING          \
 502                                 | CFG_CMD_I2C           \
 503                                 | CFG_CMD_DATE          \
 504                                 )
 505 #else
 506 #define  CONFIG_COMMANDS        (CONFIG_CMD_DFL         \
 507                                 | CFG_CMD_PING          \
 508                                 | CFG_CMD_I2C           \
 509                                 | CFG_CMD_MII           \
 510                                 | CFG_CMD_DATE          \
 511                                 )
 512 #endif
 513 #endif
 514
 515 #include <cmd_confdefs.h>
 516
 517 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 518
 519 /*
 520  * Miscellaneous configurable options
 521  */
 522 #define CFG_LONGHELP                    /* undef to save memory */
 523 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 524 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 525
 526 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 527         #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 528 #else
 529         #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 530 #endif
 531
 532 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 533 #define CFG_MAXARGS     16              /* max number of command args */
 534 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 535 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 536
 537 /*
 538  * For booting Linux, the board info and command line data
 539  * have to be in the first 8 MB of memory, since this is
 540  * the maximum mapped by the Linux kernel during initialization.
 541  */
 542 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 543
 544 /* Cache Configuration */
 545 #define CFG_DCACHE_SIZE         32768
 546 #define CFG_CACHELINE_SIZE      32
 547 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 548 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value*/
 549 #endif
 550
 551 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 552
 553 #if 1 /*528/264*/
 554 #define CFG_HRCW_LOW (\
 555         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 556         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 557         HRCWL_CSB_TO_CLKIN |\
 558         HRCWL_VCO_1X2 |\
 559         HRCWL_CORE_TO_CSB_2X1)
 560 #elif 0 /*396/132*/
 561 #define CFG_HRCW_LOW (\
 562         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 563         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 564         HRCWL_CSB_TO_CLKIN |\
 565         HRCWL_VCO_1X4 |\
 566         HRCWL_CORE_TO_CSB_3X1)
 567 #elif 0 /*264/132*/
 568 #define CFG_HRCW_LOW (\
 569         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 570         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 571         HRCWL_CSB_TO_CLKIN |\
 572         HRCWL_VCO_1X4 |\
 573         HRCWL_CORE_TO_CSB_2X1)
 574 #elif 0 /*132/132*/
 575 #define CFG_HRCW_LOW (\
 576         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 577         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 578         HRCWL_CSB_TO_CLKIN |\
 579         HRCWL_VCO_1X4 |\
 580         HRCWL_CORE_TO_CSB_1X1)
 581 #elif 0 /*264/264 */
 582 #define CFG_HRCW_LOW (\
 583         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 584         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 585         HRCWL_CSB_TO_CLKIN |\
 586         HRCWL_VCO_1X4 |\
 587         HRCWL_CORE_TO_CSB_1X1)
 588 #endif
 589
 590 #if defined(PCI_64BIT)
 591 #define CFG_HRCW_HIGH (\
 592         HRCWH_PCI_HOST |\
 593         HRCWH_64_BIT_PCI |\
 594         HRCWH_PCI1_ARBITER_ENABLE |\
 595         HRCWH_PCI2_ARBITER_DISABLE |\
 596         HRCWH_CORE_ENABLE |\
 597         HRCWH_FROM_0X00000100 |\
 598         HRCWH_BOOTSEQ_DISABLE |\
 599         HRCWH_SW_WATCHDOG_DISABLE |\
 600         HRCWH_ROM_LOC_LOCAL_16BIT |\
 601         HRCWH_TSEC1M_IN_GMII |\
 602         HRCWH_TSEC2M_IN_GMII )
 603 #else
 604 #define CFG_HRCW_HIGH (\
 605         HRCWH_PCI_HOST |\
 606         HRCWH_32_BIT_PCI |\
 607         HRCWH_PCI1_ARBITER_ENABLE |\
 608         HRCWH_PCI2_ARBITER_ENABLE |\
 609         HRCWH_CORE_ENABLE |\
 610         HRCWH_FROM_0X00000100 |\
 611         HRCWH_BOOTSEQ_DISABLE |\
 612         HRCWH_SW_WATCHDOG_DISABLE |\
 613         HRCWH_ROM_LOC_LOCAL_16BIT |\
 614         HRCWH_TSEC1M_IN_GMII |\
 615         HRCWH_TSEC2M_IN_GMII )
 616 #endif
 617
 618 /* System IO Config */
 619 #define CFG_SICRH SICRH_TSOBI1
 620 #define CFG_SICRL SICRL_LDP_A
 621
 622 #define CFG_HID0_INIT   0x000000000
 623 #define CFG_HID0_FINAL  HID0_ENABLE_MACHINE_CHECK
 624
 625 /* #define CFG_HID0_FINAL               (\
 626         HID0_ENABLE_INSTRUCTION_CACHE |\
 627         HID0_ENABLE_M_BIT |\
 628         HID0_ENABLE_ADDRESS_BROADCAST ) */
 629
 630
 631 #define CFG_HID2 HID2_HBE
 632
 633 /* DDR @ 0x00000000 */
 634 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 635 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 636
 637 /* PCI @ 0x80000000 */
 638 #ifdef CONFIG_PCI
 639 #define CFG_IBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 640 #define CFG_IBAT1U      (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 641 #define CFG_IBAT2L      (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 642 #define CFG_IBAT2U      (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 643 #else
 644 #define CFG_IBAT1L      (0)
 645 #define CFG_IBAT1U      (0)
 646 #define CFG_IBAT2L      (0)
 647 #define CFG_IBAT2U      (0)
 648 #endif
 649
 650 #ifdef CONFIG_MPC83XX_PCI2
 651 #define CFG_IBAT3L      (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 652 #define CFG_IBAT3U      (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 653 #define CFG_IBAT4L      (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 654 #define CFG_IBAT4U      (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 655 #else
 656 #define CFG_IBAT3L      (0)
 657 #define CFG_IBAT3U      (0)
 658 #define CFG_IBAT4L      (0)
 659 #define CFG_IBAT4U      (0)
 660 #endif
 661
 662 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 663 #define CFG_IBAT5L      (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 664 #define CFG_IBAT5U      (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 665
 666 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 667 #define CFG_IBAT6L      (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
 668 #define CFG_IBAT6U      (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 669
 670 #define CFG_IBAT7L      (0)
 671 #define CFG_IBAT7U      (0)
 672
 673 #define CFG_DBAT0L      CFG_IBAT0L
 674 #define CFG_DBAT0U      CFG_IBAT0U
 675 #define CFG_DBAT1L      CFG_IBAT1L
 676 #define CFG_DBAT1U      CFG_IBAT1U
 677 #define CFG_DBAT2L      CFG_IBAT2L
 678 #define CFG_DBAT2U      CFG_IBAT2U
 679 #define CFG_DBAT3L      CFG_IBAT3L
 680 #define CFG_DBAT3U      CFG_IBAT3U
 681 #define CFG_DBAT4L      CFG_IBAT4L
 682 #define CFG_DBAT4U      CFG_IBAT4U
 683 #define CFG_DBAT5L      CFG_IBAT5L
 684 #define CFG_DBAT5U      CFG_IBAT5U
 685 #define CFG_DBAT6L      CFG_IBAT6L
 686 #define CFG_DBAT6U      CFG_IBAT6U
 687 #define CFG_DBAT7L      CFG_IBAT7L
 688 #define CFG_DBAT7U      CFG_IBAT7U
 689
 690 /*
 691  * Internal Definitions
 692  *
 693  * Boot Flags
 694  */
 695 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 696 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 697
 698 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 699 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 700 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 701 #endif
 702
 703 /*
 704  * Environment Configuration
 705  */
 706 #define CONFIG_ENV_OVERWRITE
 707
 708 #if defined(CONFIG_TSEC_ENET)
 709 #define CONFIG_ETHADDR          00:04:9f:ef:23:33
 710 #define CONFIG_HAS_ETH1
 711 #define CONFIG_ETH1ADDR         00:E0:0C:00:7E:21
 712 #endif
 713
 714 #define CONFIG_IPADDR           192.168.1.253
 715
 716 #define CONFIG_HOSTNAME         mpc8349emds
 717 #define CONFIG_ROOTPATH         /nfsroot/rootfs
 718 #define CONFIG_BOOTFILE         uImage
 719
 720 #define CONFIG_SERVERIP         192.168.1.1
 721 #define CONFIG_GATEWAYIP        192.168.1.1
 722 #define CONFIG_NETMASK          255.255.255.0
 723
 724 #define CONFIG_LOADADDR         200000  /* default location for tftp and bootm */
 725
 726 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 727 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 728
 729 #define CONFIG_BAUDRATE  115200
 730
 731 #define CONFIG_PREBOOT  "echo;" \
 732         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 733         "echo"
 734
 735 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 736         "netdev=eth0\0"                                                 \
 737         "hostname=mpc8349emds\0"                                        \
 738         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 739                 "nfsroot=${serverip}:${rootpath}\0"                     \
 740         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 741         "addip=setenv bootargs ${bootargs} "                            \
 742                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 743                 ":${hostname}:${netdev}:off panic=1\0"                  \
 744         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 745         "flash_nfs=run nfsargs addip addtty;"                           \
 746                 "bootm ${kernel_addr}\0"                                \
 747         "flash_self=run ramargs addip addtty;"                          \
 748                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 749         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 750                 "bootm\0"                                               \
 751         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 752         "update=protect off fe000000 fe03ffff; "                        \
 753                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"     \
 754         "upd=run load;run update\0"                                     \
 755         "fdtaddr=400000\0"                                              \
 756         "fdtfile=mpc8349emds.dtb\0"                                     \
 757         ""
 758
 759 #define CONFIG_NFSBOOTCOMMAND                                           \
 760    "setenv bootargs root=/dev/nfs rw "                                  \
 761       "nfsroot=$serverip:$rootpath "                                    \
 762       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 763       "console=$consoledev,$baudrate $othbootargs;"                     \
 764    "tftp $loadaddr $bootfile;"                                          \
 765    "tftp $fdtaddr $fdtfile;"                                            \
 766    "bootm $loadaddr - $fdtaddr"
 767
 768 #define CONFIG_RAMBOOTCOMMAND                                           \
 769    "setenv bootargs root=/dev/ram rw "                                  \
 770       "console=$consoledev,$baudrate $othbootargs;"                     \
 771    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 772    "tftp $loadaddr $bootfile;"                                          \
 773    "tftp $fdtaddr $fdtfile;"                                            \
 774    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 775
 776 #define CONFIG_BOOTCOMMAND      "run flash_self"
 777
 778 #endif  /* __CONFIG_H */