include/configs/MPC8349EMDS.h

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * mpc8349emds board configuration file
  26  *
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 #undef DEBUG
  33
  34 /*
  35  * High Level Configuration Options
  36  */
  37 #define CONFIG_E300             1       /* E300 Family */
  38 #define CONFIG_MPC83XX          1       /* MPC83XX family */
  39 #define CONFIG_MPC834X          1       /* MPC834X family */
  40 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  41 #define CONFIG_MPC8349EMDS      1       /* MPC8349EMDS board specific */
  42
  43 #undef CONFIG_PCI
  44 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  45
  46 #define PCI_66M
  47 #ifdef PCI_66M
  48 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  49 #else
  50 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  51 #endif
  52
  53 #ifndef CONFIG_SYS_CLK_FREQ
  54 #ifdef PCI_66M
  55 #define CONFIG_SYS_CLK_FREQ     66000000
  56 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  57 #else
  58 #define CONFIG_SYS_CLK_FREQ     33000000
  59 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  60 #endif
  61 #endif
  62
  63 #define CFG_SCCR_INIT           (SCCR_DEFAULT & (~SCCR_CLK_MASK))
  64 #define CFG_SCCR_TSEC1CM        SCCR_TSEC1CM_1  /* TSEC1 clock setting */
  65 #define CFG_SCCR_TSEC2CM        SCCR_TSEC2CM_1  /* TSEC2 clock setting */
  66 #define CFG_SCCR_ENCCM          SCCR_ENCCM_3    /* ENC clock setting */
  67 #define CFG_SCCR_USBCM          SCCR_USBCM_3    /* USB clock setting */
  68 #define CFG_SCCR_VAL            ( CFG_SCCR_INIT         \
  69                                 | CFG_SCCR_TSEC1CM      \
  70                                 | CFG_SCCR_TSEC2CM      \
  71                                 | CFG_SCCR_ENCCM        \
  72                                 | CFG_SCCR_USBCM        )
  73
  74 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
  75
  76 #define CFG_IMMR                0xE0000000
  77
  78 #undef CFG_DRAM_TEST                            /* memory test, takes time */
  79 #define CFG_MEMTEST_START       0x00000000      /* memtest region */
  80 #define CFG_MEMTEST_END         0x00100000
  81
  82 /*
  83  * DDR Setup
  84  */
  85 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  86 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  87 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  88
  89 /*
  90  * 32-bit data path mode.
  91  *
  92  * Please note that using this mode for devices with the real density of 64-bit
  93  * effectively reduces the amount of available memory due to the effect of
  94  * wrapping around while translating address to row/columns, for example in the
  95  * 256MB module the upper 128MB get aliased with contents of the lower
  96  * 128MB); normally this define should be used for devices with real 32-bit
  97  * data path.
  98  */
  99 #undef CONFIG_DDR_32BIT
 100
 101 #define CFG_DDR_BASE            0x00000000      /* DDR is system memory*/
 102 #define CFG_SDRAM_BASE          CFG_DDR_BASE
 103 #define CFG_DDR_SDRAM_BASE      CFG_DDR_BASE
 104 #undef  CONFIG_DDR_2T_TIMING
 105
 106 #if defined(CONFIG_SPD_EEPROM)
 107 /*
 108  * Determine DDR configuration from I2C interface.
 109  */
 110 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 111 #else
 112 /*
 113  * Manually set up DDR parameters
 114  */
 115 #define CFG_DDR_SIZE            256             /* MB */
 116 #define CFG_DDR_CONFIG          (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 117 #define CFG_DDR_TIMING_1        0x36332321
 118 #define CFG_DDR_TIMING_2        0x00000800      /* P9-45,may need tuning */
 119 #define CFG_DDR_CONTROL         0xc2000000      /* unbuffered,no DYN_PWR */
 120 #define CFG_DDR_INTERVAL        0x04060100      /* autocharge,no open page */
 121
 122 #if defined(CONFIG_DDR_32BIT)
 123 /* set burst length to 8 for 32-bit data path */
 124 #define CFG_DDR_MODE            0x00000023      /* DLL,normal,seq,4/2.5, 8 burst len */
 125 #else
 126 /* the default burst length is 4 - for 64-bit data path */
 127 #define CFG_DDR_MODE            0x00000022      /* DLL,normal,seq,4/2.5, 4 burst len */
 128 #endif
 129 #endif
 130
 131 /*
 132  * SDRAM on the Local Bus
 133  */
 134 #define CFG_LBC_SDRAM_BASE      0xF0000000      /* Localbus SDRAM */
 135 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
 136
 137 /*
 138  * FLASH on the Local Bus
 139  */
 140 #define CFG_FLASH_CFI                           /* use the Common Flash Interface */
 141 #define CFG_FLASH_CFI_DRIVER                    /* use the CFI driver */
 142 #define CFG_FLASH_BASE          0xFE000000      /* start of FLASH   */
 143 #define CFG_FLASH_SIZE          8               /* flash size in MB */
 144 /* #define CFG_FLASH_USE_BUFFER_WRITE */
 145
 146 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE |       /* flash Base address */ \
 147                                 (2 << BR_PS_SHIFT) |    /* 32 bit port size */   \
 148                                 BR_V)                   /* valid */
 149
 150 #define CFG_OR0_PRELIM          0xFF806FF7      /* 8 MB flash size */
 151 #define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE  /* window base at flash base */
 152 #define CFG_LBLAWAR0_PRELIM     0x80000016      /* 8 MB window size */
 153
 154 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 155 #define CFG_MAX_FLASH_SECT      64              /* sectors per device */
 156
 157 #undef CFG_FLASH_CHECKSUM
 158 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 159 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 160
 161 #define CFG_MID_FLASH_JUMP      0x7F000000
 162 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 163
 164 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 165 #define CFG_RAMBOOT
 166 #else
 167 #undef  CFG_RAMBOOT
 168 #endif
 169
 170 /*
 171  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 172  */
 173 #define CFG_BCSR                0xE2400000
 174 #define CFG_LBLAWBAR1_PRELIM    CFG_BCSR                /* Access window base at BCSR base */
 175 #define CFG_LBLAWAR1_PRELIM     0x8000000E              /* Access window size 32K */
 176 #define CFG_BR1_PRELIM          (CFG_BCSR|0x00000801)   /* Port-size=8bit, MSEL=GPCM */
 177 #define CFG_OR1_PRELIM          0xFFFFE8F0              /* length 32K */
 178
 179 #define CONFIG_L1_INIT_RAM
 180 #define CFG_INIT_RAM_LOCK       1
 181 #define CFG_INIT_RAM_ADDR       0xFD000000              /* Initial RAM address */
 182 #define CFG_INIT_RAM_END        0x1000                  /* End of used area in RAM*/
 183
 184 #define CFG_GBL_DATA_SIZE       0x100                   /* num bytes initial data */
 185 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 186 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 187
 188 #define CFG_MONITOR_LEN         (256 * 1024)            /* Reserve 256 kB for Mon */
 189 #define CFG_MALLOC_LEN          (128 * 1024)            /* Reserved for malloc */
 190
 191 /*
 192  * Local Bus LCRR and LBCR regs
 193  *    LCRR:  DLL bypass, Clock divider is 4
 194  * External Local Bus rate is
 195  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 196  */
 197 #define CFG_LCRR        (LCRR_DBYP | LCRR_CLKDIV_4)
 198 #define CFG_LBC_LBCR    0x00000000
 199
 200 #define CFG_LB_SDRAM    /* if board has SRDAM on local bus */
 201
 202 #ifdef CFG_LB_SDRAM
 203 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 204 /*
 205  * Base Register 2 and Option Register 2 configure SDRAM.
 206  * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 207  *
 208  * For BR2, need:
 209  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 210  *    port-size = 32-bits = BR2[19:20] = 11
 211  *    no parity checking = BR2[21:22] = 00
 212  *    SDRAM for MSEL = BR2[24:26] = 011
 213  *    Valid = BR[31] = 1
 214  *
 215  * 0    4    8    12   16   20   24   28
 216  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 217  *
 218  * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 219  * FIXME: the top 17 bits of BR2.
 220  */
 221
 222 #define CFG_BR2_PRELIM          0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
 223 #define CFG_LBLAWBAR2_PRELIM    0xF0000000
 224 #define CFG_LBLAWAR2_PRELIM     0x80000019 /* 64M */
 225
 226 /*
 227  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 228  *
 229  * For OR2, need:
 230  *    64MB mask for AM, OR2[0:7] = 1111 1100
 231  *                 XAM, OR2[17:18] = 11
 232  *    9 columns OR2[19-21] = 010
 233  *    13 rows   OR2[23-25] = 100
 234  *    EAD set for extra time OR[31] = 1
 235  *
 236  * 0    4    8    12   16   20   24   28
 237  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 238  */
 239
 240 #define CFG_OR2_PRELIM  0xFC006901
 241
 242 #define CFG_LBC_LSRT    0x32000000    /* LB sdram refresh timer, about 6us */
 243 #define CFG_LBC_MRTPR   0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 244
 245 /*
 246  * LSDMR masks
 247  */
 248 #define CFG_LBC_LSDMR_RFEN      (1 << (31 -  1))
 249 #define CFG_LBC_LSDMR_BSMA1516  (3 << (31 - 10))
 250 #define CFG_LBC_LSDMR_BSMA1617  (4 << (31 - 10))
 251 #define CFG_LBC_LSDMR_RFCR5     (3 << (31 - 16))
 252 #define CFG_LBC_LSDMR_RFCR8     (5 << (31 - 16))
 253 #define CFG_LBC_LSDMR_RFCR16    (7 << (31 - 16))
 254 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
 255 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
 256 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
 257 #define CFG_LBC_LSDMR_ACTTORW3  (3 << (31 - 22))
 258 #define CFG_LBC_LSDMR_ACTTORW7  (7 << (31 - 22))
 259 #define CFG_LBC_LSDMR_ACTTORW6  (6 << (31 - 22))
 260 #define CFG_LBC_LSDMR_BL8       (1 << (31 - 23))
 261 #define CFG_LBC_LSDMR_WRC2      (2 << (31 - 27))
 262 #define CFG_LBC_LSDMR_WRC3      (3 << (31 - 27))
 263 #define CFG_LBC_LSDMR_WRC4      (0 << (31 - 27))
 264 #define CFG_LBC_LSDMR_BUFCMD    (1 << (31 - 29))
 265 #define CFG_LBC_LSDMR_CL3       (3 << (31 - 31))
 266
 267 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
 268 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
 269 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
 270 #define CFG_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
 271 #define CFG_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
 272 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
 273 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
 274 #define CFG_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
 275
 276 #define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
 277                                 | CFG_LBC_LSDMR_BSMA1516        \
 278                                 | CFG_LBC_LSDMR_RFCR8           \
 279                                 | CFG_LBC_LSDMR_PRETOACT6       \
 280                                 | CFG_LBC_LSDMR_ACTTORW3        \
 281                                 | CFG_LBC_LSDMR_BL8             \
 282                                 | CFG_LBC_LSDMR_WRC3            \
 283                                 | CFG_LBC_LSDMR_CL3             \
 284                                 )
 285
 286 /*
 287  * SDRAM Controller configuration sequence.
 288  */
 289 #define CFG_LBC_LSDMR_1         ( CFG_LBC_LSDMR_COMMON \
 290                                 | CFG_LBC_LSDMR_OP_PCHALL)
 291 #define CFG_LBC_LSDMR_2         ( CFG_LBC_LSDMR_COMMON \
 292                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 293 #define CFG_LBC_LSDMR_3         ( CFG_LBC_LSDMR_COMMON \
 294                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 295 #define CFG_LBC_LSDMR_4         ( CFG_LBC_LSDMR_COMMON \
 296                                 | CFG_LBC_LSDMR_OP_MRW)
 297 #define CFG_LBC_LSDMR_5         ( CFG_LBC_LSDMR_COMMON \
 298                                 | CFG_LBC_LSDMR_OP_NORMAL)
 299 #endif
 300
 301 /*
 302  * Serial Port
 303  */
 304 #define CONFIG_CONS_INDEX     1
 305 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 306 #define CFG_NS16550
 307 #define CFG_NS16550_SERIAL
 308 #define CFG_NS16550_REG_SIZE    1
 309 #define CFG_NS16550_CLK         get_bus_freq(0)
 310
 311 #define CFG_BAUDRATE_TABLE  \
 312         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 313
 314 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
 315 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 316
 317 /* Use the HUSH parser */
 318 #define CFG_HUSH_PARSER
 319 #ifdef  CFG_HUSH_PARSER
 320 #define CFG_PROMPT_HUSH_PS2 "> "
 321 #endif
 322
 323 /* pass open firmware flat tree */
 324 #define CONFIG_OF_FLAT_TREE     1
 325 #define CONFIG_OF_BOARD_SETUP   1
 326
 327 /* maximum size of the flat tree (8K) */
 328 #define OF_FLAT_TREE_MAX_SIZE   8192
 329
 330 #define OF_CPU                  "PowerPC,8349@0"
 331 #define OF_SOC                  "soc8349@e0000000"
 332 #define OF_TBCLK                (bd->bi_busfreq / 4)
 333 #define OF_STDOUT_PATH          "/soc8349@e0000000/serial@4500"
 334
 335 /* I2C */
 336 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 337 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
 338 #define CONFIG_FSL_I2C
 339 #define CONFIG_I2C_MULTI_BUS
 340 #define CONFIG_I2C_CMD_TREE
 341 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 342 #define CFG_I2C_SLAVE           0x7F
 343 #define CFG_I2C_NOPROBES        {{0,0x69}}      /* Don't probe these addrs */
 344 #define CFG_I2C_OFFSET          0x3000
 345 #define CFG_I2C2_OFFSET         0x3100
 346
 347 /* TSEC */
 348 #define CFG_TSEC1_OFFSET 0x24000
 349 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
 350 #define CFG_TSEC2_OFFSET 0x25000
 351 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
 352
 353 /* USB */
 354 #define CFG_USE_MPC834XSYS_USB_PHY      1 /* Use SYS board PHY */
 355
 356 /*
 357  * General PCI
 358  * Addresses are mapped 1-1.
 359  */
 360 #define CFG_PCI1_MEM_BASE       0x80000000
 361 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 362 #define CFG_PCI1_MEM_SIZE       0x10000000      /* 256M */
 363 #define CFG_PCI1_MMIO_BASE      0x90000000
 364 #define CFG_PCI1_MMIO_PHYS      CFG_PCI1_MMIO_BASE
 365 #define CFG_PCI1_MMIO_SIZE      0x10000000      /* 256M */
 366 #define CFG_PCI1_IO_BASE        0x00000000
 367 #define CFG_PCI1_IO_PHYS        0xE2000000
 368 #define CFG_PCI1_IO_SIZE        0x00100000      /* 1M */
 369
 370 #define CFG_PCI2_MEM_BASE       0xA0000000
 371 #define CFG_PCI2_MEM_PHYS       CFG_PCI2_MEM_BASE
 372 #define CFG_PCI2_MEM_SIZE       0x10000000      /* 256M */
 373 #define CFG_PCI2_MMIO_BASE      0xB0000000
 374 #define CFG_PCI2_MMIO_PHYS      CFG_PCI2_MMIO_BASE
 375 #define CFG_PCI2_MMIO_SIZE      0x10000000      /* 256M */
 376 #define CFG_PCI2_IO_BASE        0x00000000
 377 #define CFG_PCI2_IO_PHYS        0xE2100000
 378 #define CFG_PCI2_IO_SIZE        0x00100000      /* 1M */
 379
 380 #if defined(CONFIG_PCI)
 381
 382 #define PCI_ONE_PCI1
 383 #if defined(PCI_64BIT)
 384 #undef PCI_ALL_PCI1
 385 #undef PCI_TWO_PCI1
 386 #undef PCI_ONE_PCI1
 387 #endif
 388
 389 #define CONFIG_NET_MULTI
 390 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 391
 392 #undef CONFIG_EEPRO100
 393 #undef CONFIG_TULIP
 394
 395 #if !defined(CONFIG_PCI_PNP)
 396         #define PCI_ENET0_IOADDR        0xFIXME
 397         #define PCI_ENET0_MEMADDR       0xFIXME
 398         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 399 #endif
 400
 401 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 402 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 403
 404 #endif  /* CONFIG_PCI */
 405
 406 /*
 407  * TSEC configuration
 408  */
 409 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 410
 411 #if defined(CONFIG_TSEC_ENET)
 412 #ifndef CONFIG_NET_MULTI
 413 #define CONFIG_NET_MULTI        1
 414 #endif
 415
 416 #define CONFIG_GMII             1       /* MII PHY management */
 417 #define CONFIG_MPC83XX_TSEC1    1
 418 #define CONFIG_MPC83XX_TSEC1_NAME       "TSEC0"
 419 #define CONFIG_MPC83XX_TSEC2    1
 420 #define CONFIG_MPC83XX_TSEC2_NAME       "TSEC1"
 421 #define TSEC1_PHY_ADDR          0
 422 #define TSEC2_PHY_ADDR          1
 423 #define TSEC1_PHYIDX            0
 424 #define TSEC2_PHYIDX            0
 425
 426 /* Options are: TSEC[0-1] */
 427 #define CONFIG_ETHPRIME         "TSEC0"
 428
 429 #endif  /* CONFIG_TSEC_ENET */
 430
 431 /*
 432  * Configure on-board RTC
 433  */
 434 #define CONFIG_RTC_DS1374                       /* use ds1374 rtc via i2c       */
 435 #define CFG_I2C_RTC_ADDR                0x68    /* at address 0x68              */
 436
 437 /*
 438  * Environment
 439  */
 440 #ifndef CFG_RAMBOOT
 441         #define CFG_ENV_IS_IN_FLASH     1
 442         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 443         #define CFG_ENV_SECT_SIZE       0x20000 /* 128K(one sector) for env */
 444         #define CFG_ENV_SIZE            0x2000
 445
 446 /* Address and size of Redundant Environment Sector     */
 447 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 448 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 449
 450 #else
 451         #define CFG_NO_FLASH            1       /* Flash is not usable now */
 452         #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only */
 453         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
 454         #define CFG_ENV_SIZE            0x2000
 455 #endif
 456
 457 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 458 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 459
 460 #if defined(CFG_RAMBOOT)
 461 #if defined(CONFIG_PCI)
 462 #define  CONFIG_COMMANDS        ((CONFIG_CMD_DFL        \
 463                                  | CFG_CMD_PING         \
 464                                  | CFG_CMD_PCI          \
 465                                  | CFG_CMD_I2C          \
 466                                  | CFG_CMD_DATE)        \
 467                                 &                       \
 468                                  ~(CFG_CMD_ENV          \
 469                                   | CFG_CMD_LOADS))
 470 #else
 471 #define  CONFIG_COMMANDS        ((CONFIG_CMD_DFL        \
 472                                  | CFG_CMD_PING         \
 473                                  | CFG_CMD_I2C          \
 474                                  | CFG_CMD_DATE)        \
 475                                 &                       \
 476                                  ~(CFG_CMD_ENV          \
 477                                   | CFG_CMD_LOADS))
 478 #endif
 479 #else
 480 #if defined(CONFIG_PCI)
 481 #define  CONFIG_COMMANDS        (CONFIG_CMD_DFL         \
 482                                 | CFG_CMD_PCI           \
 483                                 | CFG_CMD_PING          \
 484                                 | CFG_CMD_I2C           \
 485                                 | CFG_CMD_DATE          \
 486                                 )
 487 #else
 488 #define  CONFIG_COMMANDS        (CONFIG_CMD_DFL         \
 489                                 | CFG_CMD_PING          \
 490                                 | CFG_CMD_I2C           \
 491                                 | CFG_CMD_MII           \
 492                                 | CFG_CMD_DATE          \
 493                                 )
 494 #endif
 495 #endif
 496
 497 #include <cmd_confdefs.h>
 498
 499 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 500
 501 /*
 502  * Miscellaneous configurable options
 503  */
 504 #define CFG_LONGHELP                    /* undef to save memory */
 505 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 506 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 507
 508 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 509         #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 510 #else
 511         #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 512 #endif
 513
 514 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 515 #define CFG_MAXARGS     16              /* max number of command args */
 516 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 517 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 518
 519 /*
 520  * For booting Linux, the board info and command line data
 521  * have to be in the first 8 MB of memory, since this is
 522  * the maximum mapped by the Linux kernel during initialization.
 523  */
 524 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 525
 526 /* Cache Configuration */
 527 #define CFG_DCACHE_SIZE         32768
 528 #define CFG_CACHELINE_SIZE      32
 529 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 530 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value*/
 531 #endif
 532
 533 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 534
 535 #if 1 /*528/264*/
 536 #define CFG_HRCW_LOW (\
 537         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 538         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 539         HRCWL_CSB_TO_CLKIN |\
 540         HRCWL_VCO_1X2 |\
 541         HRCWL_CORE_TO_CSB_2X1)
 542 #elif 0 /*396/132*/
 543 #define CFG_HRCW_LOW (\
 544         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 545         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 546         HRCWL_CSB_TO_CLKIN |\
 547         HRCWL_VCO_1X4 |\
 548         HRCWL_CORE_TO_CSB_3X1)
 549 #elif 0 /*264/132*/
 550 #define CFG_HRCW_LOW (\
 551         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 552         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 553         HRCWL_CSB_TO_CLKIN |\
 554         HRCWL_VCO_1X4 |\
 555         HRCWL_CORE_TO_CSB_2X1)
 556 #elif 0 /*132/132*/
 557 #define CFG_HRCW_LOW (\
 558         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 559         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 560         HRCWL_CSB_TO_CLKIN |\
 561         HRCWL_VCO_1X4 |\
 562         HRCWL_CORE_TO_CSB_1X1)
 563 #elif 0 /*264/264 */
 564 #define CFG_HRCW_LOW (\
 565         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 566         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 567         HRCWL_CSB_TO_CLKIN |\
 568         HRCWL_VCO_1X4 |\
 569         HRCWL_CORE_TO_CSB_1X1)
 570 #endif
 571
 572 #if defined(PCI_64BIT)
 573 #define CFG_HRCW_HIGH (\
 574         HRCWH_PCI_HOST |\
 575         HRCWH_64_BIT_PCI |\
 576         HRCWH_PCI1_ARBITER_ENABLE |\
 577         HRCWH_PCI2_ARBITER_DISABLE |\
 578         HRCWH_CORE_ENABLE |\
 579         HRCWH_FROM_0X00000100 |\
 580         HRCWH_BOOTSEQ_DISABLE |\
 581         HRCWH_SW_WATCHDOG_DISABLE |\
 582         HRCWH_ROM_LOC_LOCAL_16BIT |\
 583         HRCWH_TSEC1M_IN_GMII |\
 584         HRCWH_TSEC2M_IN_GMII )
 585 #else
 586 #define CFG_HRCW_HIGH (\
 587         HRCWH_PCI_HOST |\
 588         HRCWH_32_BIT_PCI |\
 589         HRCWH_PCI1_ARBITER_ENABLE |\
 590         HRCWH_PCI2_ARBITER_ENABLE |\
 591         HRCWH_CORE_ENABLE |\
 592         HRCWH_FROM_0X00000100 |\
 593         HRCWH_BOOTSEQ_DISABLE |\
 594         HRCWH_SW_WATCHDOG_DISABLE |\
 595         HRCWH_ROM_LOC_LOCAL_16BIT |\
 596         HRCWH_TSEC1M_IN_GMII |\
 597         HRCWH_TSEC2M_IN_GMII )
 598 #endif
 599
 600 /* System IO Config */
 601 #define CFG_SICRH SICRH_TSOBI1
 602 #define CFG_SICRL SICRL_LDP_A
 603
 604 #define CFG_HID0_INIT   0x000000000
 605 #define CFG_HID0_FINAL  HID0_ENABLE_MACHINE_CHECK
 606
 607 /* #define CFG_HID0_FINAL               (\
 608         HID0_ENABLE_INSTRUCTION_CACHE |\
 609         HID0_ENABLE_M_BIT |\
 610         HID0_ENABLE_ADDRESS_BROADCAST ) */
 611
 612
 613 #define CFG_HID2 HID2_HBE
 614
 615 /* DDR @ 0x00000000 */
 616 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 617 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 618
 619 /* PCI @ 0x80000000 */
 620 #ifdef CONFIG_PCI
 621 #define CFG_IBAT1L      (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 622 #define CFG_IBAT1U      (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 623 #define CFG_IBAT2L      (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 624 #define CFG_IBAT2U      (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 625 #else
 626 #define CFG_IBAT1L      (0)
 627 #define CFG_IBAT1U      (0)
 628 #define CFG_IBAT2L      (0)
 629 #define CFG_IBAT2U      (0)
 630 #endif
 631
 632 #ifdef CONFIG_MPC83XX_PCI2
 633 #define CFG_IBAT3L      (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 634 #define CFG_IBAT3U      (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 635 #define CFG_IBAT4L      (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 636 #define CFG_IBAT4U      (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 637 #else
 638 #define CFG_IBAT3L      (0)
 639 #define CFG_IBAT3U      (0)
 640 #define CFG_IBAT4L      (0)
 641 #define CFG_IBAT4U      (0)
 642 #endif
 643
 644 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 645 #define CFG_IBAT5L      (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 646 #define CFG_IBAT5U      (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 647
 648 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 649 #define CFG_IBAT6L      (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
 650 #define CFG_IBAT6U      (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 651
 652 #define CFG_IBAT7L      (0)
 653 #define CFG_IBAT7U      (0)
 654
 655 #define CFG_DBAT0L      CFG_IBAT0L
 656 #define CFG_DBAT0U      CFG_IBAT0U
 657 #define CFG_DBAT1L      CFG_IBAT1L
 658 #define CFG_DBAT1U      CFG_IBAT1U
 659 #define CFG_DBAT2L      CFG_IBAT2L
 660 #define CFG_DBAT2U      CFG_IBAT2U
 661 #define CFG_DBAT3L      CFG_IBAT3L
 662 #define CFG_DBAT3U      CFG_IBAT3U
 663 #define CFG_DBAT4L      CFG_IBAT4L
 664 #define CFG_DBAT4U      CFG_IBAT4U
 665 #define CFG_DBAT5L      CFG_IBAT5L
 666 #define CFG_DBAT5U      CFG_IBAT5U
 667 #define CFG_DBAT6L      CFG_IBAT6L
 668 #define CFG_DBAT6U      CFG_IBAT6U
 669 #define CFG_DBAT7L      CFG_IBAT7L
 670 #define CFG_DBAT7U      CFG_IBAT7U
 671
 672 /*
 673  * Internal Definitions
 674  *
 675  * Boot Flags
 676  */
 677 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 678 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 679
 680 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 681 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 682 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 683 #endif
 684
 685 /*
 686  * Environment Configuration
 687  */
 688 #define CONFIG_ENV_OVERWRITE
 689
 690 #if defined(CONFIG_TSEC_ENET)
 691 #define CONFIG_ETHADDR          00:04:9f:ef:23:33
 692 #define CONFIG_HAS_ETH1
 693 #define CONFIG_ETH1ADDR         00:E0:0C:00:7E:21
 694 #endif
 695
 696 #define CONFIG_IPADDR           192.168.1.253
 697
 698 #define CONFIG_HOSTNAME         mpc8349emds
 699 #define CONFIG_ROOTPATH         /nfsroot/rootfs
 700 #define CONFIG_BOOTFILE         uImage
 701
 702 #define CONFIG_SERVERIP         192.168.1.1
 703 #define CONFIG_GATEWAYIP        192.168.1.1
 704 #define CONFIG_NETMASK          255.255.255.0
 705
 706 #define CONFIG_LOADADDR         200000  /* default location for tftp and bootm */
 707
 708 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 709 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 710
 711 #define CONFIG_BAUDRATE  115200
 712
 713 #define CONFIG_PREBOOT  "echo;" \
 714         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 715         "echo"
 716
 717 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 718         "netdev=eth0\0"                                                 \
 719         "hostname=mpc8349emds\0"                                        \
 720         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 721                 "nfsroot=${serverip}:${rootpath}\0"                     \
 722         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 723         "addip=setenv bootargs ${bootargs} "                            \
 724                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 725                 ":${hostname}:${netdev}:off panic=1\0"                  \
 726         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 727         "flash_nfs=run nfsargs addip addtty;"                           \
 728                 "bootm ${kernel_addr}\0"                                \
 729         "flash_self=run ramargs addip addtty;"                          \
 730                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 731         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 732                 "bootm\0"                                               \
 733         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 734         "update=protect off fe000000 fe03ffff; "                        \
 735                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"     \
 736         "upd=run load;run update\0"                                     \
 737         "fdtaddr=400000\0"                                              \
 738         "fdtfile=mpc8349emds.dtb\0"                                     \
 739         ""
 740
 741 #define CONFIG_NFSBOOTCOMMAND                                           \
 742    "setenv bootargs root=/dev/nfs rw "                                  \
 743       "nfsroot=$serverip:$rootpath "                                    \
 744       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 745       "console=$consoledev,$baudrate $othbootargs;"                     \
 746    "tftp $loadaddr $bootfile;"                                          \
 747    "tftp $fdtaddr $fdtfile;"                                            \
 748    "bootm $loadaddr - $fdtaddr"
 749
 750 #define CONFIG_RAMBOOTCOMMAND                                           \
 751    "setenv bootargs root=/dev/ram rw "                                  \
 752       "console=$consoledev,$baudrate $othbootargs;"                     \
 753    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 754    "tftp $loadaddr $bootfile;"                                          \
 755    "tftp $fdtaddr $fdtfile;"                                            \
 756    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 757
 758 #define CONFIG_BOOTCOMMAND      "run flash_self"
 759
 760 #endif  /* __CONFIG_H */