include/configs/MPC8349EMDS.h

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * mpc8349emds board configuration file
  26  *
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_E300             1       /* E300 Family */
  36 #define CONFIG_MPC83xx          1       /* MPC83xx family */
  37 #define CONFIG_MPC834x          1       /* MPC834x family */
  38 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  39 #define CONFIG_MPC8349EMDS      1       /* MPC8349EMDS board specific */
  40
  41 #undef CONFIG_PCI
  42 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  43
  44 #define PCI_66M
  45 #ifdef PCI_66M
  46 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  47 #else
  48 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  49 #endif
  50
  51 #ifdef CONFIG_PCISLAVE
  52 #define CONFIG_PCI
  53 #define CONFIG_83XX_PCICLK      66666666        /* in Hz */
  54 #endif /* CONFIG_PCISLAVE */
  55
  56 #ifndef CONFIG_SYS_CLK_FREQ
  57 #ifdef PCI_66M
  58 #define CONFIG_SYS_CLK_FREQ     66000000
  59 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  60 #else
  61 #define CONFIG_SYS_CLK_FREQ     33000000
  62 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  63 #endif
  64 #endif
  65
  66 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
  67
  68 #define CONFIG_SYS_IMMR         0xE0000000
  69
  70 #undef CONFIG_SYS_DRAM_TEST                             /* memory test, takes time */
  71 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  72 #define CONFIG_SYS_MEMTEST_END          0x00100000
  73
  74 /*
  75  * DDR Setup
  76  */
  77 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  78 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  79 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  80
  81 /*
  82  * 32-bit data path mode.
  83  *
  84  * Please note that using this mode for devices with the real density of 64-bit
  85  * effectively reduces the amount of available memory due to the effect of
  86  * wrapping around while translating address to row/columns, for example in the
  87  * 256MB module the upper 128MB get aliased with contents of the lower
  88  * 128MB); normally this define should be used for devices with real 32-bit
  89  * data path.
  90  */
  91 #undef CONFIG_DDR_32BIT
  92
  93 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  94 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  95 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  96 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  97                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  98 #undef  CONFIG_DDR_2T_TIMING
  99
 100 /*
 101  * DDRCDR - DDR Control Driver Register
 102  */
 103 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 104
 105 #if defined(CONFIG_SPD_EEPROM)
 106 /*
 107  * Determine DDR configuration from I2C interface.
 108  */
 109 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 110 #else
 111 /*
 112  * Manually set up DDR parameters
 113  */
 114 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 115 #if defined(CONFIG_DDR_II)
 116 #define CONFIG_SYS_DDRCDR               0x80080001
 117 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
 118 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
 119 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
 120 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
 121 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
 122 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 123 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
 124 #define CONFIG_SYS_DDR_MODE             0x47d00432
 125 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 126 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
 127 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 128 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 129 #else
 130 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 131 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 132 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 133 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 134 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 135
 136 #if defined(CONFIG_DDR_32BIT)
 137 /* set burst length to 8 for 32-bit data path */
 138 #define CONFIG_SYS_DDR_MODE             0x00000023      /* DLL,normal,seq,4/2.5, 8 burst len */
 139 #else
 140 /* the default burst length is 4 - for 64-bit data path */
 141 #define CONFIG_SYS_DDR_MODE             0x00000022      /* DLL,normal,seq,4/2.5, 4 burst len */
 142 #endif
 143 #endif
 144 #endif
 145
 146 /*
 147  * SDRAM on the Local Bus
 148  */
 149 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 150 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 151
 152 /*
 153  * FLASH on the Local Bus
 154  */
 155 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 156 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 157 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 158 #define CONFIG_SYS_FLASH_SIZE           32              /* max flash size in MB */
 159 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
 160 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 161
 162 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE |        /* flash Base address */ \
 163                                 (2 << BR_PS_SHIFT) |    /* 16 bit port size */   \
 164                                 BR_V)                   /* valid */
 165 #define CONFIG_SYS_OR0_PRELIM           ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 166                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 167                                 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 168 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE   /* window base at flash base */
 169 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018      /* 32 MB window size */
 170
 171 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 172 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max sectors per device */
 173
 174 #undef CONFIG_SYS_FLASH_CHECKSUM
 175 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 176 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 177
 178 #define CONFIG_SYS_MID_FLASH_JUMP       0x7F000000
 179 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 180
 181 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 182 #define CONFIG_SYS_RAMBOOT
 183 #else
 184 #undef  CONFIG_SYS_RAMBOOT
 185 #endif
 186
 187 /*
 188  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 189  */
 190 #define CONFIG_SYS_BCSR         0xE2400000
 191 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR         /* Access window base at BCSR base */
 192 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E              /* Access window size 32K */
 193 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR|0x00000801)    /* Port-size=8bit, MSEL=GPCM */
 194 #define CONFIG_SYS_OR1_PRELIM           0xFFFFE8F0              /* length 32K */
 195
 196 #define CONFIG_SYS_INIT_RAM_LOCK        1
 197 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000              /* Initial RAM address */
 198 #define CONFIG_SYS_INIT_RAM_END 0x1000                  /* End of used area in RAM*/
 199
 200 #define CONFIG_SYS_GBL_DATA_SIZE        0x100                   /* num bytes initial data */
 201 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 202 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 203
 204 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)            /* Reserve 384 kB for Mon */
 205 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)            /* Reserved for malloc */
 206
 207 /*
 208  * Local Bus LCRR and LBCR regs
 209  *    LCRR:  DLL bypass, Clock divider is 4
 210  * External Local Bus rate is
 211  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 212  */
 213 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
 214 #define CONFIG_SYS_LBC_LBCR     0x00000000
 215
 216 /*
 217  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 218  * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
 219  */
 220 #undef CONFIG_SYS_LB_SDRAM
 221
 222 #ifdef CONFIG_SYS_LB_SDRAM
 223 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 224 /*
 225  * Base Register 2 and Option Register 2 configure SDRAM.
 226  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 227  *
 228  * For BR2, need:
 229  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 230  *    port-size = 32-bits = BR2[19:20] = 11
 231  *    no parity checking = BR2[21:22] = 00
 232  *    SDRAM for MSEL = BR2[24:26] = 011
 233  *    Valid = BR[31] = 1
 234  *
 235  * 0    4    8    12   16   20   24   28
 236  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 237  *
 238  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 239  * FIXME: the top 17 bits of BR2.
 240  */
 241
 242 #define CONFIG_SYS_BR2_PRELIM           0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
 243 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0xF0000000
 244 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019 /* 64M */
 245
 246 /*
 247  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 248  *
 249  * For OR2, need:
 250  *    64MB mask for AM, OR2[0:7] = 1111 1100
 251  *                 XAM, OR2[17:18] = 11
 252  *    9 columns OR2[19-21] = 010
 253  *    13 rows   OR2[23-25] = 100
 254  *    EAD set for extra time OR[31] = 1
 255  *
 256  * 0    4    8    12   16   20   24   28
 257  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 258  */
 259
 260 #define CONFIG_SYS_OR2_PRELIM   0xFC006901
 261
 262 #define CONFIG_SYS_LBC_LSRT     0x32000000    /* LB sdram refresh timer, about 6us */
 263 #define CONFIG_SYS_LBC_MRTPR    0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 264
 265 #define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
 266                                 | LSDMR_BSMA1516        \
 267                                 | LSDMR_RFCR8           \
 268                                 | LSDMR_PRETOACT6       \
 269                                 | LSDMR_ACTTORW3        \
 270                                 | LSDMR_BL8             \
 271                                 | LSDMR_WRC3            \
 272                                 | LSDMR_CL3             \
 273                                 )
 274
 275 /*
 276  * SDRAM Controller configuration sequence.
 277  */
 278 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 279 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 280 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 281 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 282 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 283 #endif
 284
 285 /*
 286  * Serial Port
 287  */
 288 #define CONFIG_CONS_INDEX     1
 289 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 290 #define CONFIG_SYS_NS16550
 291 #define CONFIG_SYS_NS16550_SERIAL
 292 #define CONFIG_SYS_NS16550_REG_SIZE    1
 293 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 294
 295 #define CONFIG_SYS_BAUDRATE_TABLE  \
 296         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 297
 298 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 299 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 300
 301 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 302 /* Use the HUSH parser */
 303 #define CONFIG_SYS_HUSH_PARSER
 304 #ifdef  CONFIG_SYS_HUSH_PARSER
 305 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 306 #endif
 307
 308 /* pass open firmware flat tree */
 309 #define CONFIG_OF_LIBFDT        1
 310 #define CONFIG_OF_BOARD_SETUP   1
 311 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 312
 313 /* I2C */
 314 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 315 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
 316 #define CONFIG_FSL_I2C
 317 #define CONFIG_I2C_MULTI_BUS
 318 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 319 #define CONFIG_SYS_I2C_SLAVE            0x7F
 320 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 321 #define CONFIG_SYS_I2C_OFFSET           0x3000
 322 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 323
 324 /* SPI */
 325 #define CONFIG_MPC8XXX_SPI
 326 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 327
 328 /* GPIOs.  Used as SPI chip selects */
 329 #define CONFIG_SYS_GPIO1_PRELIM
 330 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 331 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 332
 333 /* TSEC */
 334 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 335 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 336 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 337 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 338
 339 /* USB */
 340 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 341
 342 /*
 343  * General PCI
 344  * Addresses are mapped 1-1.
 345  */
 346 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 347 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 348 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 349 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 350 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 351 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 352 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 353 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 354 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 355
 356 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 357 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 358 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 359 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 360 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 361 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 362 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 363 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
 364 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 365
 366 #if defined(CONFIG_PCI)
 367
 368 #define PCI_ONE_PCI1
 369 #if defined(PCI_64BIT)
 370 #undef PCI_ALL_PCI1
 371 #undef PCI_TWO_PCI1
 372 #undef PCI_ONE_PCI1
 373 #endif
 374
 375 #define CONFIG_NET_MULTI
 376 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 377 #define CONFIG_83XX_GENERIC_PCI
 378 #define CONFIG_83XX_PCI_STREAMING
 379
 380 #undef CONFIG_EEPRO100
 381 #undef CONFIG_TULIP
 382
 383 #if !defined(CONFIG_PCI_PNP)
 384         #define PCI_ENET0_IOADDR        0xFIXME
 385         #define PCI_ENET0_MEMADDR       0xFIXME
 386         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 387 #endif
 388
 389 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 390 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 391
 392 #endif  /* CONFIG_PCI */
 393
 394 /*
 395  * TSEC configuration
 396  */
 397 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 398
 399 #if defined(CONFIG_TSEC_ENET)
 400 #ifndef CONFIG_NET_MULTI
 401 #define CONFIG_NET_MULTI        1
 402 #endif
 403
 404 #define CONFIG_GMII             1       /* MII PHY management */
 405 #define CONFIG_TSEC1    1
 406 #define CONFIG_TSEC1_NAME       "TSEC0"
 407 #define CONFIG_TSEC2    1
 408 #define CONFIG_TSEC2_NAME       "TSEC1"
 409 #define TSEC1_PHY_ADDR          0
 410 #define TSEC2_PHY_ADDR          1
 411 #define TSEC1_PHYIDX            0
 412 #define TSEC2_PHYIDX            0
 413 #define TSEC1_FLAGS             TSEC_GIGABIT
 414 #define TSEC2_FLAGS             TSEC_GIGABIT
 415
 416 /* Options are: TSEC[0-1] */
 417 #define CONFIG_ETHPRIME         "TSEC0"
 418
 419 #endif  /* CONFIG_TSEC_ENET */
 420
 421 /*
 422  * Configure on-board RTC
 423  */
 424 #define CONFIG_RTC_DS1374                       /* use ds1374 rtc via i2c       */
 425 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68              */
 426
 427 /*
 428  * Environment
 429  */
 430 #ifndef CONFIG_SYS_RAMBOOT
 431         #define CONFIG_ENV_IS_IN_FLASH  1
 432         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 433         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 434         #define CONFIG_ENV_SIZE         0x2000
 435
 436 /* Address and size of Redundant Environment Sector     */
 437 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 438 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 439
 440 #else
 441         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 442         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 443         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 444         #define CONFIG_ENV_SIZE         0x2000
 445 #endif
 446
 447 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 448 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 449
 450
 451 /*
 452  * BOOTP options
 453  */
 454 #define CONFIG_BOOTP_BOOTFILESIZE
 455 #define CONFIG_BOOTP_BOOTPATH
 456 #define CONFIG_BOOTP_GATEWAY
 457 #define CONFIG_BOOTP_HOSTNAME
 458
 459
 460 /*
 461  * Command line configuration.
 462  */
 463 #include <config_cmd_default.h>
 464
 465 #define CONFIG_CMD_PING
 466 #define CONFIG_CMD_I2C
 467 #define CONFIG_CMD_DATE
 468 #define CONFIG_CMD_MII
 469
 470 #if defined(CONFIG_PCI)
 471     #define CONFIG_CMD_PCI
 472 #endif
 473
 474 #if defined(CONFIG_SYS_RAMBOOT)
 475     #undef CONFIG_CMD_SAVEENV
 476     #undef CONFIG_CMD_LOADS
 477 #endif
 478
 479
 480 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 481
 482 /*
 483  * Miscellaneous configurable options
 484  */
 485 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 486 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 487 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 488
 489 #if defined(CONFIG_CMD_KGDB)
 490         #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 491 #else
 492         #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 493 #endif
 494
 495 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 496 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 497 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 498 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 499
 500 /*
 501  * For booting Linux, the board info and command line data
 502  * have to be in the first 8 MB of memory, since this is
 503  * the maximum mapped by the Linux kernel during initialization.
 504  */
 505 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 506
 507 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 508
 509 #if 1 /*528/264*/
 510 #define CONFIG_SYS_HRCW_LOW (\
 511         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 512         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 513         HRCWL_CSB_TO_CLKIN |\
 514         HRCWL_VCO_1X2 |\
 515         HRCWL_CORE_TO_CSB_2X1)
 516 #elif 0 /*396/132*/
 517 #define CONFIG_SYS_HRCW_LOW (\
 518         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 519         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 520         HRCWL_CSB_TO_CLKIN |\
 521         HRCWL_VCO_1X4 |\
 522         HRCWL_CORE_TO_CSB_3X1)
 523 #elif 0 /*264/132*/
 524 #define CONFIG_SYS_HRCW_LOW (\
 525         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 526         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 527         HRCWL_CSB_TO_CLKIN |\
 528         HRCWL_VCO_1X4 |\
 529         HRCWL_CORE_TO_CSB_2X1)
 530 #elif 0 /*132/132*/
 531 #define CONFIG_SYS_HRCW_LOW (\
 532         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 533         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 534         HRCWL_CSB_TO_CLKIN |\
 535         HRCWL_VCO_1X4 |\
 536         HRCWL_CORE_TO_CSB_1X1)
 537 #elif 0 /*264/264 */
 538 #define CONFIG_SYS_HRCW_LOW (\
 539         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 540         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 541         HRCWL_CSB_TO_CLKIN |\
 542         HRCWL_VCO_1X4 |\
 543         HRCWL_CORE_TO_CSB_1X1)
 544 #endif
 545
 546 #ifdef CONFIG_PCISLAVE
 547 #define CONFIG_SYS_HRCW_HIGH (\
 548         HRCWH_PCI_AGENT |\
 549         HRCWH_64_BIT_PCI |\
 550         HRCWH_PCI1_ARBITER_DISABLE |\
 551         HRCWH_PCI2_ARBITER_DISABLE |\
 552         HRCWH_CORE_ENABLE |\
 553         HRCWH_FROM_0X00000100 |\
 554         HRCWH_BOOTSEQ_DISABLE |\
 555         HRCWH_SW_WATCHDOG_DISABLE |\
 556         HRCWH_ROM_LOC_LOCAL_16BIT |\
 557         HRCWH_TSEC1M_IN_GMII |\
 558         HRCWH_TSEC2M_IN_GMII )
 559 #else
 560 #if defined(PCI_64BIT)
 561 #define CONFIG_SYS_HRCW_HIGH (\
 562         HRCWH_PCI_HOST |\
 563         HRCWH_64_BIT_PCI |\
 564         HRCWH_PCI1_ARBITER_ENABLE |\
 565         HRCWH_PCI2_ARBITER_DISABLE |\
 566         HRCWH_CORE_ENABLE |\
 567         HRCWH_FROM_0X00000100 |\
 568         HRCWH_BOOTSEQ_DISABLE |\
 569         HRCWH_SW_WATCHDOG_DISABLE |\
 570         HRCWH_ROM_LOC_LOCAL_16BIT |\
 571         HRCWH_TSEC1M_IN_GMII |\
 572         HRCWH_TSEC2M_IN_GMII )
 573 #else
 574 #define CONFIG_SYS_HRCW_HIGH (\
 575         HRCWH_PCI_HOST |\
 576         HRCWH_32_BIT_PCI |\
 577         HRCWH_PCI1_ARBITER_ENABLE |\
 578         HRCWH_PCI2_ARBITER_ENABLE |\
 579         HRCWH_CORE_ENABLE |\
 580         HRCWH_FROM_0X00000100 |\
 581         HRCWH_BOOTSEQ_DISABLE |\
 582         HRCWH_SW_WATCHDOG_DISABLE |\
 583         HRCWH_ROM_LOC_LOCAL_16BIT |\
 584         HRCWH_TSEC1M_IN_GMII |\
 585         HRCWH_TSEC2M_IN_GMII )
 586 #endif /* PCI_64BIT */
 587 #endif /* CONFIG_PCISLAVE */
 588
 589 /*
 590  * System performance
 591  */
 592 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 593 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
 594 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 595 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 596 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 597 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 598
 599 /* System IO Config */
 600 #define CONFIG_SYS_SICRH 0
 601 #define CONFIG_SYS_SICRL SICRL_LDP_A
 602
 603 #define CONFIG_SYS_HID0_INIT    0x000000000
 604 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_MACHINE_CHECK
 605
 606 /* #define CONFIG_SYS_HID0_FINAL                (\
 607         HID0_ENABLE_INSTRUCTION_CACHE |\
 608         HID0_ENABLE_M_BIT |\
 609         HID0_ENABLE_ADDRESS_BROADCAST ) */
 610
 611
 612 #define CONFIG_SYS_HID2 HID2_HBE
 613 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 614
 615 /* DDR @ 0x00000000 */
 616 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 617 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 618
 619 /* PCI @ 0x80000000 */
 620 #ifdef CONFIG_PCI
 621 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 622 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 623 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 624 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 625 #else
 626 #define CONFIG_SYS_IBAT1L       (0)
 627 #define CONFIG_SYS_IBAT1U       (0)
 628 #define CONFIG_SYS_IBAT2L       (0)
 629 #define CONFIG_SYS_IBAT2U       (0)
 630 #endif
 631
 632 #ifdef CONFIG_MPC83XX_PCI2
 633 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 634 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 635 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 636 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 637 #else
 638 #define CONFIG_SYS_IBAT3L       (0)
 639 #define CONFIG_SYS_IBAT3U       (0)
 640 #define CONFIG_SYS_IBAT4L       (0)
 641 #define CONFIG_SYS_IBAT4U       (0)
 642 #endif
 643
 644 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 645 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 646 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 647
 648 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 649 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
 650                                  BATL_GUARDEDSTORAGE)
 651 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 652
 653 #define CONFIG_SYS_IBAT7L       (0)
 654 #define CONFIG_SYS_IBAT7U       (0)
 655
 656 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 657 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 658 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 659 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 660 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 661 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 662 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 663 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 664 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 665 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 666 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 667 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 668 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 669 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 670 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 671 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 672
 673 /*
 674  * Internal Definitions
 675  *
 676  * Boot Flags
 677  */
 678 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 679 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 680
 681 #if defined(CONFIG_CMD_KGDB)
 682 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 683 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 684 #endif
 685
 686 /*
 687  * Environment Configuration
 688  */
 689 #define CONFIG_ENV_OVERWRITE
 690
 691 #if defined(CONFIG_TSEC_ENET)
 692 #define CONFIG_ETHADDR          00:04:9f:ef:23:33
 693 #define CONFIG_HAS_ETH1
 694 #define CONFIG_HAS_ETH0
 695 #define CONFIG_ETH1ADDR         00:E0:0C:00:7E:21
 696 #endif
 697
 698 #define CONFIG_IPADDR           192.168.1.253
 699
 700 #define CONFIG_HOSTNAME         mpc8349emds
 701 #define CONFIG_ROOTPATH         /nfsroot/rootfs
 702 #define CONFIG_BOOTFILE         uImage
 703
 704 #define CONFIG_SERVERIP         192.168.1.1
 705 #define CONFIG_GATEWAYIP        192.168.1.1
 706 #define CONFIG_NETMASK          255.255.255.0
 707
 708 #define CONFIG_LOADADDR         500000  /* default location for tftp and bootm */
 709
 710 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 711 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 712
 713 #define CONFIG_BAUDRATE  115200
 714
 715 #define CONFIG_PREBOOT  "echo;" \
 716         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 717         "echo"
 718
 719 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 720         "netdev=eth0\0"                                                 \
 721         "hostname=mpc8349emds\0"                                        \
 722         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 723                 "nfsroot=${serverip}:${rootpath}\0"                     \
 724         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 725         "addip=setenv bootargs ${bootargs} "                            \
 726                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 727                 ":${hostname}:${netdev}:off panic=1\0"                  \
 728         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 729         "flash_nfs=run nfsargs addip addtty;"                           \
 730                 "bootm ${kernel_addr}\0"                                \
 731         "flash_self=run ramargs addip addtty;"                          \
 732                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 733         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 734                 "bootm\0"                                               \
 735         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 736         "update=protect off fe000000 fe03ffff; "                        \
 737                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"     \
 738         "upd=run load update\0"                                         \
 739         "fdtaddr=400000\0"                                              \
 740         "fdtfile=mpc8349emds.dtb\0"                                     \
 741         ""
 742
 743 #define CONFIG_NFSBOOTCOMMAND                                           \
 744    "setenv bootargs root=/dev/nfs rw "                                  \
 745       "nfsroot=$serverip:$rootpath "                                    \
 746       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 747       "console=$consoledev,$baudrate $othbootargs;"                     \
 748    "tftp $loadaddr $bootfile;"                                          \
 749    "tftp $fdtaddr $fdtfile;"                                            \
 750    "bootm $loadaddr - $fdtaddr"
 751
 752 #define CONFIG_RAMBOOTCOMMAND                                           \
 753    "setenv bootargs root=/dev/ram rw "                                  \
 754       "console=$consoledev,$baudrate $othbootargs;"                     \
 755    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 756    "tftp $loadaddr $bootfile;"                                          \
 757    "tftp $fdtaddr $fdtfile;"                                            \
 758    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 759
 760 #define CONFIG_BOOTCOMMAND      "run flash_self"
 761
 762 #endif  /* __CONFIG_H */