include/configs/MPC8349EMDS_SDRAM.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2006-2010
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  */
   6
   7 /*
   8  * mpc8349emds board configuration file
   9  *
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1       /* E300 Family */
  19
  20 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  21 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  22 #define CONFIG_SYS_MEMTEST_END          0x00100000
  23
  24 /*
  25  * DDR Setup
  26  */
  27 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  28 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  29 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  30
  31 /*
  32  * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  33  * unselect it to use old spd_sdram.c
  34  */
  35 #define CONFIG_SYS_SPD_BUS_NUM  0
  36 #define SPD_EEPROM_ADDRESS1     0x52
  37 #define SPD_EEPROM_ADDRESS2     0x51
  38 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  39 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  40 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  41 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  42
  43 /*
  44  * 32-bit data path mode.
  45  *
  46  * Please note that using this mode for devices with the real density of 64-bit
  47  * effectively reduces the amount of available memory due to the effect of
  48  * wrapping around while translating address to row/columns, for example in the
  49  * 256MB module the upper 128MB get aliased with contents of the lower
  50  * 128MB); normally this define should be used for devices with real 32-bit
  51  * data path.
  52  */
  53 #undef CONFIG_DDR_32BIT
  54
  55 #define CONFIG_SYS_SDRAM_BASE   0x00000000      /* DDR is system memory*/
  56 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  57                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  58 #undef  CONFIG_DDR_2T_TIMING
  59
  60 /*
  61  * DDRCDR - DDR Control Driver Register
  62  */
  63 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  64
  65 #if defined(CONFIG_SPD_EEPROM)
  66 /*
  67  * Determine DDR configuration from I2C interface.
  68  */
  69 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
  70 #else
  71 /*
  72  * Manually set up DDR parameters
  73  */
  74 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  75 #if defined(CONFIG_DDR_II)
  76 #define CONFIG_SYS_DDRCDR               0x80080001
  77 #define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
  78 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
  79 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
  80 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
  81 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
  82 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
  83 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
  84 #define CONFIG_SYS_DDR_MODE             0x47d00432
  85 #define CONFIG_SYS_DDR_MODE2            0x8000c000
  86 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
  87 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
  88 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  89 #else
  90 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  91                                 | CSCONFIG_ROW_BIT_13 \
  92                                 | CSCONFIG_COL_BIT_10)
  93 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  94 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  95 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
  96 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
  97
  98 #if defined(CONFIG_DDR_32BIT)
  99 /* set burst length to 8 for 32-bit data path */
 100                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 101 #define CONFIG_SYS_DDR_MODE     0x00000023
 102 #else
 103 /* the default burst length is 4 - for 64-bit data path */
 104                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 105 #define CONFIG_SYS_DDR_MODE     0x00000022
 106 #endif
 107 #endif
 108 #endif
 109
 110 /*
 111  * SDRAM on the Local Bus
 112  */
 113 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 114 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 115
 116 /*
 117  * FLASH on the Local Bus
 118  */
 119 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 120 #define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
 121
 122 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 123 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 124
 125 #undef CONFIG_SYS_FLASH_CHECKSUM
 126 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 127 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 128
 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 130
 131 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 132 #define CONFIG_SYS_RAMBOOT
 133 #else
 134 #undef  CONFIG_SYS_RAMBOOT
 135 #endif
 136
 137 /*
 138  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 139  */
 140 #define CONFIG_SYS_BCSR                 0xE2400000
 141                                         /* Access window base at BCSR base */
 142 #define CONFIG_SYS_INIT_RAM_LOCK        1
 143 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 144 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 145
 146 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 147                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 148 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 149
 150 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 151 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 152
 153 /*
 154  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 155  */
 156
 157 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 158 /*
 159  * Base Register 2 and Option Register 2 configure SDRAM.
 160  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 161  *
 162  * For BR2, need:
 163  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 164  *    port-size = 32-bits = BR2[19:20] = 11
 165  *    no parity checking = BR2[21:22] = 00
 166  *    SDRAM for MSEL = BR2[24:26] = 011
 167  *    Valid = BR[31] = 1
 168  *
 169  * 0    4    8    12   16   20   24   28
 170  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 171  */
 172
 173 /*
 174  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 175  *
 176  * For OR2, need:
 177  *    64MB mask for AM, OR2[0:7] = 1111 1100
 178  *                 XAM, OR2[17:18] = 11
 179  *    9 columns OR2[19-21] = 010
 180  *    13 rows   OR2[23-25] = 100
 181  *    EAD set for extra time OR[31] = 1
 182  *
 183  * 0    4    8    12   16   20   24   28
 184  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 185  */
 186
 187
 188                                 /* LB sdram refresh timer, about 6us */
 189 #define CONFIG_SYS_LBC_LSRT     0x32000000
 190                                 /* LB refresh timer prescal, 266MHz/32 */
 191 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 192
 193 #define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN      \
 194                                 | LSDMR_BSMA1516        \
 195                                 | LSDMR_RFCR8           \
 196                                 | LSDMR_PRETOACT6       \
 197                                 | LSDMR_ACTTORW3        \
 198                                 | LSDMR_BL8             \
 199                                 | LSDMR_WRC3            \
 200                                 | LSDMR_CL3)
 201
 202 /*
 203  * SDRAM Controller configuration sequence.
 204  */
 205 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 206 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 207 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 208 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 209 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 210
 211 /*
 212  * Serial Port
 213  */
 214 #define CONFIG_SYS_NS16550_SERIAL
 215 #define CONFIG_SYS_NS16550_REG_SIZE    1
 216 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 217
 218 #define CONFIG_SYS_BAUDRATE_TABLE  \
 219                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 220
 221 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 222 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 223
 224 /* I2C */
 225 #define CONFIG_SYS_I2C
 226 #define CONFIG_SYS_I2C_FSL
 227 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 228 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 229 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 230 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 231 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 232 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 233 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 234
 235 /* SPI */
 236 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 237
 238 /* GPIOs.  Used as SPI chip selects */
 239 #define CONFIG_SYS_GPIO1_PRELIM
 240 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 241 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 242
 243 /* TSEC */
 244 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 245 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 246 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 247 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 248
 249 /* USB */
 250 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 251
 252 /*
 253  * General PCI
 254  * Addresses are mapped 1-1.
 255  */
 256 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 257 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 258 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 259 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 260 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 261 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 262 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 263 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 264 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 265
 266 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 267 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 268 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 269 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 270 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 271 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 272 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 273 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 274 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 275
 276 #if defined(CONFIG_PCI)
 277
 278 #define CONFIG_83XX_PCI_STREAMING
 279
 280 #undef CONFIG_EEPRO100
 281 #undef CONFIG_TULIP
 282
 283 #if !defined(CONFIG_PCI_PNP)
 284         #define PCI_ENET0_IOADDR        0xFIXME
 285         #define PCI_ENET0_MEMADDR       0xFIXME
 286         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 287 #endif
 288
 289 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 290 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 291
 292 #endif  /* CONFIG_PCI */
 293
 294 /*
 295  * TSEC configuration
 296  */
 297
 298 #if defined(CONFIG_TSEC_ENET)
 299
 300 #define CONFIG_GMII             1       /* MII PHY management */
 301 #define CONFIG_TSEC1            1
 302 #define CONFIG_TSEC1_NAME       "TSEC0"
 303 #define CONFIG_TSEC2            1
 304 #define CONFIG_TSEC2_NAME       "TSEC1"
 305 #define TSEC1_PHY_ADDR          0
 306 #define TSEC2_PHY_ADDR          1
 307 #define TSEC1_PHYIDX            0
 308 #define TSEC2_PHYIDX            0
 309 #define TSEC1_FLAGS             TSEC_GIGABIT
 310 #define TSEC2_FLAGS             TSEC_GIGABIT
 311
 312 /* Options are: TSEC[0-1] */
 313 #define CONFIG_ETHPRIME         "TSEC0"
 314
 315 #endif  /* CONFIG_TSEC_ENET */
 316
 317 /*
 318  * Configure on-board RTC
 319  */
 320 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 321 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 322
 323 /*
 324  * Environment
 325  */
 326 #ifndef CONFIG_SYS_RAMBOOT
 327         #define CONFIG_ENV_ADDR         \
 328                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 329         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 330         #define CONFIG_ENV_SIZE         0x2000
 331
 332 /* Address and size of Redundant Environment Sector     */
 333 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 334 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 335
 336 #else
 337         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 338         #define CONFIG_ENV_SIZE         0x2000
 339 #endif
 340
 341 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 342 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 343
 344 /*
 345  * BOOTP options
 346  */
 347 #define CONFIG_BOOTP_BOOTFILESIZE
 348
 349 /*
 350  * Command line configuration.
 351  */
 352
 353 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 354
 355 /*
 356  * Miscellaneous configurable options
 357  */
 358 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 359
 360 /*
 361  * For booting Linux, the board info and command line data
 362  * have to be in the first 256 MB of memory, since this is
 363  * the maximum mapped by the Linux kernel during initialization.
 364  */
 365                                 /* Initial Memory map for Linux*/
 366 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 367 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 368
 369 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 370
 371 /*
 372  * System performance
 373  */
 374 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 375 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 376 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 377 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 378
 379 /* System IO Config */
 380 #define CONFIG_SYS_SICRH 0
 381 #define CONFIG_SYS_SICRL SICRL_LDP_A
 382
 383 #ifdef CONFIG_PCI
 384 #define CONFIG_PCI_INDIRECT_BRIDGE
 385 #endif
 386
 387 #if defined(CONFIG_CMD_KGDB)
 388 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 389 #endif
 390
 391 /*
 392  * Environment Configuration
 393  */
 394 #define CONFIG_ENV_OVERWRITE
 395
 396 #if defined(CONFIG_TSEC_ENET)
 397 #define CONFIG_HAS_ETH1
 398 #define CONFIG_HAS_ETH0
 399 #endif
 400
 401 #define CONFIG_HOSTNAME         "mpc8349emds"
 402 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 403 #define CONFIG_BOOTFILE         "uImage"
 404
 405 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 406
 407 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 408         "netdev=eth0\0"                                                 \
 409         "hostname=mpc8349emds\0"                                        \
 410         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 411                 "nfsroot=${serverip}:${rootpath}\0"                     \
 412         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 413         "addip=setenv bootargs ${bootargs} "                            \
 414                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 415                 ":${hostname}:${netdev}:off panic=1\0"                  \
 416         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 417         "flash_nfs=run nfsargs addip addtty;"                           \
 418                 "bootm ${kernel_addr}\0"                                \
 419         "flash_self=run ramargs addip addtty;"                          \
 420                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 421         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 422                 "bootm\0"                                               \
 423         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 424         "update=protect off fe000000 fe03ffff; "                        \
 425                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
 426         "upd=run load update\0"                                         \
 427         "fdtaddr=780000\0"                                              \
 428         "fdtfile=mpc834x_mds.dtb\0"                                     \
 429         ""
 430
 431 #define CONFIG_NFSBOOTCOMMAND                                           \
 432         "setenv bootargs root=/dev/nfs rw "                             \
 433                 "nfsroot=$serverip:$rootpath "                          \
 434                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 435                                                         "$netdev:off "  \
 436                 "console=$consoledev,$baudrate $othbootargs;"           \
 437         "tftp $loadaddr $bootfile;"                                     \
 438         "tftp $fdtaddr $fdtfile;"                                       \
 439         "bootm $loadaddr - $fdtaddr"
 440
 441 #define CONFIG_RAMBOOTCOMMAND                                           \
 442         "setenv bootargs root=/dev/ram rw "                             \
 443                 "console=$consoledev,$baudrate $othbootargs;"           \
 444         "tftp $ramdiskaddr $ramdiskfile;"                               \
 445         "tftp $loadaddr $bootfile;"                                     \
 446         "tftp $fdtaddr $fdtfile;"                                       \
 447         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 448
 449 #define CONFIG_BOOTCOMMAND      "run flash_self"
 450
 451 #endif  /* __CONFIG_H */