include/configs/MPC8349ITX.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  */
   5
   6 /*
   7  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
   8
   9  Memory map:
  10
  11  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  12  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  13  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  14  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  15  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  16  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  17  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  18  0xF001_0000-0xF001_FFFF Local bus expansion slot
  19  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  20  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  21  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  22
  23  I2C address list:
  24                                                 Align.  Board
  25  Bus    Addr    Part No.        Description     Length  Location
  26  ----------------------------------------------------------------
  27  I2C0   0x50    M24256-BWMN6P   Board EEPROM    2       U64
  28
  29  I2C1   0x20    PCF8574         I2C Expander    0       U8
  30  I2C1   0x21    PCF8574         I2C Expander    0       U10
  31  I2C1   0x38    PCF8574A        I2C Expander    0       U8
  32  I2C1   0x39    PCF8574A        I2C Expander    0       U10
  33  I2C1   0x51    (DDR)           DDR EEPROM      1       U1
  34  I2C1   0x68    DS1339          RTC             1       U68
  35
  36  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  37 */
  38
  39 #ifndef __CONFIG_H
  40 #define __CONFIG_H
  41
  42 #define CONFIG_MISC_INIT_F
  43
  44 /*
  45  * On-board devices
  46  */
  47
  48 #ifdef CONFIG_TARGET_MPC8349ITX
  49 /* The CF card interface on the back of the board */
  50 #define CONFIG_COMPACT_FLASH
  51 #define CONFIG_VSC7385_ENET     /* VSC7385 ethernet support */
  52 #define CONFIG_SYS_USB_HOST     /* use the EHCI USB controller */
  53 #endif
  54
  55 #define CONFIG_RTC_DS1337
  56 #define CONFIG_SYS_I2C
  57
  58 /*
  59  * Device configurations
  60  */
  61
  62 /* I2C */
  63 #ifdef CONFIG_SYS_I2C
  64 #define CONFIG_SYS_I2C_FSL
  65 #define CONFIG_SYS_FSL_I2C_SPEED        400000
  66 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  67 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
  68 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
  69 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
  70 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
  71
  72 #define CONFIG_SYS_SPD_BUS_NUM          1       /* The I2C bus for SPD */
  73 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC */
  74
  75 #define CONFIG_SYS_I2C_8574_ADDR1       0x20    /* I2C1, PCF8574 */
  76 #define CONFIG_SYS_I2C_8574_ADDR2       0x21    /* I2C1, PCF8574 */
  77 #define CONFIG_SYS_I2C_8574A_ADDR1      0x38    /* I2C1, PCF8574A */
  78 #define CONFIG_SYS_I2C_8574A_ADDR2      0x39    /* I2C1, PCF8574A */
  79 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C0, Board EEPROM */
  80 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* I2C1, DS1339 RTC*/
  81 #define SPD_EEPROM_ADDRESS              0x51    /* I2C1, DDR */
  82
  83 /* Don't probe these addresses: */
  84 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
  85                                  {1, CONFIG_SYS_I2C_8574_ADDR2}, \
  86                                  {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
  87                                  {1, CONFIG_SYS_I2C_8574A_ADDR2} }
  88 /* Bit definitions for the 8574[A] I2C expander */
  89                                 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
  90 #define I2C_8574_REVISION       0x03
  91 #define I2C_8574_CF             0x08    /* 1=Compact flash absent, 0=present */
  92 #define I2C_8574_MPCICLKRN      0x10    /* MiniPCI Clk Run */
  93 #define I2C_8574_PCI66          0x20    /* 0=33MHz PCI, 1=66MHz PCI */
  94 #define I2C_8574_FLASHSIDE      0x40    /* 0=Reset vector from U4, 1=from U7*/
  95
  96 #endif
  97
  98 /* Compact Flash */
  99 #ifdef CONFIG_COMPACT_FLASH
 100
 101 #define CONFIG_SYS_IDE_MAXBUS           1
 102 #define CONFIG_SYS_IDE_MAXDEVICE        1
 103
 104 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 105 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF_BASE
 106 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000
 107 #define CONFIG_SYS_ATA_REG_OFFSET       0
 108 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0200
 109 #define CONFIG_SYS_ATA_STRIDE           2
 110
 111 /* If a CF card is not inserted, time out quickly */
 112 #define ATA_RESET_TIME  1
 113
 114 #endif
 115
 116 /*
 117  * SATA
 118  */
 119 #ifdef CONFIG_SATA_SIL3114
 120
 121 #define CONFIG_SYS_SATA_MAX_DEVICE      4
 122 #define CONFIG_LBA48
 123
 124 #endif
 125
 126 #ifdef CONFIG_SYS_USB_HOST
 127 /*
 128  * Support USB
 129  */
 130 #define CONFIG_USB_EHCI_FSL
 131
 132 /* Current USB implementation supports the only USB controller,
 133  * so we have to choose between the MPH or the DR ones */
 134 #if 1
 135 #define CONFIG_HAS_FSL_MPH_USB
 136 #else
 137 #define CONFIG_HAS_FSL_DR_USB
 138 #endif
 139
 140 #endif
 141
 142 /*
 143  * DDR Setup
 144  */
 145 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory*/
 146 #define CONFIG_SYS_83XX_DDR_USES_CS0
 147
 148 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 149                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 150
 151 #define CONFIG_VERY_BIG_RAM
 152 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
 153
 154 #ifdef CONFIG_SYS_I2C
 155 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
 156 #endif
 157
 158 /* No SPD? Then manually set up DDR parameters */
 159 #ifndef CONFIG_SPD_EEPROM
 160     #define CONFIG_SYS_DDR_SIZE         256     /* Mb */
 161     #define CONFIG_SYS_DDR_CS0_CONFIG   (CSCONFIG_EN \
 162                                         | CSCONFIG_ROW_BIT_13 \
 163                                         | CSCONFIG_COL_BIT_10)
 164
 165     #define CONFIG_SYS_DDR_TIMING_1     0x26242321
 166     #define CONFIG_SYS_DDR_TIMING_2     0x00000800  /* P9-45, may need tuning */
 167 #endif
 168
 169 /*
 170  *Flash on the Local Bus
 171  */
 172
 173 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 174 #define CONFIG_SYS_FLASH_EMPTY_INFO
 175 /* 127 64KB sectors + 8 8KB sectors per device */
 176 #define CONFIG_SYS_MAX_FLASH_SECT       135
 177 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 178 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 179 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 180
 181 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 182 boards, we say we have two, but don't display a message if we find only one. */
 183 #define CONFIG_SYS_FLASH_QUIET_TEST
 184 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 185 #define CONFIG_SYS_FLASH_BANKS_LIST     \
 186                 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
 187 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size in MB */
 188
 189 /* Vitesse 7385 */
 190
 191 #ifdef CONFIG_VSC7385_ENET
 192
 193 #define CONFIG_TSEC2
 194
 195 /* The flash address and size of the VSC7385 firmware image */
 196 #define CONFIG_VSC7385_IMAGE            0xFEFFE000
 197 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 198
 199 #endif
 200
 201 /*
 202  * BRx, ORx, LBLAWBARx, and LBLAWARx
 203  */
 204
 205
 206 /* Vitesse 7385 */
 207
 208 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
 209
 210 #define CONFIG_SYS_LED_BASE     0xF9000000
 211
 212
 213 /* Compact Flash */
 214
 215 #ifdef CONFIG_COMPACT_FLASH
 216
 217 #define CONFIG_SYS_CF_BASE      0xF0000000
 218
 219
 220 #endif
 221
 222 /*
 223  * U-Boot memory configuration
 224  */
 225 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 226
 227 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 228 #define CONFIG_SYS_RAMBOOT
 229 #else
 230 #undef  CONFIG_SYS_RAMBOOT
 231 #endif
 232
 233 #define CONFIG_SYS_INIT_RAM_LOCK
 234 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 235 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 236
 237 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 238                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 239 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 240
 241 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 242 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 243 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
 244
 245 /*
 246  * Serial Port
 247  */
 248 #define CONFIG_SYS_NS16550_SERIAL
 249 #define CONFIG_SYS_NS16550_REG_SIZE     1
 250 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 251
 252 #define CONFIG_SYS_BAUDRATE_TABLE  \
 253                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 254
 255 #define CONSOLE                 ttyS0
 256
 257 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 258 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 259
 260 /*
 261  * PCI
 262  */
 263 #ifdef CONFIG_PCI
 264 #define CONFIG_PCI_INDIRECT_BRIDGE
 265
 266 #define CONFIG_MPC83XX_PCI2
 267
 268 /*
 269  * General PCI
 270  * Addresses are mapped 1-1.
 271  */
 272 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 273 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 274 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 275 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 276                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 277 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 278 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 279 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 280 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 281 #define CONFIG_SYS_PCI1_IO_SIZE         0x01000000      /* 16M */
 282
 283 #ifdef CONFIG_MPC83XX_PCI2
 284 #define CONFIG_SYS_PCI2_MEM_BASE        \
 285                         (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
 286 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 287 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 288 #define CONFIG_SYS_PCI2_MMIO_BASE       \
 289                         (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
 290 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 291 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 292 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 293 #define CONFIG_SYS_PCI2_IO_PHYS         \
 294                         (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
 295 #define CONFIG_SYS_PCI2_IO_SIZE         0x01000000      /* 16M */
 296 #endif
 297
 298 #ifndef CONFIG_PCI_PNP
 299     #define PCI_ENET0_IOADDR    0x00000000
 300     #define PCI_ENET0_MEMADDR   CONFIG_SYS_PCI2_MEM_BASE
 301     #define PCI_IDSEL_NUMBER    0x0f    /* IDSEL = AD15 */
 302 #endif
 303
 304 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 305
 306 #endif
 307
 308 /* TSEC */
 309
 310 #ifdef CONFIG_TSEC_ENET
 311 #define CONFIG_TSEC1
 312
 313 #ifdef CONFIG_TSEC1
 314 #define CONFIG_HAS_ETH0
 315 #define CONFIG_TSEC1_NAME  "TSEC0"
 316 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 317 #define TSEC1_PHY_ADDR          0x1c    /* VSC8201 uses address 0x1c */
 318 #define TSEC1_PHYIDX            0
 319 #define TSEC1_FLAGS             TSEC_GIGABIT
 320 #endif
 321
 322 #ifdef CONFIG_TSEC2
 323 #define CONFIG_HAS_ETH1
 324 #define CONFIG_TSEC2_NAME  "TSEC1"
 325 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 326
 327 #define TSEC2_PHY_ADDR          4
 328 #define TSEC2_PHYIDX            0
 329 #define TSEC2_FLAGS             TSEC_GIGABIT
 330 #endif
 331
 332 #define CONFIG_ETHPRIME         "Freescale TSEC"
 333
 334 #endif
 335
 336 /*
 337  * Environment
 338  */
 339 #define CONFIG_ENV_OVERWRITE
 340
 341 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 342 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 343
 344 /*
 345  * BOOTP options
 346  */
 347 #define CONFIG_BOOTP_BOOTFILESIZE
 348
 349 /* Watchdog */
 350 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 351
 352 /*
 353  * Miscellaneous configurable options
 354  */
 355
 356 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 357 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 358
 359 /*
 360  * For booting Linux, the board info and command line data
 361  * have to be in the first 256 MB of memory, since this is
 362  * the maximum mapped by the Linux kernel during initialization.
 363  */
 364                                 /* Initial Memory map for Linux*/
 365 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 366 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 367
 368 /*
 369  * System performance
 370  */
 371 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 372 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 373 #define CONFIG_SYS_SCCR_USBMPHCM 3      /* USB MPH controller's clock */
 374 #define CONFIG_SYS_SCCR_USBDRCM 0       /* USB DR controller's clock */
 375
 376 /*
 377  * System IO Config
 378  */
 379 /* Needed for gigabit to work on TSEC 1 */
 380 #define CONFIG_SYS_SICRH SICRH_TSOBI1
 381                                 /* USB DR as device + USB MPH as host */
 382 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1)
 383
 384 #if defined(CONFIG_CMD_KGDB)
 385 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 386 #endif
 387
 388 /*
 389  * Environment Configuration
 390  */
 391 #define CONFIG_ENV_OVERWRITE
 392
 393 #define CONFIG_NETDEV           "eth0"
 394
 395 /* Default path and filenames */
 396 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 397 #define CONFIG_BOOTFILE         "uImage"
 398                                 /* U-Boot image on TFTP server */
 399 #define CONFIG_UBOOTPATH        "u-boot.bin"
 400
 401 #ifdef CONFIG_TARGET_MPC8349ITX
 402 #define CONFIG_FDTFILE          "mpc8349emitx.dtb"
 403 #else
 404 #define CONFIG_FDTFILE          "mpc8349emitxgp.dtb"
 405 #endif
 406
 407
 408 #define CONFIG_EXTRA_ENV_SETTINGS \
 409         "console=" __stringify(CONSOLE) "\0"                    \
 410         "netdev=" CONFIG_NETDEV "\0"                                    \
 411         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 412         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 413                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 414                         " +$filesize; " \
 415                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 416                         " +$filesize; " \
 417                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 418                         " $filesize; "  \
 419                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 420                         " +$filesize; " \
 421                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 422                         " $filesize\0"  \
 423         "fdtaddr=780000\0"                                              \
 424         "fdtfile=" CONFIG_FDTFILE "\0"
 425
 426 #define CONFIG_NFSBOOTCOMMAND                                           \
 427         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"  \
 428         " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
 429         " console=$console,$baudrate $othbootargs; "                    \
 430         "tftp $loadaddr $bootfile;"                                     \
 431         "tftp $fdtaddr $fdtfile;"                                       \
 432         "bootm $loadaddr - $fdtaddr"
 433
 434 #define CONFIG_RAMBOOTCOMMAND                                           \
 435         "setenv bootargs root=/dev/ram rw"                              \
 436         " console=$console,$baudrate $othbootargs; "                    \
 437         "tftp $ramdiskaddr $ramdiskfile;"                               \
 438         "tftp $loadaddr $bootfile;"                                     \
 439         "tftp $fdtaddr $fdtfile;"                                       \
 440         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 441
 442 #endif