include/configs/MPC8349ITX.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  */
   5
   6 /*
   7  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
   8
   9  Memory map:
  10
  11  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  12  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  13  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  14  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  15  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  16  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  17  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  18  0xF001_0000-0xF001_FFFF Local bus expansion slot
  19  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  20  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  21  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  22
  23  I2C address list:
  24                                                 Align.  Board
  25  Bus    Addr    Part No.        Description     Length  Location
  26  ----------------------------------------------------------------
  27  I2C0   0x50    M24256-BWMN6P   Board EEPROM    2       U64
  28
  29  I2C1   0x20    PCF8574         I2C Expander    0       U8
  30  I2C1   0x21    PCF8574         I2C Expander    0       U10
  31  I2C1   0x38    PCF8574A        I2C Expander    0       U8
  32  I2C1   0x39    PCF8574A        I2C Expander    0       U10
  33  I2C1   0x51    (DDR)           DDR EEPROM      1       U1
  34  I2C1   0x68    DS1339          RTC             1       U68
  35
  36  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  37 */
  38
  39 #ifndef __CONFIG_H
  40 #define __CONFIG_H
  41
  42 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
  43 #define CONFIG_SYS_LOWBOOT
  44 #endif
  45
  46 /*
  47  * High Level Configuration Options
  48  */
  49 #define CONFIG_MPC834x          /* MPC834x family (8343, 8347, 8349) */
  50 #define CONFIG_MPC8349          /* MPC8349 specific */
  51
  52 #define CONFIG_SYS_IMMR 0xE0000000      /* The IMMR is relocated to here */
  53
  54 #define CONFIG_MISC_INIT_F
  55
  56 /*
  57  * On-board devices
  58  */
  59
  60 #ifdef CONFIG_MPC8349ITX
  61 /* The CF card interface on the back of the board */
  62 #define CONFIG_COMPACT_FLASH
  63 #define CONFIG_VSC7385_ENET     /* VSC7385 ethernet support */
  64 #define CONFIG_SYS_USB_HOST     /* use the EHCI USB controller */
  65 #endif
  66
  67 #define CONFIG_RTC_DS1337
  68 #define CONFIG_SYS_I2C
  69
  70 /*
  71  * Device configurations
  72  */
  73
  74 /* I2C */
  75 #ifdef CONFIG_SYS_I2C
  76 #define CONFIG_SYS_I2C_FSL
  77 #define CONFIG_SYS_FSL_I2C_SPEED        400000
  78 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  79 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
  80 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
  81 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
  82 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
  83
  84 #define CONFIG_SYS_SPD_BUS_NUM          1       /* The I2C bus for SPD */
  85 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC */
  86
  87 #define CONFIG_SYS_I2C_8574_ADDR1       0x20    /* I2C1, PCF8574 */
  88 #define CONFIG_SYS_I2C_8574_ADDR2       0x21    /* I2C1, PCF8574 */
  89 #define CONFIG_SYS_I2C_8574A_ADDR1      0x38    /* I2C1, PCF8574A */
  90 #define CONFIG_SYS_I2C_8574A_ADDR2      0x39    /* I2C1, PCF8574A */
  91 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C0, Board EEPROM */
  92 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* I2C1, DS1339 RTC*/
  93 #define SPD_EEPROM_ADDRESS              0x51    /* I2C1, DDR */
  94
  95 /* Don't probe these addresses: */
  96 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
  97                                  {1, CONFIG_SYS_I2C_8574_ADDR2}, \
  98                                  {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
  99                                  {1, CONFIG_SYS_I2C_8574A_ADDR2} }
 100 /* Bit definitions for the 8574[A] I2C expander */
 101                                 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
 102 #define I2C_8574_REVISION       0x03
 103 #define I2C_8574_CF             0x08    /* 1=Compact flash absent, 0=present */
 104 #define I2C_8574_MPCICLKRN      0x10    /* MiniPCI Clk Run */
 105 #define I2C_8574_PCI66          0x20    /* 0=33MHz PCI, 1=66MHz PCI */
 106 #define I2C_8574_FLASHSIDE      0x40    /* 0=Reset vector from U4, 1=from U7*/
 107
 108 #endif
 109
 110 /* Compact Flash */
 111 #ifdef CONFIG_COMPACT_FLASH
 112
 113 #define CONFIG_SYS_IDE_MAXBUS           1
 114 #define CONFIG_SYS_IDE_MAXDEVICE        1
 115
 116 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 117 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF_BASE
 118 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000
 119 #define CONFIG_SYS_ATA_REG_OFFSET       0
 120 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0200
 121 #define CONFIG_SYS_ATA_STRIDE           2
 122
 123 /* If a CF card is not inserted, time out quickly */
 124 #define ATA_RESET_TIME  1
 125
 126 #endif
 127
 128 /*
 129  * SATA
 130  */
 131 #ifdef CONFIG_SATA_SIL3114
 132
 133 #define CONFIG_SYS_SATA_MAX_DEVICE      4
 134 #define CONFIG_LBA48
 135
 136 #endif
 137
 138 #ifdef CONFIG_SYS_USB_HOST
 139 /*
 140  * Support USB
 141  */
 142 #define CONFIG_USB_EHCI_FSL
 143
 144 /* Current USB implementation supports the only USB controller,
 145  * so we have to choose between the MPH or the DR ones */
 146 #if 1
 147 #define CONFIG_HAS_FSL_MPH_USB
 148 #else
 149 #define CONFIG_HAS_FSL_DR_USB
 150 #endif
 151
 152 #endif
 153
 154 /*
 155  * DDR Setup
 156  */
 157 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 158 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 159 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 160 #define CONFIG_SYS_83XX_DDR_USES_CS0
 161 #define CONFIG_SYS_MEMTEST_START        0x1000  /* memtest region */
 162 #define CONFIG_SYS_MEMTEST_END          0x2000
 163
 164 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 165                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 166
 167 #define CONFIG_VERY_BIG_RAM
 168 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
 169
 170 #ifdef CONFIG_SYS_I2C
 171 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
 172 #endif
 173
 174 /* No SPD? Then manually set up DDR parameters */
 175 #ifndef CONFIG_SPD_EEPROM
 176     #define CONFIG_SYS_DDR_SIZE         256     /* Mb */
 177     #define CONFIG_SYS_DDR_CS0_CONFIG   (CSCONFIG_EN \
 178                                         | CSCONFIG_ROW_BIT_13 \
 179                                         | CSCONFIG_COL_BIT_10)
 180
 181     #define CONFIG_SYS_DDR_TIMING_1     0x26242321
 182     #define CONFIG_SYS_DDR_TIMING_2     0x00000800  /* P9-45, may need tuning */
 183 #endif
 184
 185 /*
 186  *Flash on the Local Bus
 187  */
 188
 189 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 190 #define CONFIG_SYS_FLASH_EMPTY_INFO
 191 /* 127 64KB sectors + 8 8KB sectors per device */
 192 #define CONFIG_SYS_MAX_FLASH_SECT       135
 193 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 194 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 195 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 196
 197 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 198 boards, we say we have two, but don't display a message if we find only one. */
 199 #define CONFIG_SYS_FLASH_QUIET_TEST
 200 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 201 #define CONFIG_SYS_FLASH_BANKS_LIST     \
 202                 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
 203 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size in MB */
 204
 205 /* Vitesse 7385 */
 206
 207 #ifdef CONFIG_VSC7385_ENET
 208
 209 #define CONFIG_TSEC2
 210
 211 /* The flash address and size of the VSC7385 firmware image */
 212 #define CONFIG_VSC7385_IMAGE            0xFEFFE000
 213 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 214
 215 #endif
 216
 217 /*
 218  * BRx, ORx, LBLAWBARx, and LBLAWARx
 219  */
 220
 221 /* Flash */
 222
 223 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 224                                 | BR_PS_16 \
 225                                 | BR_MS_GPCM \
 226                                 | BR_V)
 227 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 228                                 | OR_UPM_XAM \
 229                                 | OR_GPCM_CSNT \
 230                                 | OR_GPCM_ACS_DIV2 \
 231                                 | OR_GPCM_XACS \
 232                                 | OR_GPCM_SCY_15 \
 233                                 | OR_GPCM_TRLX_SET \
 234                                 | OR_GPCM_EHTR_SET \
 235                                 | OR_GPCM_EAD)
 236 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 237 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 238
 239 /* Vitesse 7385 */
 240
 241 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
 242
 243 #ifdef CONFIG_VSC7385_ENET
 244
 245 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_VSC7385_BASE \
 246                                 | BR_PS_8 \
 247                                 | BR_MS_GPCM \
 248                                 | BR_V)
 249 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128KB \
 250                                 | OR_GPCM_CSNT \
 251                                 | OR_GPCM_XACS \
 252                                 | OR_GPCM_SCY_15 \
 253                                 | OR_GPCM_SETA \
 254                                 | OR_GPCM_TRLX_SET \
 255                                 | OR_GPCM_EHTR_SET \
 256                                 | OR_GPCM_EAD)
 257
 258 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_VSC7385_BASE
 259 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 260
 261 #endif
 262
 263 /* LED */
 264
 265 #define CONFIG_SYS_LED_BASE     0xF9000000
 266 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_LED_BASE \
 267                                 | BR_PS_8 \
 268                                 | BR_MS_GPCM \
 269                                 | BR_V)
 270 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_2MB \
 271                                 | OR_GPCM_CSNT \
 272                                 | OR_GPCM_ACS_DIV2 \
 273                                 | OR_GPCM_XACS \
 274                                 | OR_GPCM_SCY_9 \
 275                                 | OR_GPCM_TRLX_SET \
 276                                 | OR_GPCM_EHTR_SET \
 277                                 | OR_GPCM_EAD)
 278
 279 /* Compact Flash */
 280
 281 #ifdef CONFIG_COMPACT_FLASH
 282
 283 #define CONFIG_SYS_CF_BASE      0xF0000000
 284
 285 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_CF_BASE \
 286                                 | BR_PS_16 \
 287                                 | BR_MS_UPMA \
 288                                 | BR_V)
 289 #define CONFIG_SYS_OR3_PRELIM   (OR_UPM_AM | OR_UPM_BI)
 290
 291 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CF_BASE
 292 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 293
 294 #endif
 295
 296 /*
 297  * U-Boot memory configuration
 298  */
 299 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 300
 301 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 302 #define CONFIG_SYS_RAMBOOT
 303 #else
 304 #undef  CONFIG_SYS_RAMBOOT
 305 #endif
 306
 307 #define CONFIG_SYS_INIT_RAM_LOCK
 308 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 309 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 310
 311 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 312                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 313 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 314
 315 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 316 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 317 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
 318
 319 /*
 320  * Local Bus LCRR and LBCR regs
 321  *    LCRR:  DLL bypass, Clock divider is 4
 322  * External Local Bus rate is
 323  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 324  */
 325 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 326 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 327 #define CONFIG_SYS_LBC_LBCR     0x00000000
 328
 329                                 /* LB sdram refresh timer, about 6us */
 330 #define CONFIG_SYS_LBC_LSRT     0x32000000
 331                                 /* LB refresh timer prescal, 266MHz/32*/
 332 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 333
 334 /*
 335  * Serial Port
 336  */
 337 #define CONFIG_SYS_NS16550_SERIAL
 338 #define CONFIG_SYS_NS16550_REG_SIZE     1
 339 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 340
 341 #define CONFIG_SYS_BAUDRATE_TABLE  \
 342                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 343
 344 #define CONSOLE                 ttyS0
 345
 346 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 347 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 348
 349 /*
 350  * PCI
 351  */
 352 #ifdef CONFIG_PCI
 353 #define CONFIG_PCI_INDIRECT_BRIDGE
 354
 355 #define CONFIG_MPC83XX_PCI2
 356
 357 /*
 358  * General PCI
 359  * Addresses are mapped 1-1.
 360  */
 361 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 362 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 363 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 364 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 365                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 366 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 367 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 368 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 369 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 370 #define CONFIG_SYS_PCI1_IO_SIZE         0x01000000      /* 16M */
 371
 372 #ifdef CONFIG_MPC83XX_PCI2
 373 #define CONFIG_SYS_PCI2_MEM_BASE        \
 374                         (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
 375 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 376 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 377 #define CONFIG_SYS_PCI2_MMIO_BASE       \
 378                         (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
 379 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 380 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 381 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 382 #define CONFIG_SYS_PCI2_IO_PHYS         \
 383                         (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
 384 #define CONFIG_SYS_PCI2_IO_SIZE         0x01000000      /* 16M */
 385 #endif
 386
 387 #ifndef CONFIG_PCI_PNP
 388     #define PCI_ENET0_IOADDR    0x00000000
 389     #define PCI_ENET0_MEMADDR   CONFIG_SYS_PCI2_MEM_BASE
 390     #define PCI_IDSEL_NUMBER    0x0f    /* IDSEL = AD15 */
 391 #endif
 392
 393 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 394
 395 #endif
 396
 397 #define CONFIG_PCI_66M
 398 #ifdef CONFIG_PCI_66M
 399 #define CONFIG_83XX_CLKIN       66666666        /* in Hz */
 400 #else
 401 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
 402 #endif
 403
 404 /* TSEC */
 405
 406 #ifdef CONFIG_TSEC_ENET
 407 #define CONFIG_TSEC1
 408
 409 #ifdef CONFIG_TSEC1
 410 #define CONFIG_HAS_ETH0
 411 #define CONFIG_TSEC1_NAME  "TSEC0"
 412 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 413 #define TSEC1_PHY_ADDR          0x1c    /* VSC8201 uses address 0x1c */
 414 #define TSEC1_PHYIDX            0
 415 #define TSEC1_FLAGS             TSEC_GIGABIT
 416 #endif
 417
 418 #ifdef CONFIG_TSEC2
 419 #define CONFIG_HAS_ETH1
 420 #define CONFIG_TSEC2_NAME  "TSEC1"
 421 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 422
 423 #define TSEC2_PHY_ADDR          4
 424 #define TSEC2_PHYIDX            0
 425 #define TSEC2_FLAGS             TSEC_GIGABIT
 426 #endif
 427
 428 #define CONFIG_ETHPRIME         "Freescale TSEC"
 429
 430 #endif
 431
 432 /*
 433  * Environment
 434  */
 435 #define CONFIG_ENV_OVERWRITE
 436
 437 #ifndef CONFIG_SYS_RAMBOOT
 438   #define CONFIG_ENV_ADDR       \
 439                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 440   #define CONFIG_ENV_SECT_SIZE  0x10000 /* 64K (one sector) for environment */
 441   #define CONFIG_ENV_SIZE       0x2000
 442 #else
 443   #define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE - 0x1000)
 444   #define CONFIG_ENV_SIZE       0x2000
 445 #endif
 446
 447 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 448 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 449
 450 /*
 451  * BOOTP options
 452  */
 453 #define CONFIG_BOOTP_BOOTFILESIZE
 454
 455 /* Watchdog */
 456 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 457
 458 /*
 459  * Miscellaneous configurable options
 460  */
 461
 462 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 463 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 464
 465 /*
 466  * For booting Linux, the board info and command line data
 467  * have to be in the first 256 MB of memory, since this is
 468  * the maximum mapped by the Linux kernel during initialization.
 469  */
 470                                 /* Initial Memory map for Linux*/
 471 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 472 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 473
 474 #define CONFIG_SYS_HRCW_LOW (\
 475         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 476         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 477         HRCWL_CSB_TO_CLKIN_4X1 |\
 478         HRCWL_VCO_1X2 |\
 479         HRCWL_CORE_TO_CSB_2X1)
 480
 481 #ifdef CONFIG_SYS_LOWBOOT
 482 #define CONFIG_SYS_HRCW_HIGH (\
 483         HRCWH_PCI_HOST |\
 484         HRCWH_32_BIT_PCI |\
 485         HRCWH_PCI1_ARBITER_ENABLE |\
 486         HRCWH_PCI2_ARBITER_ENABLE |\
 487         HRCWH_CORE_ENABLE |\
 488         HRCWH_FROM_0X00000100 |\
 489         HRCWH_BOOTSEQ_DISABLE |\
 490         HRCWH_SW_WATCHDOG_DISABLE |\
 491         HRCWH_ROM_LOC_LOCAL_16BIT |\
 492         HRCWH_TSEC1M_IN_GMII |\
 493         HRCWH_TSEC2M_IN_GMII)
 494 #else
 495 #define CONFIG_SYS_HRCW_HIGH (\
 496         HRCWH_PCI_HOST |\
 497         HRCWH_32_BIT_PCI |\
 498         HRCWH_PCI1_ARBITER_ENABLE |\
 499         HRCWH_PCI2_ARBITER_ENABLE |\
 500         HRCWH_CORE_ENABLE |\
 501         HRCWH_FROM_0XFFF00100 |\
 502         HRCWH_BOOTSEQ_DISABLE |\
 503         HRCWH_SW_WATCHDOG_DISABLE |\
 504         HRCWH_ROM_LOC_LOCAL_16BIT |\
 505         HRCWH_TSEC1M_IN_GMII |\
 506         HRCWH_TSEC2M_IN_GMII)
 507 #endif
 508
 509 /*
 510  * System performance
 511  */
 512 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 513 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 514 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 515 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 516 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 517 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 518 #define CONFIG_SYS_SCCR_USBMPHCM 3      /* USB MPH controller's clock */
 519 #define CONFIG_SYS_SCCR_USBDRCM 0       /* USB DR controller's clock */
 520
 521 /*
 522  * System IO Config
 523  */
 524 /* Needed for gigabit to work on TSEC 1 */
 525 #define CONFIG_SYS_SICRH SICRH_TSOBI1
 526                                 /* USB DR as device + USB MPH as host */
 527 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1)
 528
 529 #define CONFIG_SYS_HID0_INIT    0x00000000
 530 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_INSTRUCTION_CACHE
 531
 532 #define CONFIG_SYS_HID2 HID2_HBE
 533 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 534
 535 /* DDR  */
 536 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 537                                 | BATL_PP_RW \
 538                                 | BATL_MEMCOHERENCE)
 539 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 540                                 | BATU_BL_256M \
 541                                 | BATU_VS \
 542                                 | BATU_VP)
 543
 544 /* PCI  */
 545 #ifdef CONFIG_PCI
 546 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 547                                 | BATL_PP_RW \
 548                                 | BATL_MEMCOHERENCE)
 549 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 550                                 | BATU_BL_256M \
 551                                 | BATU_VS \
 552                                 | BATU_VP)
 553 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 554                                 | BATL_PP_RW \
 555                                 | BATL_CACHEINHIBIT \
 556                                 | BATL_GUARDEDSTORAGE)
 557 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 558                                 | BATU_BL_256M \
 559                                 | BATU_VS \
 560                                 | BATU_VP)
 561 #else
 562 #define CONFIG_SYS_IBAT1L       0
 563 #define CONFIG_SYS_IBAT1U       0
 564 #define CONFIG_SYS_IBAT2L       0
 565 #define CONFIG_SYS_IBAT2U       0
 566 #endif
 567
 568 #ifdef CONFIG_MPC83XX_PCI2
 569 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 570                                 | BATL_PP_RW \
 571                                 | BATL_MEMCOHERENCE)
 572 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 573                                 | BATU_BL_256M \
 574                                 | BATU_VS \
 575                                 | BATU_VP)
 576 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 577                                 | BATL_PP_RW \
 578                                 | BATL_CACHEINHIBIT \
 579                                 | BATL_GUARDEDSTORAGE)
 580 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 581                                 | BATU_BL_256M \
 582                                 | BATU_VS \
 583                                 | BATU_VP)
 584 #else
 585 #define CONFIG_SYS_IBAT3L       0
 586 #define CONFIG_SYS_IBAT3U       0
 587 #define CONFIG_SYS_IBAT4L       0
 588 #define CONFIG_SYS_IBAT4U       0
 589 #endif
 590
 591 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 592 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 593                                 | BATL_PP_RW \
 594                                 | BATL_CACHEINHIBIT \
 595                                 | BATL_GUARDEDSTORAGE)
 596 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 597                                 | BATU_BL_256M \
 598                                 | BATU_VS \
 599                                 | BATU_VP)
 600
 601 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 602 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 603                                 | BATL_PP_RW \
 604                                 | BATL_MEMCOHERENCE \
 605                                 | BATL_GUARDEDSTORAGE)
 606 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 607                                 | BATU_BL_256M \
 608                                 | BATU_VS \
 609                                 | BATU_VP)
 610
 611 #define CONFIG_SYS_IBAT7L       0
 612 #define CONFIG_SYS_IBAT7U       0
 613
 614 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 615 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 616 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 617 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 618 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 619 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 620 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 621 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 622 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 623 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 624 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 625 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 626 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 627 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 628 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 629 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 630
 631 #if defined(CONFIG_CMD_KGDB)
 632 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 633 #endif
 634
 635 /*
 636  * Environment Configuration
 637  */
 638 #define CONFIG_ENV_OVERWRITE
 639
 640 #define CONFIG_NETDEV           "eth0"
 641
 642 /* Default path and filenames */
 643 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 644 #define CONFIG_BOOTFILE         "uImage"
 645                                 /* U-Boot image on TFTP server */
 646 #define CONFIG_UBOOTPATH        "u-boot.bin"
 647
 648 #ifdef CONFIG_MPC8349ITX
 649 #define CONFIG_FDTFILE          "mpc8349emitx.dtb"
 650 #else
 651 #define CONFIG_FDTFILE          "mpc8349emitxgp.dtb"
 652 #endif
 653
 654
 655 #define CONFIG_EXTRA_ENV_SETTINGS \
 656         "console=" __stringify(CONSOLE) "\0"                    \
 657         "netdev=" CONFIG_NETDEV "\0"                                    \
 658         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 659         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 660                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 661                         " +$filesize; " \
 662                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 663                         " +$filesize; " \
 664                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 665                         " $filesize; "  \
 666                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 667                         " +$filesize; " \
 668                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 669                         " $filesize\0"  \
 670         "fdtaddr=780000\0"                                              \
 671         "fdtfile=" CONFIG_FDTFILE "\0"
 672
 673 #define CONFIG_NFSBOOTCOMMAND                                           \
 674         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"  \
 675         " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
 676         " console=$console,$baudrate $othbootargs; "                    \
 677         "tftp $loadaddr $bootfile;"                                     \
 678         "tftp $fdtaddr $fdtfile;"                                       \
 679         "bootm $loadaddr - $fdtaddr"
 680
 681 #define CONFIG_RAMBOOTCOMMAND                                           \
 682         "setenv bootargs root=/dev/ram rw"                              \
 683         " console=$console,$baudrate $othbootargs; "                    \
 684         "tftp $ramdiskaddr $ramdiskfile;"                               \
 685         "tftp $loadaddr $bootfile;"                                     \
 686         "tftp $fdtaddr $fdtfile;"                                       \
 687         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 688
 689 #endif