include/configs/MPC8349ITX.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  */
   5
   6 /*
   7  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
   8
   9  Memory map:
  10
  11  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  12  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  13  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  14  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  15  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  16  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  17  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  18  0xF001_0000-0xF001_FFFF Local bus expansion slot
  19  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  20  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  21  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  22
  23  I2C address list:
  24                                                 Align.  Board
  25  Bus    Addr    Part No.        Description     Length  Location
  26  ----------------------------------------------------------------
  27  I2C0   0x50    M24256-BWMN6P   Board EEPROM    2       U64
  28
  29  I2C1   0x20    PCF8574         I2C Expander    0       U8
  30  I2C1   0x21    PCF8574         I2C Expander    0       U10
  31  I2C1   0x38    PCF8574A        I2C Expander    0       U8
  32  I2C1   0x39    PCF8574A        I2C Expander    0       U10
  33  I2C1   0x51    (DDR)           DDR EEPROM      1       U1
  34  I2C1   0x68    DS1339          RTC             1       U68
  35
  36  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  37 */
  38
  39 #ifndef __CONFIG_H
  40 #define __CONFIG_H
  41
  42 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
  43 #define CONFIG_SYS_LOWBOOT
  44 #endif
  45
  46 /*
  47  * High Level Configuration Options
  48  */
  49 #define CONFIG_SYS_IMMR 0xE0000000      /* The IMMR is relocated to here */
  50
  51 #define CONFIG_MISC_INIT_F
  52
  53 /*
  54  * On-board devices
  55  */
  56
  57 #ifdef CONFIG_TARGET_MPC8349ITX
  58 /* The CF card interface on the back of the board */
  59 #define CONFIG_COMPACT_FLASH
  60 #define CONFIG_VSC7385_ENET     /* VSC7385 ethernet support */
  61 #define CONFIG_SYS_USB_HOST     /* use the EHCI USB controller */
  62 #endif
  63
  64 #define CONFIG_RTC_DS1337
  65 #define CONFIG_SYS_I2C
  66
  67 /*
  68  * Device configurations
  69  */
  70
  71 /* I2C */
  72 #ifdef CONFIG_SYS_I2C
  73 #define CONFIG_SYS_I2C_FSL
  74 #define CONFIG_SYS_FSL_I2C_SPEED        400000
  75 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  76 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
  77 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
  78 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
  79 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
  80
  81 #define CONFIG_SYS_SPD_BUS_NUM          1       /* The I2C bus for SPD */
  82 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC */
  83
  84 #define CONFIG_SYS_I2C_8574_ADDR1       0x20    /* I2C1, PCF8574 */
  85 #define CONFIG_SYS_I2C_8574_ADDR2       0x21    /* I2C1, PCF8574 */
  86 #define CONFIG_SYS_I2C_8574A_ADDR1      0x38    /* I2C1, PCF8574A */
  87 #define CONFIG_SYS_I2C_8574A_ADDR2      0x39    /* I2C1, PCF8574A */
  88 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C0, Board EEPROM */
  89 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* I2C1, DS1339 RTC*/
  90 #define SPD_EEPROM_ADDRESS              0x51    /* I2C1, DDR */
  91
  92 /* Don't probe these addresses: */
  93 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
  94                                  {1, CONFIG_SYS_I2C_8574_ADDR2}, \
  95                                  {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
  96                                  {1, CONFIG_SYS_I2C_8574A_ADDR2} }
  97 /* Bit definitions for the 8574[A] I2C expander */
  98                                 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
  99 #define I2C_8574_REVISION       0x03
 100 #define I2C_8574_CF             0x08    /* 1=Compact flash absent, 0=present */
 101 #define I2C_8574_MPCICLKRN      0x10    /* MiniPCI Clk Run */
 102 #define I2C_8574_PCI66          0x20    /* 0=33MHz PCI, 1=66MHz PCI */
 103 #define I2C_8574_FLASHSIDE      0x40    /* 0=Reset vector from U4, 1=from U7*/
 104
 105 #endif
 106
 107 /* Compact Flash */
 108 #ifdef CONFIG_COMPACT_FLASH
 109
 110 #define CONFIG_SYS_IDE_MAXBUS           1
 111 #define CONFIG_SYS_IDE_MAXDEVICE        1
 112
 113 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 114 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF_BASE
 115 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000
 116 #define CONFIG_SYS_ATA_REG_OFFSET       0
 117 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0200
 118 #define CONFIG_SYS_ATA_STRIDE           2
 119
 120 /* If a CF card is not inserted, time out quickly */
 121 #define ATA_RESET_TIME  1
 122
 123 #endif
 124
 125 /*
 126  * SATA
 127  */
 128 #ifdef CONFIG_SATA_SIL3114
 129
 130 #define CONFIG_SYS_SATA_MAX_DEVICE      4
 131 #define CONFIG_LBA48
 132
 133 #endif
 134
 135 #ifdef CONFIG_SYS_USB_HOST
 136 /*
 137  * Support USB
 138  */
 139 #define CONFIG_USB_EHCI_FSL
 140
 141 /* Current USB implementation supports the only USB controller,
 142  * so we have to choose between the MPH or the DR ones */
 143 #if 1
 144 #define CONFIG_HAS_FSL_MPH_USB
 145 #else
 146 #define CONFIG_HAS_FSL_DR_USB
 147 #endif
 148
 149 #endif
 150
 151 /*
 152  * DDR Setup
 153  */
 154 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 155 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 156 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 157 #define CONFIG_SYS_83XX_DDR_USES_CS0
 158 #define CONFIG_SYS_MEMTEST_START        0x1000  /* memtest region */
 159 #define CONFIG_SYS_MEMTEST_END          0x2000
 160
 161 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 162                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 163
 164 #define CONFIG_VERY_BIG_RAM
 165 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
 166
 167 #ifdef CONFIG_SYS_I2C
 168 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
 169 #endif
 170
 171 /* No SPD? Then manually set up DDR parameters */
 172 #ifndef CONFIG_SPD_EEPROM
 173     #define CONFIG_SYS_DDR_SIZE         256     /* Mb */
 174     #define CONFIG_SYS_DDR_CS0_CONFIG   (CSCONFIG_EN \
 175                                         | CSCONFIG_ROW_BIT_13 \
 176                                         | CSCONFIG_COL_BIT_10)
 177
 178     #define CONFIG_SYS_DDR_TIMING_1     0x26242321
 179     #define CONFIG_SYS_DDR_TIMING_2     0x00000800  /* P9-45, may need tuning */
 180 #endif
 181
 182 /*
 183  *Flash on the Local Bus
 184  */
 185
 186 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 187 #define CONFIG_SYS_FLASH_EMPTY_INFO
 188 /* 127 64KB sectors + 8 8KB sectors per device */
 189 #define CONFIG_SYS_MAX_FLASH_SECT       135
 190 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 191 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 192 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 193
 194 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 195 boards, we say we have two, but don't display a message if we find only one. */
 196 #define CONFIG_SYS_FLASH_QUIET_TEST
 197 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 198 #define CONFIG_SYS_FLASH_BANKS_LIST     \
 199                 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
 200 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size in MB */
 201
 202 /* Vitesse 7385 */
 203
 204 #ifdef CONFIG_VSC7385_ENET
 205
 206 #define CONFIG_TSEC2
 207
 208 /* The flash address and size of the VSC7385 firmware image */
 209 #define CONFIG_VSC7385_IMAGE            0xFEFFE000
 210 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 211
 212 #endif
 213
 214 /*
 215  * BRx, ORx, LBLAWBARx, and LBLAWARx
 216  */
 217
 218 /* Flash */
 219
 220 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 221                                 | BR_PS_16 \
 222                                 | BR_MS_GPCM \
 223                                 | BR_V)
 224 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 225                                 | OR_UPM_XAM \
 226                                 | OR_GPCM_CSNT \
 227                                 | OR_GPCM_ACS_DIV2 \
 228                                 | OR_GPCM_XACS \
 229                                 | OR_GPCM_SCY_15 \
 230                                 | OR_GPCM_TRLX_SET \
 231                                 | OR_GPCM_EHTR_SET \
 232                                 | OR_GPCM_EAD)
 233 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 234 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 235
 236 /* Vitesse 7385 */
 237
 238 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
 239
 240 #ifdef CONFIG_VSC7385_ENET
 241
 242 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_VSC7385_BASE \
 243                                 | BR_PS_8 \
 244                                 | BR_MS_GPCM \
 245                                 | BR_V)
 246 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128KB \
 247                                 | OR_GPCM_CSNT \
 248                                 | OR_GPCM_XACS \
 249                                 | OR_GPCM_SCY_15 \
 250                                 | OR_GPCM_SETA \
 251                                 | OR_GPCM_TRLX_SET \
 252                                 | OR_GPCM_EHTR_SET \
 253                                 | OR_GPCM_EAD)
 254
 255 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_VSC7385_BASE
 256 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 257
 258 #endif
 259
 260 /* LED */
 261
 262 #define CONFIG_SYS_LED_BASE     0xF9000000
 263 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_LED_BASE \
 264                                 | BR_PS_8 \
 265                                 | BR_MS_GPCM \
 266                                 | BR_V)
 267 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_2MB \
 268                                 | OR_GPCM_CSNT \
 269                                 | OR_GPCM_ACS_DIV2 \
 270                                 | OR_GPCM_XACS \
 271                                 | OR_GPCM_SCY_9 \
 272                                 | OR_GPCM_TRLX_SET \
 273                                 | OR_GPCM_EHTR_SET \
 274                                 | OR_GPCM_EAD)
 275
 276 /* Compact Flash */
 277
 278 #ifdef CONFIG_COMPACT_FLASH
 279
 280 #define CONFIG_SYS_CF_BASE      0xF0000000
 281
 282 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_CF_BASE \
 283                                 | BR_PS_16 \
 284                                 | BR_MS_UPMA \
 285                                 | BR_V)
 286 #define CONFIG_SYS_OR3_PRELIM   (OR_UPM_AM | OR_UPM_BI)
 287
 288 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CF_BASE
 289 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 290
 291 #endif
 292
 293 /*
 294  * U-Boot memory configuration
 295  */
 296 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 297
 298 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 299 #define CONFIG_SYS_RAMBOOT
 300 #else
 301 #undef  CONFIG_SYS_RAMBOOT
 302 #endif
 303
 304 #define CONFIG_SYS_INIT_RAM_LOCK
 305 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 306 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 307
 308 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 309                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 310 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 311
 312 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 313 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 314 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
 315
 316 /*
 317  * Local Bus LCRR and LBCR regs
 318  *    LCRR:  DLL bypass, Clock divider is 4
 319  * External Local Bus rate is
 320  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 321  */
 322 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 323 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 324 #define CONFIG_SYS_LBC_LBCR     0x00000000
 325
 326                                 /* LB sdram refresh timer, about 6us */
 327 #define CONFIG_SYS_LBC_LSRT     0x32000000
 328                                 /* LB refresh timer prescal, 266MHz/32*/
 329 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 330
 331 /*
 332  * Serial Port
 333  */
 334 #define CONFIG_SYS_NS16550_SERIAL
 335 #define CONFIG_SYS_NS16550_REG_SIZE     1
 336 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 337
 338 #define CONFIG_SYS_BAUDRATE_TABLE  \
 339                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 340
 341 #define CONSOLE                 ttyS0
 342
 343 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 344 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 345
 346 /*
 347  * PCI
 348  */
 349 #ifdef CONFIG_PCI
 350 #define CONFIG_PCI_INDIRECT_BRIDGE
 351
 352 #define CONFIG_MPC83XX_PCI2
 353
 354 /*
 355  * General PCI
 356  * Addresses are mapped 1-1.
 357  */
 358 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 359 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 360 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 361 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 362                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 363 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 364 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 365 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 366 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 367 #define CONFIG_SYS_PCI1_IO_SIZE         0x01000000      /* 16M */
 368
 369 #ifdef CONFIG_MPC83XX_PCI2
 370 #define CONFIG_SYS_PCI2_MEM_BASE        \
 371                         (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
 372 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 373 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 374 #define CONFIG_SYS_PCI2_MMIO_BASE       \
 375                         (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
 376 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 377 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 378 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 379 #define CONFIG_SYS_PCI2_IO_PHYS         \
 380                         (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
 381 #define CONFIG_SYS_PCI2_IO_SIZE         0x01000000      /* 16M */
 382 #endif
 383
 384 #ifndef CONFIG_PCI_PNP
 385     #define PCI_ENET0_IOADDR    0x00000000
 386     #define PCI_ENET0_MEMADDR   CONFIG_SYS_PCI2_MEM_BASE
 387     #define PCI_IDSEL_NUMBER    0x0f    /* IDSEL = AD15 */
 388 #endif
 389
 390 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 391
 392 #endif
 393
 394 /* TSEC */
 395
 396 #ifdef CONFIG_TSEC_ENET
 397 #define CONFIG_TSEC1
 398
 399 #ifdef CONFIG_TSEC1
 400 #define CONFIG_HAS_ETH0
 401 #define CONFIG_TSEC1_NAME  "TSEC0"
 402 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 403 #define TSEC1_PHY_ADDR          0x1c    /* VSC8201 uses address 0x1c */
 404 #define TSEC1_PHYIDX            0
 405 #define TSEC1_FLAGS             TSEC_GIGABIT
 406 #endif
 407
 408 #ifdef CONFIG_TSEC2
 409 #define CONFIG_HAS_ETH1
 410 #define CONFIG_TSEC2_NAME  "TSEC1"
 411 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 412
 413 #define TSEC2_PHY_ADDR          4
 414 #define TSEC2_PHYIDX            0
 415 #define TSEC2_FLAGS             TSEC_GIGABIT
 416 #endif
 417
 418 #define CONFIG_ETHPRIME         "Freescale TSEC"
 419
 420 #endif
 421
 422 /*
 423  * Environment
 424  */
 425 #define CONFIG_ENV_OVERWRITE
 426
 427 #ifndef CONFIG_SYS_RAMBOOT
 428   #define CONFIG_ENV_ADDR       \
 429                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 430   #define CONFIG_ENV_SECT_SIZE  0x10000 /* 64K (one sector) for environment */
 431   #define CONFIG_ENV_SIZE       0x2000
 432 #else
 433   #define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE - 0x1000)
 434   #define CONFIG_ENV_SIZE       0x2000
 435 #endif
 436
 437 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 438 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 439
 440 /*
 441  * BOOTP options
 442  */
 443 #define CONFIG_BOOTP_BOOTFILESIZE
 444
 445 /* Watchdog */
 446 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 447
 448 /*
 449  * Miscellaneous configurable options
 450  */
 451
 452 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 453 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 454
 455 /*
 456  * For booting Linux, the board info and command line data
 457  * have to be in the first 256 MB of memory, since this is
 458  * the maximum mapped by the Linux kernel during initialization.
 459  */
 460                                 /* Initial Memory map for Linux*/
 461 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 462 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 463
 464 #define CONFIG_SYS_HRCW_LOW (\
 465         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 466         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 467         HRCWL_CSB_TO_CLKIN_4X1 |\
 468         HRCWL_VCO_1X2 |\
 469         HRCWL_CORE_TO_CSB_2X1)
 470
 471 #ifdef CONFIG_SYS_LOWBOOT
 472 #define CONFIG_SYS_HRCW_HIGH (\
 473         HRCWH_PCI_HOST |\
 474         HRCWH_32_BIT_PCI |\
 475         HRCWH_PCI1_ARBITER_ENABLE |\
 476         HRCWH_PCI2_ARBITER_ENABLE |\
 477         HRCWH_CORE_ENABLE |\
 478         HRCWH_FROM_0X00000100 |\
 479         HRCWH_BOOTSEQ_DISABLE |\
 480         HRCWH_SW_WATCHDOG_DISABLE |\
 481         HRCWH_ROM_LOC_LOCAL_16BIT |\
 482         HRCWH_TSEC1M_IN_GMII |\
 483         HRCWH_TSEC2M_IN_GMII)
 484 #else
 485 #define CONFIG_SYS_HRCW_HIGH (\
 486         HRCWH_PCI_HOST |\
 487         HRCWH_32_BIT_PCI |\
 488         HRCWH_PCI1_ARBITER_ENABLE |\
 489         HRCWH_PCI2_ARBITER_ENABLE |\
 490         HRCWH_CORE_ENABLE |\
 491         HRCWH_FROM_0XFFF00100 |\
 492         HRCWH_BOOTSEQ_DISABLE |\
 493         HRCWH_SW_WATCHDOG_DISABLE |\
 494         HRCWH_ROM_LOC_LOCAL_16BIT |\
 495         HRCWH_TSEC1M_IN_GMII |\
 496         HRCWH_TSEC2M_IN_GMII)
 497 #endif
 498
 499 /*
 500  * System performance
 501  */
 502 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 503 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 504 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 505 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 506 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 507 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 508 #define CONFIG_SYS_SCCR_USBMPHCM 3      /* USB MPH controller's clock */
 509 #define CONFIG_SYS_SCCR_USBDRCM 0       /* USB DR controller's clock */
 510
 511 /*
 512  * System IO Config
 513  */
 514 /* Needed for gigabit to work on TSEC 1 */
 515 #define CONFIG_SYS_SICRH SICRH_TSOBI1
 516                                 /* USB DR as device + USB MPH as host */
 517 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1)
 518
 519 #define CONFIG_SYS_HID0_INIT    0x00000000
 520 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_INSTRUCTION_CACHE
 521
 522 #define CONFIG_SYS_HID2 HID2_HBE
 523 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 524
 525 /* DDR  */
 526 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 527                                 | BATL_PP_RW \
 528                                 | BATL_MEMCOHERENCE)
 529 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 530                                 | BATU_BL_256M \
 531                                 | BATU_VS \
 532                                 | BATU_VP)
 533
 534 /* PCI  */
 535 #ifdef CONFIG_PCI
 536 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 537                                 | BATL_PP_RW \
 538                                 | BATL_MEMCOHERENCE)
 539 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 540                                 | BATU_BL_256M \
 541                                 | BATU_VS \
 542                                 | BATU_VP)
 543 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 544                                 | BATL_PP_RW \
 545                                 | BATL_CACHEINHIBIT \
 546                                 | BATL_GUARDEDSTORAGE)
 547 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 548                                 | BATU_BL_256M \
 549                                 | BATU_VS \
 550                                 | BATU_VP)
 551 #else
 552 #define CONFIG_SYS_IBAT1L       0
 553 #define CONFIG_SYS_IBAT1U       0
 554 #define CONFIG_SYS_IBAT2L       0
 555 #define CONFIG_SYS_IBAT2U       0
 556 #endif
 557
 558 #ifdef CONFIG_MPC83XX_PCI2
 559 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 560                                 | BATL_PP_RW \
 561                                 | BATL_MEMCOHERENCE)
 562 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 563                                 | BATU_BL_256M \
 564                                 | BATU_VS \
 565                                 | BATU_VP)
 566 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 567                                 | BATL_PP_RW \
 568                                 | BATL_CACHEINHIBIT \
 569                                 | BATL_GUARDEDSTORAGE)
 570 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 571                                 | BATU_BL_256M \
 572                                 | BATU_VS \
 573                                 | BATU_VP)
 574 #else
 575 #define CONFIG_SYS_IBAT3L       0
 576 #define CONFIG_SYS_IBAT3U       0
 577 #define CONFIG_SYS_IBAT4L       0
 578 #define CONFIG_SYS_IBAT4U       0
 579 #endif
 580
 581 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 582 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 583                                 | BATL_PP_RW \
 584                                 | BATL_CACHEINHIBIT \
 585                                 | BATL_GUARDEDSTORAGE)
 586 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 587                                 | BATU_BL_256M \
 588                                 | BATU_VS \
 589                                 | BATU_VP)
 590
 591 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 592 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 593                                 | BATL_PP_RW \
 594                                 | BATL_MEMCOHERENCE \
 595                                 | BATL_GUARDEDSTORAGE)
 596 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 597                                 | BATU_BL_256M \
 598                                 | BATU_VS \
 599                                 | BATU_VP)
 600
 601 #define CONFIG_SYS_IBAT7L       0
 602 #define CONFIG_SYS_IBAT7U       0
 603
 604 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 605 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 606 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 607 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 608 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 609 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 610 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 611 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 612 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 613 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 614 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 615 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 616 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 617 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 618 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 619 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 620
 621 #if defined(CONFIG_CMD_KGDB)
 622 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 623 #endif
 624
 625 /*
 626  * Environment Configuration
 627  */
 628 #define CONFIG_ENV_OVERWRITE
 629
 630 #define CONFIG_NETDEV           "eth0"
 631
 632 /* Default path and filenames */
 633 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 634 #define CONFIG_BOOTFILE         "uImage"
 635                                 /* U-Boot image on TFTP server */
 636 #define CONFIG_UBOOTPATH        "u-boot.bin"
 637
 638 #ifdef CONFIG_TARGET_MPC8349ITX
 639 #define CONFIG_FDTFILE          "mpc8349emitx.dtb"
 640 #else
 641 #define CONFIG_FDTFILE          "mpc8349emitxgp.dtb"
 642 #endif
 643
 644
 645 #define CONFIG_EXTRA_ENV_SETTINGS \
 646         "console=" __stringify(CONSOLE) "\0"                    \
 647         "netdev=" CONFIG_NETDEV "\0"                                    \
 648         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 649         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 650                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 651                         " +$filesize; " \
 652                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 653                         " +$filesize; " \
 654                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 655                         " $filesize; "  \
 656                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 657                         " +$filesize; " \
 658                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 659                         " $filesize\0"  \
 660         "fdtaddr=780000\0"                                              \
 661         "fdtfile=" CONFIG_FDTFILE "\0"
 662
 663 #define CONFIG_NFSBOOTCOMMAND                                           \
 664         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"  \
 665         " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
 666         " console=$console,$baudrate $othbootargs; "                    \
 667         "tftp $loadaddr $bootfile;"                                     \
 668         "tftp $fdtaddr $fdtfile;"                                       \
 669         "bootm $loadaddr - $fdtaddr"
 670
 671 #define CONFIG_RAMBOOTCOMMAND                                           \
 672         "setenv bootargs root=/dev/ram rw"                              \
 673         " console=$console,$baudrate $othbootargs; "                    \
 674         "tftp $ramdiskaddr $ramdiskfile;"                               \
 675         "tftp $loadaddr $bootfile;"                                     \
 676         "tftp $fdtaddr $fdtfile;"                                       \
 677         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 678
 679 #endif