include/configs/MPC8360EMDS.h

   1 /*
   2  * Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1 /* E300 family */
  16 #define CONFIG_QE               1 /* Has QE */
  17 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  18 #define CONFIG_MPC8360EMDS      1 /* MPC8360EMDS board specific */
  19
  20 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  21
  22 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
  23 #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
  24
  25 /*
  26  * System Clock Setup
  27  */
  28 #ifdef CONFIG_CLKIN_33MHZ
  29 #ifdef CONFIG_PCISLAVE
  30 #define CONFIG_83XX_PCICLK      33330000 /* in HZ */
  31 #else
  32 #define CONFIG_83XX_CLKIN       33330000 /* in Hz */
  33 #endif
  34
  35 #ifndef CONFIG_SYS_CLK_FREQ
  36 #define CONFIG_SYS_CLK_FREQ     33330000
  37 #endif
  38
  39 #elif defined(CONFIG_CLKIN_66MHZ)
  40 #ifdef CONFIG_PCISLAVE
  41 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
  42 #else
  43 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
  44 #endif
  45
  46 #ifndef CONFIG_SYS_CLK_FREQ
  47 #define CONFIG_SYS_CLK_FREQ     66000000
  48 #endif
  49 #else
  50 #error Unknown oscillator frequency.
  51 #endif
  52
  53 /*
  54  * Hardware Reset Configuration Word
  55  */
  56 #ifdef CONFIG_CLKIN_33MHZ
  57 #define CONFIG_SYS_HRCW_LOW (\
  58         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  59         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  60         HRCWL_CSB_TO_CLKIN_8X1 |\
  61         HRCWL_VCO_1X2 |\
  62         HRCWL_CE_PLL_VCO_DIV_4 |\
  63         HRCWL_CE_PLL_DIV_1X1 |\
  64         HRCWL_CE_TO_PLL_1X15 |\
  65         HRCWL_CORE_TO_CSB_2X1)
  66 #elif defined(CONFIG_CLKIN_66MHZ)
  67 #define CONFIG_SYS_HRCW_LOW (\
  68         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  69         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  70         HRCWL_CSB_TO_CLKIN_4X1 |\
  71         HRCWL_VCO_1X2 |\
  72         HRCWL_CE_PLL_VCO_DIV_4 |\
  73         HRCWL_CE_PLL_DIV_1X1 |\
  74         HRCWL_CE_TO_PLL_1X6 |\
  75         HRCWL_CORE_TO_CSB_2X1)
  76 #endif
  77
  78 #ifdef CONFIG_PCISLAVE
  79 #define CONFIG_SYS_HRCW_HIGH (\
  80         HRCWH_PCI_AGENT |\
  81         HRCWH_PCI1_ARBITER_DISABLE |\
  82         HRCWH_PCICKDRV_DISABLE |\
  83         HRCWH_CORE_ENABLE |\
  84         HRCWH_FROM_0XFFF00100 |\
  85         HRCWH_BOOTSEQ_DISABLE |\
  86         HRCWH_SW_WATCHDOG_DISABLE |\
  87         HRCWH_ROM_LOC_LOCAL_16BIT)
  88 #else
  89 #define CONFIG_SYS_HRCW_HIGH (\
  90         HRCWH_PCI_HOST |\
  91         HRCWH_PCI1_ARBITER_ENABLE |\
  92         HRCWH_PCICKDRV_ENABLE |\
  93         HRCWH_CORE_ENABLE |\
  94         HRCWH_FROM_0X00000100 |\
  95         HRCWH_BOOTSEQ_DISABLE |\
  96         HRCWH_SW_WATCHDOG_DISABLE |\
  97         HRCWH_ROM_LOC_LOCAL_16BIT)
  98 #endif
  99
 100 /*
 101  * System IO Config
 102  */
 103 #define CONFIG_SYS_SICRH                0x00000000
 104 #define CONFIG_SYS_SICRL                0x40000000
 105
 106 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 107 #define CONFIG_BOARD_EARLY_INIT_R
 108
 109 /*
 110  * IMMR new address
 111  */
 112 #define CONFIG_SYS_IMMR         0xE0000000
 113
 114 /*
 115  * DDR Setup
 116  */
 117 #define CONFIG_SYS_DDR_BASE     0x00000000 /* DDR is system memory */
 118 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
 119                                 /* + 256M */
 120 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 121 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 122 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 123                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 124
 125 #define CONFIG_SYS_83XX_DDR_USES_CS0
 126
 127 #define CONFIG_DDR_ECC          /* support DDR ECC function */
 128 #define CONFIG_DDR_ECC_CMD      /* Use DDR ECC user commands */
 129
 130 /*
 131  * DDRCDR - DDR Control Driver Register
 132  */
 133 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 134
 135 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 136 #if defined(CONFIG_SPD_EEPROM)
 137 /*
 138  * Determine DDR configuration from I2C interface.
 139  */
 140 #define SPD_EEPROM_ADDRESS      0x52 /* DDR SODIMM */
 141 #else
 142 /*
 143  * Manually set up DDR parameters
 144  */
 145 #define CONFIG_SYS_DDR_SIZE             256 /* MB */
 146 #if defined(CONFIG_DDR_II)
 147 #define CONFIG_SYS_DDRCDR               0x80080001
 148 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
 149 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80330102
 150 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
 151 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
 152 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
 153 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 154 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
 155 #define CONFIG_SYS_DDR_MODE             0x47d00432
 156 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 157 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
 158 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 159 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 160 #else
 161 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 162                                         | CSCONFIG_ROW_BIT_13 \
 163                                         | CSCONFIG_COL_BIT_9)
 164 #define CONFIG_SYS_DDR_CS1_CONFIG       CONFIG_SYS_DDR_CS0_CONFIG
 165 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
 166 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
 167 #define CONFIG_SYS_DDR_CONTROL  0x42008000 /* Self refresh,2T timing */
 168 #define CONFIG_SYS_DDR_MODE     0x20000162 /* DLL,normal,seq,4/2.5 */
 169 #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
 170 #endif
 171 #endif
 172
 173 /*
 174  * Memory test
 175  */
 176 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 177 #define CONFIG_SYS_MEMTEST_START        0x00000000 /* memtest region */
 178 #define CONFIG_SYS_MEMTEST_END          0x00100000
 179
 180 /*
 181  * The reserved memory
 182  */
 183
 184 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 185
 186 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 187 #define CONFIG_SYS_RAMBOOT
 188 #else
 189 #undef  CONFIG_SYS_RAMBOOT
 190 #endif
 191
 192 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 193 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 194 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
 195
 196 /*
 197  * Initial RAM Base Address Setup
 198  */
 199 #define CONFIG_SYS_INIT_RAM_LOCK        1
 200 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 201 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 202 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 203                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 204
 205 /*
 206  * Local Bus Configuration & Clock Setup
 207  */
 208 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 209 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 210 #define CONFIG_SYS_LBC_LBCR     0x00000000
 211
 212 /*
 213  * FLASH on the Local Bus
 214  */
 215 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 216 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 217 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 218 #define CONFIG_SYS_FLASH_SIZE           32 /* max FLASH size is 32M */
 219 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 220 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 221
 222                                         /* Window base at flash base */
 223 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 224 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 225
 226 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 227                                 | BR_PS_16      /* 16 bit port */ \
 228                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 229                                 | BR_V)         /* valid */
 230 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 231                                 | OR_GPCM_XAM \
 232                                 | OR_GPCM_CSNT \
 233                                 | OR_GPCM_ACS_DIV2 \
 234                                 | OR_GPCM_XACS \
 235                                 | OR_GPCM_SCY_15 \
 236                                 | OR_GPCM_TRLX_SET \
 237                                 | OR_GPCM_EHTR_SET \
 238                                 | OR_GPCM_EAD)
 239
 240 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 241 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 242
 243 #undef  CONFIG_SYS_FLASH_CHECKSUM
 244
 245 /*
 246  * BCSR on the Local Bus
 247  */
 248 #define CONFIG_SYS_BCSR                 0xF8000000
 249                                         /* Access window base at BCSR base */
 250 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 251 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 252
 253 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_BCSR \
 254                                 | BR_PS_8 \
 255                                 | BR_MS_GPCM \
 256                                 | BR_V)
 257 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 258                                 | OR_GPCM_XAM \
 259                                 | OR_GPCM_CSNT \
 260                                 | OR_GPCM_XACS \
 261                                 | OR_GPCM_SCY_15 \
 262                                 | OR_GPCM_TRLX_SET \
 263                                 | OR_GPCM_EHTR_SET \
 264                                 | OR_GPCM_EAD)
 265                                 /* 0xFFFFE9F7 */
 266
 267 /*
 268  * SDRAM on the Local Bus
 269  */
 270 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* SDRAM base address */
 271 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 272
 273 #define CONFIG_SYS_LB_SDRAM             /* if board has SRDAM on local bus */
 274
 275 #ifdef CONFIG_SYS_LB_SDRAM
 276 #define CONFIG_SYS_LBLAWBAR2            0
 277 #define CONFIG_SYS_LBLAWAR2             (LBLAWAR_EN | LBLAWAR_64MB)
 278
 279 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 280 /*
 281  * Base Register 2 and Option Register 2 configure SDRAM.
 282  *
 283  * For BR2, need:
 284  *    Base address = BR[0:16] = dynamic
 285  *    port size = 32-bits = BR2[19:20] = 11
 286  *    no parity checking = BR2[21:22] = 00
 287  *    SDRAM for MSEL = BR2[24:26] = 011
 288  *    Valid = BR[31] = 1
 289  *
 290  * 0    4    8    12   16   20   24   28
 291  * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
 292  */
 293
 294 /* Port size=32bit, MSEL=DRAM */
 295 #define CONFIG_SYS_BR2  (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */
 296
 297 /*
 298  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 299  *
 300  * For OR2, need:
 301  *    64MB mask for AM, OR2[0:7] = 1111 1100
 302  *                 XAM, OR2[17:18] = 11
 303  *    9 columns OR2[19-21] = 010
 304  *    13 rows   OR2[23-25] = 100
 305  *    EAD set for extra time OR[31] = 1
 306  *
 307  * 0    4    8    12   16   20   24   28
 308  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 309  */
 310
 311 #define CONFIG_SYS_OR2  (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
 312                         | OR_SDRAM_XAM \
 313                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 314                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 315                         | OR_SDRAM_EAD)
 316                         /* 0xFC006901 */
 317
 318                                 /* LB sdram refresh timer, about 6us */
 319 #define CONFIG_SYS_LBC_LSRT     0x32000000
 320                                 /* LB refresh timer prescal, 266MHz/32 */
 321 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 322
 323 #define CONFIG_SYS_LBC_LSDMR_COMMON     0x0063b723
 324
 325 /*
 326  * SDRAM Controller configuration sequence.
 327  */
 328 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 329 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 330 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 331 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 332 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 333
 334 #endif
 335
 336 /*
 337  * Windows to access Platform I/O Boards (PIB) via local bus
 338  */
 339 #define CONFIG_SYS_PIB_BASE             0xF8008000
 340 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
 341
 342 /* [RFC] This LBLAW only covers the 2nd window (CS5) */
 343 #define CONFIG_SYS_LBLAWBAR3_PRELIM     \
 344                         CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE
 345 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 346
 347 /*
 348  * CS4 on Local Bus, to PIB
 349  */
 350                                 /* CS4 base address at 0xf8008000 */
 351 #define CONFIG_SYS_BR4_PRELIM   (CONFIG_SYS_PIB_BASE \
 352                                 | BR_PS_8 \
 353                                 | BR_MS_GPCM \
 354                                 | BR_V)
 355                                 /* 0xF8008801 */
 356 #define CONFIG_SYS_OR4_PRELIM   (OR_AM_32KB \
 357                                 | OR_GPCM_XAM \
 358                                 | OR_GPCM_CSNT \
 359                                 | OR_GPCM_XACS \
 360                                 | OR_GPCM_SCY_15 \
 361                                 | OR_GPCM_TRLX_SET \
 362                                 | OR_GPCM_EHTR_SET \
 363                                 | OR_GPCM_EAD)
 364                                 /* 0xffffe9f7 */
 365
 366 /*
 367  * CS5 on Local Bus, to PIB
 368  */
 369                                 /* CS5 base address at 0xf8010000 */
 370 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_PIB_BASE + \
 371                                                 CONFIG_SYS_PIB_WINDOW_SIZE) \
 372                                 | BR_PS_8 \
 373                                 | BR_MS_GPCM \
 374                                 | BR_V)
 375                                 /* 0xF8010801 */
 376 #define CONFIG_SYS_OR5_PRELIM   (CONFIG_SYS_PIB_BASE \
 377                                 | OR_GPCM_XAM \
 378                                 | OR_GPCM_CSNT \
 379                                 | OR_GPCM_XACS \
 380                                 | OR_GPCM_SCY_15 \
 381                                 | OR_GPCM_TRLX_SET \
 382                                 | OR_GPCM_EHTR_SET \
 383                                 | OR_GPCM_EAD)
 384                                 /* 0xffffe9f7 */
 385
 386 /*
 387  * Serial Port
 388  */
 389 #define CONFIG_CONS_INDEX       1
 390 #define CONFIG_SYS_NS16550
 391 #define CONFIG_SYS_NS16550_SERIAL
 392 #define CONFIG_SYS_NS16550_REG_SIZE     1
 393 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 394
 395 #define CONFIG_SYS_BAUDRATE_TABLE  \
 396                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 397
 398 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 399 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 400
 401 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 402 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 403 /* Use the HUSH parser */
 404 #define CONFIG_SYS_HUSH_PARSER
 405
 406 /* pass open firmware flat tree */
 407 #define CONFIG_OF_LIBFDT        1
 408 #define CONFIG_OF_BOARD_SETUP   1
 409 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 410
 411 /* I2C */
 412 #define CONFIG_SYS_I2C
 413 #define CONFIG_SYS_I2C_FSL
 414 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 415 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 416 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 417 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x52} }
 418
 419 /*
 420  * Config on-board RTC
 421  */
 422 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 423 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 424
 425 /*
 426  * General PCI
 427  * Addresses are mapped 1-1.
 428  */
 429 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 430 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 431 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000 /* 256M */
 432 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 433 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 434 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000 /* 256M */
 435 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 436 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 437 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000 /* 1M */
 438
 439 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 440 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 441 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 442
 443
 444 #ifdef CONFIG_PCI
 445 #define CONFIG_PCI_INDIRECT_BRIDGE
 446
 447 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 448 #define CONFIG_83XX_PCI_STREAMING
 449
 450 #undef CONFIG_EEPRO100
 451 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 452 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 453
 454 #endif  /* CONFIG_PCI */
 455
 456
 457 #define CONFIG_HWCONFIG         1
 458
 459 /*
 460  * QE UEC ethernet configuration
 461  */
 462 #define CONFIG_UEC_ETH
 463 #define CONFIG_ETHPRIME         "UEC0"
 464 #define CONFIG_PHY_MODE_NEED_CHANGE
 465
 466 #define CONFIG_UEC_ETH1         /* GETH1 */
 467
 468 #ifdef CONFIG_UEC_ETH1
 469 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 470 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE
 471 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK9
 472 #define CONFIG_SYS_UEC1_ETH_TYPE        GIGA_ETH
 473 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 474 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 475 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 476 #endif
 477
 478 #define CONFIG_UEC_ETH2         /* GETH2 */
 479
 480 #ifdef CONFIG_UEC_ETH2
 481 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 482 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE
 483 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK4
 484 #define CONFIG_SYS_UEC2_ETH_TYPE        GIGA_ETH
 485 #define CONFIG_SYS_UEC2_PHY_ADDR        1
 486 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 487 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 488 #endif
 489
 490 /*
 491  * Environment
 492  */
 493
 494 #ifndef CONFIG_SYS_RAMBOOT
 495         #define CONFIG_ENV_IS_IN_FLASH  1
 496         #define CONFIG_ENV_ADDR         \
 497                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 498         #define CONFIG_ENV_SECT_SIZE    0x20000
 499         #define CONFIG_ENV_SIZE         0x2000
 500 #else
 501         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 502         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 503         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 504         #define CONFIG_ENV_SIZE         0x2000
 505 #endif
 506
 507 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 508 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 509
 510 /*
 511  * BOOTP options
 512  */
 513 #define CONFIG_BOOTP_BOOTFILESIZE
 514 #define CONFIG_BOOTP_BOOTPATH
 515 #define CONFIG_BOOTP_GATEWAY
 516 #define CONFIG_BOOTP_HOSTNAME
 517
 518
 519 /*
 520  * Command line configuration.
 521  */
 522 #include <config_cmd_default.h>
 523
 524 #define CONFIG_CMD_PING
 525 #define CONFIG_CMD_I2C
 526 #define CONFIG_CMD_ASKENV
 527 #define CONFIG_CMD_SDRAM
 528
 529 #if defined(CONFIG_PCI)
 530     #define CONFIG_CMD_PCI
 531 #endif
 532
 533 #if defined(CONFIG_SYS_RAMBOOT)
 534     #undef CONFIG_CMD_SAVEENV
 535     #undef CONFIG_CMD_LOADS
 536 #endif
 537
 538
 539 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 540
 541 /*
 542  * Miscellaneous configurable options
 543  */
 544 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 545 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 546
 547 #if defined(CONFIG_CMD_KGDB)
 548         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 549 #else
 550         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 551 #endif
 552
 553                                 /* Print Buffer Size */
 554 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 555 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 556                                 /* Boot Argument Buffer Size */
 557 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 558
 559 /*
 560  * For booting Linux, the board info and command line data
 561  * have to be in the first 256 MB of memory, since this is
 562  * the maximum mapped by the Linux kernel during initialization.
 563  */
 564 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 565
 566 /*
 567  * Core HID Setup
 568  */
 569 #define CONFIG_SYS_HID0_INIT    0x000000000
 570 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 571                                  HID0_ENABLE_INSTRUCTION_CACHE)
 572 #define CONFIG_SYS_HID2         HID2_HBE
 573
 574 /*
 575  * MMU Setup
 576  */
 577
 578 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 579 #define CONFIG_BAT_RW
 580
 581 /* DDR/LBC SDRAM: cacheable */
 582 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 583                                 | BATL_PP_RW \
 584                                 | BATL_MEMCOHERENCE)
 585 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 586                                 | BATU_BL_256M \
 587                                 | BATU_VS \
 588                                 | BATU_VP)
 589 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 590 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 591
 592 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 593 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 594                                 | BATL_PP_RW \
 595                                 | BATL_CACHEINHIBIT \
 596                                 | BATL_GUARDEDSTORAGE)
 597 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 598                                 | BATU_BL_4M \
 599                                 | BATU_VS \
 600                                 | BATU_VP)
 601 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 602 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 603
 604 /* BCSR: cache-inhibit and guarded */
 605 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
 606                                 | BATL_PP_RW \
 607                                 | BATL_CACHEINHIBIT \
 608                                 | BATL_GUARDEDSTORAGE)
 609 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
 610                                 | BATU_BL_128K \
 611                                 | BATU_VS \
 612                                 | BATU_VP)
 613 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 614 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 615
 616 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 617 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
 618                                 | BATL_PP_RW \
 619                                 | BATL_MEMCOHERENCE)
 620 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
 621                                 | BATU_BL_32M \
 622                                 | BATU_VS \
 623                                 | BATU_VP)
 624 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
 625                                 | BATL_PP_RW \
 626                                 | BATL_CACHEINHIBIT \
 627                                 | BATL_GUARDEDSTORAGE)
 628 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 629
 630 /* DDR/LBC SDRAM next 256M: cacheable */
 631 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_SDRAM_BASE2 \
 632                                 | BATL_PP_RW \
 633                                 | BATL_MEMCOHERENCE)
 634 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_SDRAM_BASE2 \
 635                                 | BATU_BL_256M \
 636                                 | BATU_VS \
 637                                 | BATU_VP)
 638 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 639 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 640
 641 /* Stack in dcache: cacheable, no memory coherence */
 642 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 643 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 644                                 | BATU_BL_128K \
 645                                 | BATU_VS \
 646                                 | BATU_VP)
 647 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 648 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 649
 650 #ifdef CONFIG_PCI
 651 /* PCI MEM space: cacheable */
 652 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
 653                                 | BATL_PP_RW \
 654                                 | BATL_MEMCOHERENCE)
 655 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
 656                                 | BATU_BL_256M \
 657                                 | BATU_VS \
 658                                 | BATU_VP)
 659 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 660 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 661 /* PCI MMIO space: cache-inhibit and guarded */
 662 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 663                                 | BATL_PP_RW \
 664                                 | BATL_CACHEINHIBIT \
 665                                 | BATL_GUARDEDSTORAGE)
 666 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 667                                 | BATU_BL_256M \
 668                                 | BATU_VS \
 669                                 | BATU_VP)
 670 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 671 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 672 #else
 673 #define CONFIG_SYS_IBAT6L       (0)
 674 #define CONFIG_SYS_IBAT6U       (0)
 675 #define CONFIG_SYS_IBAT7L       (0)
 676 #define CONFIG_SYS_IBAT7U       (0)
 677 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 678 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 679 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 680 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 681 #endif
 682
 683 #if defined(CONFIG_CMD_KGDB)
 684 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 685 #endif
 686
 687 /*
 688  * Environment Configuration
 689  */
 690
 691 #define CONFIG_ENV_OVERWRITE
 692
 693 #if defined(CONFIG_UEC_ETH)
 694 #define CONFIG_HAS_ETH0
 695 #define CONFIG_HAS_ETH1
 696 #endif
 697
 698 #define CONFIG_BAUDRATE 115200
 699
 700 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 701
 702 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 703 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 704
 705 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 706         "netdev=eth0\0"                                                 \
 707         "consoledev=ttyS0\0"                                            \
 708         "ramdiskaddr=1000000\0"                                         \
 709         "ramdiskfile=ramfs.83xx\0"                                      \
 710         "fdtaddr=780000\0"                                              \
 711         "fdtfile=mpc836x_mds.dtb\0"                                     \
 712         ""
 713
 714 #define CONFIG_NFSBOOTCOMMAND                                           \
 715         "setenv bootargs root=/dev/nfs rw "                             \
 716                 "nfsroot=$serverip:$rootpath "                          \
 717                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 718                                                         "$netdev:off "  \
 719                 "console=$consoledev,$baudrate $othbootargs;"           \
 720         "tftp $loadaddr $bootfile;"                                     \
 721         "tftp $fdtaddr $fdtfile;"                                       \
 722         "bootm $loadaddr - $fdtaddr"
 723
 724 #define CONFIG_RAMBOOTCOMMAND                                           \
 725         "setenv bootargs root=/dev/ram rw "                             \
 726                 "console=$consoledev,$baudrate $othbootargs;"           \
 727         "tftp $ramdiskaddr $ramdiskfile;"                               \
 728         "tftp $loadaddr $bootfile;"                                     \
 729         "tftp $fdtaddr $fdtfile;"                                       \
 730         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 731
 732
 733 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 734
 735 #endif  /* __CONFIG_H */