include/configs/MPC8360EMDS.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 /*
  26  * High Level Configuration Options
  27  */
  28 #define CONFIG_E300             1 /* E300 family */
  29 #define CONFIG_QE               1 /* Has QE */
  30 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  31 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  32 #define CONFIG_MPC8360EMDS      1 /* MPC8360EMDS board specific */
  33
  34 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  35
  36 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
  37 #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
  38
  39 /*
  40  * System Clock Setup
  41  */
  42 #ifdef CONFIG_PCISLAVE
  43 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
  44 #else
  45 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
  46 #endif
  47
  48 #ifndef CONFIG_SYS_CLK_FREQ
  49 #define CONFIG_SYS_CLK_FREQ     66000000
  50 #endif
  51
  52 /*
  53  * Hardware Reset Configuration Word
  54  */
  55 #define CONFIG_SYS_HRCW_LOW (\
  56         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  57         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  58         HRCWL_CSB_TO_CLKIN_4X1 |\
  59         HRCWL_VCO_1X2 |\
  60         HRCWL_CE_PLL_VCO_DIV_4 |\
  61         HRCWL_CE_PLL_DIV_1X1 |\
  62         HRCWL_CE_TO_PLL_1X6 |\
  63         HRCWL_CORE_TO_CSB_2X1)
  64
  65 #ifdef CONFIG_PCISLAVE
  66 #define CONFIG_SYS_HRCW_HIGH (\
  67         HRCWH_PCI_AGENT |\
  68         HRCWH_PCI1_ARBITER_DISABLE |\
  69         HRCWH_PCICKDRV_DISABLE |\
  70         HRCWH_CORE_ENABLE |\
  71         HRCWH_FROM_0XFFF00100 |\
  72         HRCWH_BOOTSEQ_DISABLE |\
  73         HRCWH_SW_WATCHDOG_DISABLE |\
  74         HRCWH_ROM_LOC_LOCAL_16BIT)
  75 #else
  76 #define CONFIG_SYS_HRCW_HIGH (\
  77         HRCWH_PCI_HOST |\
  78         HRCWH_PCI1_ARBITER_ENABLE |\
  79         HRCWH_PCICKDRV_ENABLE |\
  80         HRCWH_CORE_ENABLE |\
  81         HRCWH_FROM_0X00000100 |\
  82         HRCWH_BOOTSEQ_DISABLE |\
  83         HRCWH_SW_WATCHDOG_DISABLE |\
  84         HRCWH_ROM_LOC_LOCAL_16BIT)
  85 #endif
  86
  87 /*
  88  * System IO Config
  89  */
  90 #define CONFIG_SYS_SICRH                0x00000000
  91 #define CONFIG_SYS_SICRL                0x40000000
  92
  93 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  94 #define CONFIG_BOARD_EARLY_INIT_R
  95
  96 /*
  97  * IMMR new address
  98  */
  99 #define CONFIG_SYS_IMMR         0xE0000000
 100
 101 /*
 102  * DDR Setup
 103  */
 104 #define CONFIG_SYS_DDR_BASE     0x00000000 /* DDR is system memory */
 105 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
 106                                 /* + 256M */
 107 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 108 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 109 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 110                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 111
 112 #define CONFIG_SYS_83XX_DDR_USES_CS0
 113
 114 #define CONFIG_DDR_ECC          /* support DDR ECC function */
 115 #define CONFIG_DDR_ECC_CMD      /* Use DDR ECC user commands */
 116
 117 /*
 118  * DDRCDR - DDR Control Driver Register
 119  */
 120 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 121
 122 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 123 #if defined(CONFIG_SPD_EEPROM)
 124 /*
 125  * Determine DDR configuration from I2C interface.
 126  */
 127 #define SPD_EEPROM_ADDRESS      0x52 /* DDR SODIMM */
 128 #else
 129 /*
 130  * Manually set up DDR parameters
 131  */
 132 #define CONFIG_SYS_DDR_SIZE             256 /* MB */
 133 #if defined(CONFIG_DDR_II)
 134 #define CONFIG_SYS_DDRCDR               0x80080001
 135 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
 136 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80330102
 137 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
 138 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
 139 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
 140 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 141 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
 142 #define CONFIG_SYS_DDR_MODE             0x47d00432
 143 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 144 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
 145 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 146 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 147 #else
 148 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 149                                         | CSCONFIG_ROW_BIT_13 \
 150                                         | CSCONFIG_COL_BIT_9)
 151 #define CONFIG_SYS_DDR_CS1_CONFIG       CONFIG_SYS_DDR_CS0_CONFIG
 152 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
 153 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
 154 #define CONFIG_SYS_DDR_CONTROL  0x42008000 /* Self refresh,2T timing */
 155 #define CONFIG_SYS_DDR_MODE     0x20000162 /* DLL,normal,seq,4/2.5 */
 156 #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
 157 #endif
 158 #endif
 159
 160 /*
 161  * Memory test
 162  */
 163 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 164 #define CONFIG_SYS_MEMTEST_START        0x00000000 /* memtest region */
 165 #define CONFIG_SYS_MEMTEST_END          0x00100000
 166
 167 /*
 168  * The reserved memory
 169  */
 170
 171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 172
 173 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 174 #define CONFIG_SYS_RAMBOOT
 175 #else
 176 #undef  CONFIG_SYS_RAMBOOT
 177 #endif
 178
 179 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 180 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 181 #define CONFIG_SYS_MALLOC_LEN   (128 * 1024) /* Reserved for malloc */
 182
 183 /*
 184  * Initial RAM Base Address Setup
 185  */
 186 #define CONFIG_SYS_INIT_RAM_LOCK        1
 187 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 188 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 189 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 190                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 191
 192 /*
 193  * Local Bus Configuration & Clock Setup
 194  */
 195 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 196 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 197 #define CONFIG_SYS_LBC_LBCR     0x00000000
 198
 199 /*
 200  * FLASH on the Local Bus
 201  */
 202 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 203 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 204 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 205 #define CONFIG_SYS_FLASH_SIZE           32 /* max FLASH size is 32M */
 206 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 207 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 208
 209                                         /* Window base at flash base */
 210 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 211 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 212
 213 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 214                                 | BR_PS_16      /* 16 bit port */ \
 215                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 216                                 | BR_V)         /* valid */
 217 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 218                                 | OR_GPCM_XAM \
 219                                 | OR_GPCM_CSNT \
 220                                 | OR_GPCM_ACS_DIV2 \
 221                                 | OR_GPCM_XACS \
 222                                 | OR_GPCM_SCY_15 \
 223                                 | OR_GPCM_TRLX_SET \
 224                                 | OR_GPCM_EHTR_SET \
 225                                 | OR_GPCM_EAD)
 226
 227 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 228 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 229
 230 #undef  CONFIG_SYS_FLASH_CHECKSUM
 231
 232 /*
 233  * BCSR on the Local Bus
 234  */
 235 #define CONFIG_SYS_BCSR                 0xF8000000
 236                                         /* Access window base at BCSR base */
 237 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 238 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 239
 240 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_BCSR \
 241                                 | BR_PS_8 \
 242                                 | BR_MS_GPCM \
 243                                 | BR_V)
 244 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 245                                 | OR_GPCM_XAM \
 246                                 | OR_GPCM_CSNT \
 247                                 | OR_GPCM_XACS \
 248                                 | OR_GPCM_SCY_15 \
 249                                 | OR_GPCM_TRLX_SET \
 250                                 | OR_GPCM_EHTR_SET \
 251                                 | OR_GPCM_EAD)
 252                                 /* 0xFFFFE9F7 */
 253
 254 /*
 255  * SDRAM on the Local Bus
 256  */
 257 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* SDRAM base address */
 258 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 259
 260 #define CONFIG_SYS_LB_SDRAM             /* if board has SRDAM on local bus */
 261
 262 #ifdef CONFIG_SYS_LB_SDRAM
 263 #define CONFIG_SYS_LBLAWBAR2            0
 264 #define CONFIG_SYS_LBLAWAR2             (LBLAWAR_EN | LBLAWAR_64MB)
 265
 266 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 267 /*
 268  * Base Register 2 and Option Register 2 configure SDRAM.
 269  *
 270  * For BR2, need:
 271  *    Base address = BR[0:16] = dynamic
 272  *    port size = 32-bits = BR2[19:20] = 11
 273  *    no parity checking = BR2[21:22] = 00
 274  *    SDRAM for MSEL = BR2[24:26] = 011
 275  *    Valid = BR[31] = 1
 276  *
 277  * 0    4    8    12   16   20   24   28
 278  * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
 279  */
 280
 281 /* Port size=32bit, MSEL=DRAM */
 282 #define CONFIG_SYS_BR2  (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */
 283
 284 /*
 285  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 286  *
 287  * For OR2, need:
 288  *    64MB mask for AM, OR2[0:7] = 1111 1100
 289  *                 XAM, OR2[17:18] = 11
 290  *    9 columns OR2[19-21] = 010
 291  *    13 rows   OR2[23-25] = 100
 292  *    EAD set for extra time OR[31] = 1
 293  *
 294  * 0    4    8    12   16   20   24   28
 295  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 296  */
 297
 298 #define CONFIG_SYS_OR2  (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
 299                         | OR_SDRAM_XAM \
 300                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 301                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 302                         | OR_SDRAM_EAD)
 303                         /* 0xFC006901 */
 304
 305                                 /* LB sdram refresh timer, about 6us */
 306 #define CONFIG_SYS_LBC_LSRT     0x32000000
 307                                 /* LB refresh timer prescal, 266MHz/32 */
 308 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 309
 310 #define CONFIG_SYS_LBC_LSDMR_COMMON     0x0063b723
 311
 312 /*
 313  * SDRAM Controller configuration sequence.
 314  */
 315 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 316 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 317 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 318 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 319 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 320
 321 #endif
 322
 323 /*
 324  * Windows to access Platform I/O Boards (PIB) via local bus
 325  */
 326 #define CONFIG_SYS_PIB_BASE             0xF8008000
 327 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
 328
 329 /* [RFC] This LBLAW only covers the 2nd window (CS5) */
 330 #define CONFIG_SYS_LBLAWBAR3_PRELIM     \
 331                         CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE
 332 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 333
 334 /*
 335  * CS4 on Local Bus, to PIB
 336  */
 337                                 /* CS4 base address at 0xf8008000 */
 338 #define CONFIG_SYS_BR4_PRELIM   (CONFIG_SYS_PIB_BASE \
 339                                 | BR_PS_8 \
 340                                 | BR_MS_GPCM \
 341                                 | BR_V)
 342                                 /* 0xF8008801 */
 343 #define CONFIG_SYS_OR4_PRELIM   (OR_AM_32KB \
 344                                 | OR_GPCM_XAM \
 345                                 | OR_GPCM_CSNT \
 346                                 | OR_GPCM_XACS \
 347                                 | OR_GPCM_SCY_15 \
 348                                 | OR_GPCM_TRLX_SET \
 349                                 | OR_GPCM_EHTR_SET \
 350                                 | OR_GPCM_EAD)
 351                                 /* 0xffffe9f7 */
 352
 353 /*
 354  * CS5 on Local Bus, to PIB
 355  */
 356                                 /* CS5 base address at 0xf8010000 */
 357 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_PIB_BASE + \
 358                                                 CONFIG_SYS_PIB_WINDOW_SIZE) \
 359                                 | BR_PS_8 \
 360                                 | BR_MS_GPCM \
 361                                 | BR_V)
 362                                 /* 0xF8010801 */
 363 #define CONFIG_SYS_OR5_PRELIM   (CONFIG_SYS_PIB_BASE \
 364                                 | OR_GPCM_XAM \
 365                                 | OR_GPCM_CSNT \
 366                                 | OR_GPCM_XACS \
 367                                 | OR_GPCM_SCY_15 \
 368                                 | OR_GPCM_TRLX_SET \
 369                                 | OR_GPCM_EHTR_SET \
 370                                 | OR_GPCM_EAD)
 371                                 /* 0xffffe9f7 */
 372
 373 /*
 374  * Serial Port
 375  */
 376 #define CONFIG_CONS_INDEX       1
 377 #define CONFIG_SYS_NS16550
 378 #define CONFIG_SYS_NS16550_SERIAL
 379 #define CONFIG_SYS_NS16550_REG_SIZE     1
 380 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 381
 382 #define CONFIG_SYS_BAUDRATE_TABLE  \
 383                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 384
 385 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 386 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 387
 388 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 389 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 390 /* Use the HUSH parser */
 391 #define CONFIG_SYS_HUSH_PARSER
 392 #ifdef  CONFIG_SYS_HUSH_PARSER
 393 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 394 #endif
 395
 396 /* pass open firmware flat tree */
 397 #define CONFIG_OF_LIBFDT        1
 398 #define CONFIG_OF_BOARD_SETUP   1
 399 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 400
 401 /* I2C */
 402 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 403 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 404 #define CONFIG_FSL_I2C
 405 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 406 #define CONFIG_SYS_I2C_SLAVE    0x7F
 407 #define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */
 408 #define CONFIG_SYS_I2C_OFFSET   0x3000
 409 #define CONFIG_SYS_I2C2_OFFSET 0x3100
 410
 411 /*
 412  * Config on-board RTC
 413  */
 414 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 415 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 416
 417 /*
 418  * General PCI
 419  * Addresses are mapped 1-1.
 420  */
 421 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 422 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 423 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000 /* 256M */
 424 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 425 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 426 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000 /* 256M */
 427 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 428 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 429 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000 /* 1M */
 430
 431 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 432 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 433 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 434
 435
 436 #ifdef CONFIG_PCI
 437
 438 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 439 #define CONFIG_83XX_PCI_STREAMING
 440
 441 #undef CONFIG_EEPRO100
 442 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 443 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 444
 445 #endif  /* CONFIG_PCI */
 446
 447
 448 #define CONFIG_HWCONFIG         1
 449
 450 /*
 451  * QE UEC ethernet configuration
 452  */
 453 #define CONFIG_UEC_ETH
 454 #define CONFIG_ETHPRIME         "UEC0"
 455 #define CONFIG_PHY_MODE_NEED_CHANGE
 456
 457 #define CONFIG_UEC_ETH1         /* GETH1 */
 458
 459 #ifdef CONFIG_UEC_ETH1
 460 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 461 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE
 462 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK9
 463 #define CONFIG_SYS_UEC1_ETH_TYPE        GIGA_ETH
 464 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 465 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 466 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 467 #endif
 468
 469 #define CONFIG_UEC_ETH2         /* GETH2 */
 470
 471 #ifdef CONFIG_UEC_ETH2
 472 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 473 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE
 474 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK4
 475 #define CONFIG_SYS_UEC2_ETH_TYPE        GIGA_ETH
 476 #define CONFIG_SYS_UEC2_PHY_ADDR        1
 477 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 478 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 479 #endif
 480
 481 /*
 482  * Environment
 483  */
 484
 485 #ifndef CONFIG_SYS_RAMBOOT
 486         #define CONFIG_ENV_IS_IN_FLASH  1
 487         #define CONFIG_ENV_ADDR         \
 488                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 489         #define CONFIG_ENV_SECT_SIZE    0x20000
 490         #define CONFIG_ENV_SIZE         0x2000
 491 #else
 492         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 493         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 494         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 495         #define CONFIG_ENV_SIZE         0x2000
 496 #endif
 497
 498 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 499 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 500
 501 /*
 502  * BOOTP options
 503  */
 504 #define CONFIG_BOOTP_BOOTFILESIZE
 505 #define CONFIG_BOOTP_BOOTPATH
 506 #define CONFIG_BOOTP_GATEWAY
 507 #define CONFIG_BOOTP_HOSTNAME
 508
 509
 510 /*
 511  * Command line configuration.
 512  */
 513 #include <config_cmd_default.h>
 514
 515 #define CONFIG_CMD_PING
 516 #define CONFIG_CMD_I2C
 517 #define CONFIG_CMD_ASKENV
 518 #define CONFIG_CMD_SDRAM
 519
 520 #if defined(CONFIG_PCI)
 521     #define CONFIG_CMD_PCI
 522 #endif
 523
 524 #if defined(CONFIG_SYS_RAMBOOT)
 525     #undef CONFIG_CMD_SAVEENV
 526     #undef CONFIG_CMD_LOADS
 527 #endif
 528
 529
 530 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 531
 532 /*
 533  * Miscellaneous configurable options
 534  */
 535 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 536 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 537 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 538
 539 #if defined(CONFIG_CMD_KGDB)
 540         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 541 #else
 542         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 543 #endif
 544
 545                                 /* Print Buffer Size */
 546 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 547 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 548                                 /* Boot Argument Buffer Size */
 549 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 550 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 551
 552 /*
 553  * For booting Linux, the board info and command line data
 554  * have to be in the first 256 MB of memory, since this is
 555  * the maximum mapped by the Linux kernel during initialization.
 556  */
 557 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 558
 559 /*
 560  * Core HID Setup
 561  */
 562 #define CONFIG_SYS_HID0_INIT    0x000000000
 563 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 564                                  HID0_ENABLE_INSTRUCTION_CACHE)
 565 #define CONFIG_SYS_HID2         HID2_HBE
 566
 567 /*
 568  * MMU Setup
 569  */
 570
 571 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 572
 573 /* DDR/LBC SDRAM: cacheable */
 574 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 575                                 | BATL_PP_RW \
 576                                 | BATL_MEMCOHERENCE)
 577 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 578                                 | BATU_BL_256M \
 579                                 | BATU_VS \
 580                                 | BATU_VP)
 581 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 582 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 583
 584 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 585 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 586                                 | BATL_PP_RW \
 587                                 | BATL_CACHEINHIBIT \
 588                                 | BATL_GUARDEDSTORAGE)
 589 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 590                                 | BATU_BL_4M \
 591                                 | BATU_VS \
 592                                 | BATU_VP)
 593 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 594 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 595
 596 /* BCSR: cache-inhibit and guarded */
 597 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
 598                                 | BATL_PP_RW \
 599                                 | BATL_CACHEINHIBIT \
 600                                 | BATL_GUARDEDSTORAGE)
 601 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
 602                                 | BATU_BL_128K \
 603                                 | BATU_VS \
 604                                 | BATU_VP)
 605 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 606 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 607
 608 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 609 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
 610                                 | BATL_PP_RW \
 611                                 | BATL_MEMCOHERENCE)
 612 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
 613                                 | BATU_BL_32M \
 614                                 | BATU_VS \
 615                                 | BATU_VP)
 616 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
 617                                 | BATL_PP_RW \
 618                                 | BATL_CACHEINHIBIT \
 619                                 | BATL_GUARDEDSTORAGE)
 620 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 621
 622 /* DDR/LBC SDRAM next 256M: cacheable */
 623 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_SDRAM_BASE2 \
 624                                 | BATL_PP_RW \
 625                                 | BATL_MEMCOHERENCE)
 626 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_SDRAM_BASE2 \
 627                                 | BATU_BL_256M \
 628                                 | BATU_VS \
 629                                 | BATU_VP)
 630 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 631 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 632
 633 /* Stack in dcache: cacheable, no memory coherence */
 634 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 635 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 636                                 | BATU_BL_128K \
 637                                 | BATU_VS \
 638                                 | BATU_VP)
 639 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 640 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 641
 642 #ifdef CONFIG_PCI
 643 /* PCI MEM space: cacheable */
 644 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
 645                                 | BATL_PP_RW \
 646                                 | BATL_MEMCOHERENCE)
 647 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
 648                                 | BATU_BL_256M \
 649                                 | BATU_VS \
 650                                 | BATU_VP)
 651 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 652 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 653 /* PCI MMIO space: cache-inhibit and guarded */
 654 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 655                                 | BATL_PP_RW \
 656                                 | BATL_CACHEINHIBIT \
 657                                 | BATL_GUARDEDSTORAGE)
 658 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 659                                 | BATU_BL_256M \
 660                                 | BATU_VS \
 661                                 | BATU_VP)
 662 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 663 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 664 #else
 665 #define CONFIG_SYS_IBAT6L       (0)
 666 #define CONFIG_SYS_IBAT6U       (0)
 667 #define CONFIG_SYS_IBAT7L       (0)
 668 #define CONFIG_SYS_IBAT7U       (0)
 669 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 670 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 671 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 672 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 673 #endif
 674
 675 #if defined(CONFIG_CMD_KGDB)
 676 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 677 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 678 #endif
 679
 680 /*
 681  * Environment Configuration
 682  */
 683
 684 #define CONFIG_ENV_OVERWRITE
 685
 686 #if defined(CONFIG_UEC_ETH)
 687 #define CONFIG_HAS_ETH0
 688 #define CONFIG_HAS_ETH1
 689 #endif
 690
 691 #define CONFIG_BAUDRATE 115200
 692
 693 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 694
 695 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 696 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 697
 698 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 699         "netdev=eth0\0"                                                 \
 700         "consoledev=ttyS0\0"                                            \
 701         "ramdiskaddr=1000000\0"                                         \
 702         "ramdiskfile=ramfs.83xx\0"                                      \
 703         "fdtaddr=780000\0"                                              \
 704         "fdtfile=mpc836x_mds.dtb\0"                                     \
 705         ""
 706
 707 #define CONFIG_NFSBOOTCOMMAND                                           \
 708         "setenv bootargs root=/dev/nfs rw "                             \
 709                 "nfsroot=$serverip:$rootpath "                          \
 710                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 711                                                         "$netdev:off "  \
 712                 "console=$consoledev,$baudrate $othbootargs;"           \
 713         "tftp $loadaddr $bootfile;"                                     \
 714         "tftp $fdtaddr $fdtfile;"                                       \
 715         "bootm $loadaddr - $fdtaddr"
 716
 717 #define CONFIG_RAMBOOTCOMMAND                                           \
 718         "setenv bootargs root=/dev/ram rw "                             \
 719                 "console=$consoledev,$baudrate $othbootargs;"           \
 720         "tftp $ramdiskaddr $ramdiskfile;"                               \
 721         "tftp $loadaddr $bootfile;"                                     \
 722         "tftp $fdtaddr $fdtfile;"                                       \
 723         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 724
 725
 726 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 727
 728 #endif  /* __CONFIG_H */