include/configs/MPC8360EMDS.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 /*
  26  * High Level Configuration Options
  27  */
  28 #define CONFIG_E300             1 /* E300 family */
  29 #define CONFIG_QE               1 /* Has QE */
  30 #define CONFIG_MPC83XX          1 /* MPC83XX family */
  31 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  32 #define CONFIG_MPC8360EMDS      1 /* MPC8360EMDS board specific */
  33 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
  34 #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
  35
  36 /*
  37  * System Clock Setup
  38  */
  39 #ifdef CONFIG_PCISLAVE
  40 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
  41 #else
  42 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
  43 #endif
  44
  45 #ifndef CONFIG_SYS_CLK_FREQ
  46 #define CONFIG_SYS_CLK_FREQ     66000000
  47 #endif
  48
  49 /*
  50  * Hardware Reset Configuration Word
  51  */
  52 #define CONFIG_SYS_HRCW_LOW (\
  53         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  54         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  55         HRCWL_CSB_TO_CLKIN_4X1 |\
  56         HRCWL_VCO_1X2 |\
  57         HRCWL_CE_PLL_VCO_DIV_4 |\
  58         HRCWL_CE_PLL_DIV_1X1 |\
  59         HRCWL_CE_TO_PLL_1X6 |\
  60         HRCWL_CORE_TO_CSB_2X1)
  61
  62 #ifdef CONFIG_PCISLAVE
  63 #define CONFIG_SYS_HRCW_HIGH (\
  64         HRCWH_PCI_AGENT |\
  65         HRCWH_PCI1_ARBITER_DISABLE |\
  66         HRCWH_PCICKDRV_DISABLE |\
  67         HRCWH_CORE_ENABLE |\
  68         HRCWH_FROM_0XFFF00100 |\
  69         HRCWH_BOOTSEQ_DISABLE |\
  70         HRCWH_SW_WATCHDOG_DISABLE |\
  71         HRCWH_ROM_LOC_LOCAL_16BIT)
  72 #else
  73 #define CONFIG_SYS_HRCW_HIGH (\
  74         HRCWH_PCI_HOST |\
  75         HRCWH_PCI1_ARBITER_ENABLE |\
  76         HRCWH_PCICKDRV_ENABLE |\
  77         HRCWH_CORE_ENABLE |\
  78         HRCWH_FROM_0X00000100 |\
  79         HRCWH_BOOTSEQ_DISABLE |\
  80         HRCWH_SW_WATCHDOG_DISABLE |\
  81         HRCWH_ROM_LOC_LOCAL_16BIT)
  82 #endif
  83
  84 /*
  85  * System IO Config
  86  */
  87 #define CONFIG_SYS_SICRH                0x00000000
  88 #define CONFIG_SYS_SICRL                0x40000000
  89
  90 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  91 #define CONFIG_BOARD_EARLY_INIT_R
  92
  93 /*
  94  * IMMR new address
  95  */
  96 #define CONFIG_SYS_IMMR         0xE0000000
  97
  98 /*
  99  * DDR Setup
 100  */
 101 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 102 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 103 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 104 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
 105                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 106
 107 #define CONFIG_SYS_83XX_DDR_USES_CS0
 108
 109 #define CONFIG_DDR_ECC          /* support DDR ECC function */
 110 #define CONFIG_DDR_ECC_CMD      /* Use DDR ECC user commands */
 111
 112 /*
 113  * DDRCDR - DDR Control Driver Register
 114  */
 115 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 116
 117 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 118 #if defined(CONFIG_SPD_EEPROM)
 119 /*
 120  * Determine DDR configuration from I2C interface.
 121  */
 122 #define SPD_EEPROM_ADDRESS      0x52 /* DDR SODIMM */
 123 #else
 124 /*
 125  * Manually set up DDR parameters
 126  */
 127 #define CONFIG_SYS_DDR_SIZE             256 /* MB */
 128 #if defined(CONFIG_DDR_II)
 129 #define CONFIG_SYS_DDRCDR               0x80080001
 130 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
 131 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80330102
 132 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
 133 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
 134 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
 135 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 136 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
 137 #define CONFIG_SYS_DDR_MODE             0x47d00432
 138 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 139 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
 140 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 141 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 142 #else
 143 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
 144 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
 145 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
 146 #define CONFIG_SYS_DDR_CONTROL          0x42008000 /* Self refresh,2T timing */
 147 #define CONFIG_SYS_DDR_MODE             0x20000162 /* DLL,normal,seq,4/2.5 */
 148 #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
 149 #endif
 150 #endif
 151
 152 /*
 153  * Memory test
 154  */
 155 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 156 #define CONFIG_SYS_MEMTEST_START        0x00000000 /* memtest region */
 157 #define CONFIG_SYS_MEMTEST_END          0x00100000
 158
 159 /*
 160  * The reserved memory
 161  */
 162
 163 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 164
 165 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 166 #define CONFIG_SYS_RAMBOOT
 167 #else
 168 #undef  CONFIG_SYS_RAMBOOT
 169 #endif
 170
 171 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 172 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 173 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024) /* Reserved for malloc */
 174
 175 /*
 176  * Initial RAM Base Address Setup
 177  */
 178 #define CONFIG_SYS_INIT_RAM_LOCK        1
 179 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 180 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 181 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 182 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 183
 184 /*
 185  * Local Bus Configuration & Clock Setup
 186  */
 187 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_CLKDIV_4)
 188 #define CONFIG_SYS_LBC_LBCR             0x00000000
 189
 190 /*
 191  * FLASH on the Local Bus
 192  */
 193 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 194 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 195 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 196 #define CONFIG_SYS_FLASH_SIZE           32 /* max FLASH size is 32M */
 197 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
 198 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 199
 200 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 201 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018 /* 32MB window size */
 202
 203 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
 204                         (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 205                         BR_V)   /* valid */
 206 #define CONFIG_SYS_OR0_PRELIM           ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 207                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 208                                 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 209
 210 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 211 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 212
 213 #undef  CONFIG_SYS_FLASH_CHECKSUM
 214
 215 /*
 216  * BCSR on the Local Bus
 217  */
 218 #define CONFIG_SYS_BCSR         0xF8000000
 219 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR /* Access window base at BCSR base */
 220 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000F /* Access window size 64K */
 221
 222 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
 223 #define CONFIG_SYS_OR1_PRELIM           0xFFFFE9f7 /* length 32K */
 224
 225 /*
 226  * SDRAM on the Local Bus
 227  */
 228 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* SDRAM base address */
 229 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 230
 231 #define CONFIG_SYS_LB_SDRAM             /* if board has SRDAM on local bus */
 232
 233 #ifdef CONFIG_SYS_LB_SDRAM
 234 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 235 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019 /* 64MB */
 236
 237 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 238 /*
 239  * Base Register 2 and Option Register 2 configure SDRAM.
 240  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 241  *
 242  * For BR2, need:
 243  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 244  *    port size = 32-bits = BR2[19:20] = 11
 245  *    no parity checking = BR2[21:22] = 00
 246  *    SDRAM for MSEL = BR2[24:26] = 011
 247  *    Valid = BR[31] = 1
 248  *
 249  * 0    4    8    12   16   20   24   28
 250  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 251  *
 252  * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 253  * the top 17 bits of BR2.
 254  */
 255
 256 #define CONFIG_SYS_BR2_PRELIM   0xf0001861 /*Port size=32bit, MSEL=SDRAM */
 257
 258 /*
 259  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 260  *
 261  * For OR2, need:
 262  *    64MB mask for AM, OR2[0:7] = 1111 1100
 263  *                 XAM, OR2[17:18] = 11
 264  *    9 columns OR2[19-21] = 010
 265  *    13 rows   OR2[23-25] = 100
 266  *    EAD set for extra time OR[31] = 1
 267  *
 268  * 0    4    8    12   16   20   24   28
 269  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 270  */
 271
 272 #define CONFIG_SYS_OR2_PRELIM   0xfc006901
 273
 274 #define CONFIG_SYS_LBC_LSRT     0x32000000 /* LB sdram refresh timer, about 6us */
 275 #define CONFIG_SYS_LBC_MRTPR    0x20000000 /* LB refresh timer prescal, 266MHz/32 */
 276
 277 /*
 278  * LSDMR masks
 279  */
 280 #define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
 281 #define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
 282 #define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
 283 #define CONFIG_SYS_LBC_LSDMR_OP_MRW     (3 << (31 - 4))
 284 #define CONFIG_SYS_LBC_LSDMR_OP_PRECH   (4 << (31 - 4))
 285 #define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
 286 #define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
 287 #define CONFIG_SYS_LBC_LSDMR_OP_RWINV   (7 << (31 - 4))
 288
 289 #define CONFIG_SYS_LBC_LSDMR_COMMON     0x0063b723
 290
 291 /*
 292  * SDRAM Controller configuration sequence.
 293  */
 294 #define CONFIG_SYS_LBC_LSDMR_1          ( CONFIG_SYS_LBC_LSDMR_COMMON \
 295                                 | CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
 296 #define CONFIG_SYS_LBC_LSDMR_2          ( CONFIG_SYS_LBC_LSDMR_COMMON \
 297                                 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
 298 #define CONFIG_SYS_LBC_LSDMR_3          ( CONFIG_SYS_LBC_LSDMR_COMMON \
 299                                 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
 300 #define CONFIG_SYS_LBC_LSDMR_4          ( CONFIG_SYS_LBC_LSDMR_COMMON \
 301                                 | CONFIG_SYS_LBC_LSDMR_OP_MRW)
 302 #define CONFIG_SYS_LBC_LSDMR_5          ( CONFIG_SYS_LBC_LSDMR_COMMON \
 303                                 | CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
 304
 305 #endif
 306
 307 /*
 308  * Windows to access PIB via local bus
 309  */
 310 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0xf8010000 /* windows base 0xf8010000 */
 311 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000e /* windows size 32KB */
 312
 313 /*
 314  * CS4 on Local Bus, to PIB
 315  */
 316 #define CONFIG_SYS_BR4_PRELIM   0xf8010801 /* CS4 base address at 0xf8010000 */
 317 #define CONFIG_SYS_OR4_PRELIM   0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 318
 319 /*
 320  * CS5 on Local Bus, to PIB
 321  */
 322 #define CONFIG_SYS_BR5_PRELIM   0xf8008801 /* CS5 base address at 0xf8008000 */
 323 #define CONFIG_SYS_OR5_PRELIM   0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 324
 325 /*
 326  * Serial Port
 327  */
 328 #define CONFIG_CONS_INDEX       1
 329 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 330 #define CONFIG_SYS_NS16550
 331 #define CONFIG_SYS_NS16550_SERIAL
 332 #define CONFIG_SYS_NS16550_REG_SIZE     1
 333 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 334
 335 #define CONFIG_SYS_BAUDRATE_TABLE  \
 336         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 337
 338 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 339 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 340
 341 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 342 /* Use the HUSH parser */
 343 #define CONFIG_SYS_HUSH_PARSER
 344 #ifdef  CONFIG_SYS_HUSH_PARSER
 345 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 346 #endif
 347
 348 /* pass open firmware flat tree */
 349 #define CONFIG_OF_LIBFDT        1
 350 #define CONFIG_OF_BOARD_SETUP   1
 351 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 352
 353 /* I2C */
 354 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 355 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 356 #define CONFIG_FSL_I2C
 357 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 358 #define CONFIG_SYS_I2C_SLAVE    0x7F
 359 #define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */
 360 #define CONFIG_SYS_I2C_OFFSET   0x3000
 361 #define CONFIG_SYS_I2C2_OFFSET 0x3100
 362
 363 /*
 364  * Config on-board RTC
 365  */
 366 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 367 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 368
 369 /*
 370  * General PCI
 371  * Addresses are mapped 1-1.
 372  */
 373 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
 374 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
 375 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
 376 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 377 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 378 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 379 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 380 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 381 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 382
 383 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 384 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 385 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 386
 387
 388 #ifdef CONFIG_PCI
 389
 390 #define CONFIG_NET_MULTI
 391 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 392
 393 #undef CONFIG_EEPRO100
 394 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 395 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 396
 397 #endif  /* CONFIG_PCI */
 398
 399
 400 #ifndef CONFIG_NET_MULTI
 401 #define CONFIG_NET_MULTI        1
 402 #endif
 403
 404 /*
 405  * QE UEC ethernet configuration
 406  */
 407 #define CONFIG_UEC_ETH
 408 #define CONFIG_ETHPRIME         "FSL UEC0"
 409 #define CONFIG_PHY_MODE_NEED_CHANGE
 410
 411 #define CONFIG_UEC_ETH1         /* GETH1 */
 412
 413 #ifdef CONFIG_UEC_ETH1
 414 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 415 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE
 416 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK9
 417 #define CONFIG_SYS_UEC1_ETH_TYPE        GIGA_ETH
 418 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 419 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_GMII
 420 #endif
 421
 422 #define CONFIG_UEC_ETH2         /* GETH2 */
 423
 424 #ifdef CONFIG_UEC_ETH2
 425 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 426 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE
 427 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK4
 428 #define CONFIG_SYS_UEC2_ETH_TYPE        GIGA_ETH
 429 #define CONFIG_SYS_UEC2_PHY_ADDR        1
 430 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_GMII
 431 #endif
 432
 433 /*
 434  * Environment
 435  */
 436
 437 #ifndef CONFIG_SYS_RAMBOOT
 438         #define CONFIG_ENV_IS_IN_FLASH  1
 439         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 440         #define CONFIG_ENV_SECT_SIZE    0x20000
 441         #define CONFIG_ENV_SIZE         0x2000
 442 #else
 443         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 444         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 445         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 446         #define CONFIG_ENV_SIZE         0x2000
 447 #endif
 448
 449 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 450 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 451
 452 /*
 453  * BOOTP options
 454  */
 455 #define CONFIG_BOOTP_BOOTFILESIZE
 456 #define CONFIG_BOOTP_BOOTPATH
 457 #define CONFIG_BOOTP_GATEWAY
 458 #define CONFIG_BOOTP_HOSTNAME
 459
 460
 461 /*
 462  * Command line configuration.
 463  */
 464 #include <config_cmd_default.h>
 465
 466 #define CONFIG_CMD_PING
 467 #define CONFIG_CMD_I2C
 468 #define CONFIG_CMD_ASKENV
 469 #define CONFIG_CMD_SDRAM
 470
 471 #if defined(CONFIG_PCI)
 472     #define CONFIG_CMD_PCI
 473 #endif
 474
 475 #if defined(CONFIG_SYS_RAMBOOT)
 476     #undef CONFIG_CMD_ENV
 477     #undef CONFIG_CMD_LOADS
 478 #endif
 479
 480
 481 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 482
 483 /*
 484  * Miscellaneous configurable options
 485  */
 486 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 487 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 488 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 489
 490 #if defined(CONFIG_CMD_KGDB)
 491         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 492 #else
 493         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 494 #endif
 495
 496 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 497 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 498 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 499 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 500
 501 /*
 502  * For booting Linux, the board info and command line data
 503  * have to be in the first 8 MB of memory, since this is
 504  * the maximum mapped by the Linux kernel during initialization.
 505  */
 506 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 507
 508 /*
 509  * Core HID Setup
 510  */
 511 #define CONFIG_SYS_HID0_INIT            0x000000000
 512 #define CONFIG_SYS_HID0_FINAL           HID0_ENABLE_MACHINE_CHECK
 513 #define CONFIG_SYS_HID2         HID2_HBE
 514
 515 /*
 516  * MMU Setup
 517  */
 518
 519 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 520
 521 /* DDR: cache cacheable */
 522 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 523 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 524 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 525 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 526
 527 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 528 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 529                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 530 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 531 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 532 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 533
 534 /* BCSR: cache-inhibit and guarded */
 535 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR | BATL_PP_10 | \
 536                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 537 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
 538 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 539 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 540
 541 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 542 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 543 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 544 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 545                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 546 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 547
 548 /* Local bus SDRAM: cacheable */
 549 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 550 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 551 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 552 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 553
 554 /* Stack in dcache: cacheable, no memory coherence */
 555 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 556 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 557 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 558 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 559
 560 #ifdef CONFIG_PCI
 561 /* PCI MEM space: cacheable */
 562 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 563 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 564 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 565 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 566 /* PCI MMIO space: cache-inhibit and guarded */
 567 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
 568                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 569 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 570 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 571 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 572 #else
 573 #define CONFIG_SYS_IBAT6L       (0)
 574 #define CONFIG_SYS_IBAT6U       (0)
 575 #define CONFIG_SYS_IBAT7L       (0)
 576 #define CONFIG_SYS_IBAT7U       (0)
 577 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 578 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 579 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 580 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 581 #endif
 582
 583 /*
 584  * Internal Definitions
 585  *
 586  * Boot Flags
 587  */
 588 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 589 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 590
 591 #if defined(CONFIG_CMD_KGDB)
 592 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 593 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 594 #endif
 595
 596 /*
 597  * Environment Configuration
 598  */
 599
 600 #define CONFIG_ENV_OVERWRITE
 601
 602 #if defined(CONFIG_UEC_ETH)
 603 #define CONFIG_HAS_ETH0
 604 #define CONFIG_ETHADDR  00:04:9f:ef:01:01
 605 #define CONFIG_HAS_ETH1
 606 #define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
 607 #endif
 608
 609 #define CONFIG_BAUDRATE 115200
 610
 611 #define CONFIG_LOADADDR 500000  /* default location for tftp and bootm */
 612
 613 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 614 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 615
 616 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 617    "netdev=eth0\0"                                                      \
 618    "consoledev=ttyS0\0"                                                 \
 619    "ramdiskaddr=1000000\0"                                              \
 620    "ramdiskfile=ramfs.83xx\0"                                           \
 621    "fdtaddr=400000\0"                                                   \
 622    "fdtfile=mpc836x_mds.dtb\0"                                          \
 623    ""
 624
 625 #define CONFIG_NFSBOOTCOMMAND                                           \
 626    "setenv bootargs root=/dev/nfs rw "                                  \
 627       "nfsroot=$serverip:$rootpath "                                    \
 628       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 629       "console=$consoledev,$baudrate $othbootargs;"                     \
 630    "tftp $loadaddr $bootfile;"                                          \
 631    "tftp $fdtaddr $fdtfile;"                                            \
 632    "bootm $loadaddr - $fdtaddr"
 633
 634 #define CONFIG_RAMBOOTCOMMAND                                           \
 635    "setenv bootargs root=/dev/ram rw "                                  \
 636       "console=$consoledev,$baudrate $othbootargs;"                     \
 637    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 638    "tftp $loadaddr $bootfile;"                                          \
 639    "tftp $fdtaddr $fdtfile;"                                            \
 640    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 641
 642
 643 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 644
 645 #endif  /* __CONFIG_H */