include/configs/MPC8360ERDK.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  */
  23 #define CONFIG_E300             1 /* E300 family */
  24 #define CONFIG_QE               1 /* Has QE */
  25 #define CONFIG_MPC83XX          1 /* MPC83XX family */
  26 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  27 #define CONFIG_MPC8360ERDK      1 /* MPC8360ERDK board specific */
  28
  29 /*
  30  * System Clock Setup
  31  */
  32 #ifdef CONFIG_CLKIN_33MHZ
  33 #define CONFIG_83XX_CLKIN               33333333
  34 #define CONFIG_SYS_CLK_FREQ             33333333
  35 #define PCI_33M                         1
  36 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK  HRCWL_CSB_TO_CLKIN_10X1
  37 #else
  38 #define CONFIG_83XX_CLKIN               66000000
  39 #define CONFIG_SYS_CLK_FREQ             66000000
  40 #define PCI_66M                         1
  41 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK  HRCWL_CSB_TO_CLKIN_5X1
  42 #endif /* CONFIG_CLKIN_33MHZ */
  43
  44 /*
  45  * Hardware Reset Configuration Word
  46  */
  47 #define CONFIG_SYS_HRCW_LOW (\
  48         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  49         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  50         HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
  51         HRCWL_CORE_TO_CSB_2X1 |\
  52         HRCWL_CE_TO_PLL_1X15)
  53
  54 #define CONFIG_SYS_HRCW_HIGH (\
  55         HRCWH_PCI_HOST |\
  56         HRCWH_PCI1_ARBITER_ENABLE |\
  57         HRCWH_PCICKDRV_ENABLE |\
  58         HRCWH_CORE_ENABLE |\
  59         HRCWH_FROM_0X00000100 |\
  60         HRCWH_BOOTSEQ_DISABLE |\
  61         HRCWH_SW_WATCHDOG_DISABLE |\
  62         HRCWH_ROM_LOC_LOCAL_16BIT |\
  63         HRCWH_SECONDARY_DDR_DISABLE |\
  64         HRCWH_BIG_ENDIAN |\
  65         HRCWH_LALE_EARLY)
  66
  67 /*
  68  * System IO Config
  69  */
  70 #define CONFIG_SYS_SICRH                0x00000000
  71 #define CONFIG_SYS_SICRL                0x40000000
  72
  73 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  74 #define CONFIG_BOARD_EARLY_INIT_R
  75
  76 /*
  77  * IMMR new address
  78  */
  79 #define CONFIG_SYS_IMMR         0xE0000000
  80
  81 /*
  82  * DDR Setup
  83  */
  84 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  85 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  86 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  87 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  88                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  89
  90 #define CONFIG_SYS_83XX_DDR_USES_CS0
  91
  92 #define CONFIG_DDR_ECC          /* support DDR ECC function */
  93 #define CONFIG_DDR_ECC_CMD      /* Use DDR ECC user commands */
  94
  95 /*
  96  * DDRCDR - DDR Control Driver Register
  97  */
  98 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  99
 100 #undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
 101
 102 /*
 103  * Manually set up DDR parameters
 104  */
 105 #define CONFIG_DDR_II
 106 #define CONFIG_SYS_DDR_SIZE             256 /* MB */
 107 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
 108 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
 109                                  CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
 110 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
 111 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000
 112 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 113 #define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 114                                  (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
 115 #define CONFIG_SYS_DDR_MODE             0x47800432
 116 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 117
 118 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 119                                  (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 120                                  (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 121                                  (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 122                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 123                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 124                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 125                                  (0 << TIMING_CFG0_RWT_SHIFT))
 126
 127 #define CONFIG_SYS_DDR_TIMING_1 ((      TIMING_CFG1_CASLAT_30) | \
 128                                  ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 129                                  ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 130                                  ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
 131                                  (10 << TIMING_CFG1_REFREC_SHIFT) | \
 132                                  ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 133                                  ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 134                                  ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
 135
 136 #define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 137                                  (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 138                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 139                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 140                                  (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 141                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 142                                  (0 << TIMING_CFG2_CPO_SHIFT))
 143
 144 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 145
 146 /*
 147  * Memory test
 148  */
 149 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 150 #define CONFIG_SYS_MEMTEST_START        0x00000000 /* memtest region */
 151 #define CONFIG_SYS_MEMTEST_END          0x00100000
 152
 153 /*
 154  * The reserved memory
 155  */
 156 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 157 #define CONFIG_SYS_FLASH_BASE           0xFF800000 /* FLASH base address */
 158
 159 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 160 #define CONFIG_SYS_RAMBOOT
 161 #else
 162 #undef  CONFIG_SYS_RAMBOOT
 163 #endif
 164
 165 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 166 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024) /* Reserved for malloc */
 167
 168 /*
 169  * Initial RAM Base Address Setup
 170  */
 171 #define CONFIG_SYS_INIT_RAM_LOCK        1
 172 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 173 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 174 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 175 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 176
 177 /*
 178  * Local Bus Configuration & Clock Setup
 179  */
 180 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_CLKDIV_4)
 181 #define CONFIG_SYS_LBC_LBCR             0x00000000
 182
 183 /*
 184  * FLASH on the Local Bus
 185  */
 186 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 187 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 188 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 189 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use intel Flash protection. */
 190
 191 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 192 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018 /* 32MB window size */
 193
 194 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
 195                         (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 196                         BR_V)   /* valid */
 197 #define CONFIG_SYS_OR0_PRELIM           ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 198                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 199                                 OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 200                                 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 201
 202 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 203 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 204
 205 #undef  CONFIG_SYS_FLASH_CHECKSUM
 206
 207 /*
 208  * NAND flash on the local bus
 209  */
 210 #define CONFIG_SYS_NAND_BASE            0x60000000
 211 #define CONFIG_CMD_NAND         1
 212 #define CONFIG_NAND_FSL_UPM     1
 213 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 214 #define CONFIG_MTD_NAND_VERIFY_WRITE
 215
 216 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 217 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000001b /* Access window size 4K */
 218
 219 /* Port size 8 bit, UPMA */
 220 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_NAND_BASE | 0x00000881)
 221 #define CONFIG_SYS_OR1_PRELIM           0xfc000001
 222
 223 /*
 224  * Fujitsu MB86277 (MINT) graphics controller
 225  */
 226 #define CONFIG_SYS_VIDEO_BASE           0x70000000
 227
 228 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VIDEO_BASE
 229 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019 /* Access window size 64MB */
 230
 231 /* Port size 32 bit, UPMB */
 232 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
 233 #define CONFIG_SYS_OR2_PRELIM           0xfc000001 /* (64MB, EAD=1) */
 234
 235 /*
 236  * Serial Port
 237  */
 238 #define CONFIG_CONS_INDEX       1
 239 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 240 #define CONFIG_SYS_NS16550
 241 #define CONFIG_SYS_NS16550_SERIAL
 242 #define CONFIG_SYS_NS16550_REG_SIZE     1
 243 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 244
 245 #define CONFIG_SYS_BAUDRATE_TABLE  \
 246         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
 247
 248 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 249 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 250
 251 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 252 /* Use the HUSH parser */
 253 #define CONFIG_SYS_HUSH_PARSER
 254 #ifdef  CONFIG_SYS_HUSH_PARSER
 255 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 256 #endif
 257
 258 /* Pass open firmware flat tree */
 259 #define CONFIG_OF_LIBFDT        1
 260 #define CONFIG_OF_BOARD_SETUP   1
 261 #define CONFIG_OF_STDOUT_VIA_ALIAS
 262
 263 /* I2C */
 264 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 265 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 266 #define CONFIG_FSL_I2C
 267 #define CONFIG_I2C_MULTI_BUS
 268 #define CONFIG_I2C_CMD_TREE
 269 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 270 #define CONFIG_SYS_I2C_SLAVE    0x7F
 271 #define CONFIG_SYS_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */
 272 #define CONFIG_SYS_I2C_OFFSET   0x3000
 273 #define CONFIG_SYS_I2C2_OFFSET 0x3100
 274
 275 /*
 276  * General PCI
 277  * Addresses are mapped 1-1.
 278  */
 279 #define CONFIG_PCI
 280 #define CONFIG_83XX_GENERIC_PCI 1
 281
 282 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 283 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 284 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000 /* 256M */
 285 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 286 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 287 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000 /* 256M */
 288 #define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
 289 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
 290 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
 291
 292 #ifdef CONFIG_PCI
 293
 294 #define CONFIG_NET_MULTI
 295 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 296
 297 #undef CONFIG_EEPRO100
 298 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 299 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 300
 301 #endif  /* CONFIG_PCI */
 302
 303
 304 #ifndef CONFIG_NET_MULTI
 305 #define CONFIG_NET_MULTI        1
 306 #endif
 307
 308 /*
 309  * QE UEC ethernet configuration
 310  */
 311 #define CONFIG_UEC_ETH
 312 #define CONFIG_ETHPRIME         "FSL UEC0"
 313
 314 #define CONFIG_UEC_ETH1         /* GETH1 */
 315
 316 #ifdef CONFIG_UEC_ETH1
 317 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 318 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE
 319 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK9
 320 #define CONFIG_SYS_UEC1_ETH_TYPE        GIGA_ETH
 321 #define CONFIG_SYS_UEC1_PHY_ADDR        2
 322 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
 323 #endif
 324
 325 #define CONFIG_UEC_ETH2         /* GETH2 */
 326
 327 #ifdef CONFIG_UEC_ETH2
 328 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 329 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE
 330 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK4
 331 #define CONFIG_SYS_UEC2_ETH_TYPE        GIGA_ETH
 332 #define CONFIG_SYS_UEC2_PHY_ADDR        4
 333 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
 334 #endif
 335
 336 /*
 337  * Environment
 338  */
 339
 340 #ifndef CONFIG_SYS_RAMBOOT
 341 #define CONFIG_ENV_IS_IN_FLASH  1
 342 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 343 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 344 #define CONFIG_ENV_SIZE         0x20000
 345 #else /* CONFIG_SYS_RAMBOOT */
 346 #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 347 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 348 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 349 #define CONFIG_ENV_SIZE         0x2000
 350 #endif /* CONFIG_SYS_RAMBOOT */
 351
 352 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 353 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 354
 355 /*
 356  * BOOTP options
 357  */
 358 #define CONFIG_BOOTP_BOOTFILESIZE
 359 #define CONFIG_BOOTP_BOOTPATH
 360 #define CONFIG_BOOTP_GATEWAY
 361 #define CONFIG_BOOTP_HOSTNAME
 362
 363
 364 /*
 365  * Command line configuration.
 366  */
 367 #include <config_cmd_default.h>
 368
 369 #define CONFIG_CMD_PING
 370 #define CONFIG_CMD_I2C
 371 #define CONFIG_CMD_ASKENV
 372 #define CONFIG_CMD_DHCP
 373
 374 #if defined(CONFIG_PCI)
 375 #define CONFIG_CMD_PCI
 376 #endif
 377
 378 #if defined(CONFIG_SYS_RAMBOOT)
 379 #undef CONFIG_CMD_SAVEENV
 380 #undef CONFIG_CMD_LOADS
 381 #endif
 382
 383 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 384
 385 /*
 386  * Miscellaneous configurable options
 387  */
 388 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 389 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 390 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 391
 392 #if defined(CONFIG_CMD_KGDB)
 393         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 394 #else
 395         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 396 #endif
 397
 398 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 399 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 400 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 401 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 402
 403 /*
 404  * For booting Linux, the board info and command line data
 405  * have to be in the first 8 MB of memory, since this is
 406  * the maximum mapped by the Linux kernel during initialization.
 407  */
 408 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 409
 410 /*
 411  * Core HID Setup
 412  */
 413 #define CONFIG_SYS_HID0_INIT            0x000000000
 414 #define CONFIG_SYS_HID0_FINAL           HID0_ENABLE_MACHINE_CHECK
 415 #define CONFIG_SYS_HID2         HID2_HBE
 416
 417 /*
 418  * MMU Setup
 419  */
 420
 421 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 422
 423 /* DDR: cache cacheable */
 424 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 425 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 426 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 427 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 428
 429 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 430 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 431                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 432 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 433 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 434 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 435
 436 /* NAND: cache-inhibit and guarded */
 437 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
 438                          BATL_GUARDEDSTORAGE)
 439 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 440 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 441 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 442
 443 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 444 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 445 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 446 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 447                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 448 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 449
 450 /* Stack in dcache: cacheable, no memory coherence */
 451 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 452 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 453 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 454 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 455
 456 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
 457                          BATL_GUARDEDSTORAGE)
 458 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 459 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 460 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 461
 462 #ifdef CONFIG_PCI
 463 /* PCI MEM space: cacheable */
 464 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 465 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 466 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 467 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 468 /* PCI MMIO space: cache-inhibit and guarded */
 469 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
 470                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 471 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 472 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 473 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 474 #else /* CONFIG_PCI */
 475 #define CONFIG_SYS_IBAT6L       (0)
 476 #define CONFIG_SYS_IBAT6U       (0)
 477 #define CONFIG_SYS_IBAT7L       (0)
 478 #define CONFIG_SYS_IBAT7U       (0)
 479 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 480 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 481 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 482 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 483 #endif /* CONFIG_PCI */
 484
 485 /*
 486  * Internal Definitions
 487  *
 488  * Boot Flags
 489  */
 490 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 491 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 492
 493 #if defined(CONFIG_CMD_KGDB)
 494 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 495 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 496 #endif
 497
 498 /*
 499  * Environment Configuration
 500  */
 501 #define CONFIG_ENV_OVERWRITE
 502
 503 #if defined(CONFIG_UEC_ETH)
 504 #define CONFIG_HAS_ETH0
 505 #define CONFIG_HAS_ETH1
 506 #define CONFIG_HAS_ETH2
 507 #define CONFIG_HAS_ETH3
 508 #define CONFIG_ETHADDR  00:04:9f:ef:01:01
 509 #define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
 510 #define CONFIG_ETH2ADDR 00:04:9f:ef:01:03
 511 #define CONFIG_ETH3ADDR 00:04:9f:ef:01:04
 512 #endif
 513
 514 #define CONFIG_BAUDRATE 115200
 515
 516 #define CONFIG_LOADADDR a00000
 517 #define CONFIG_HOSTNAME mpc8360erdk
 518 #define CONFIG_BOOTFILE uImage
 519
 520 #define CONFIG_IPADDR           10.0.0.99
 521 #define CONFIG_SERVERIP         10.0.0.2
 522 #define CONFIG_GATEWAYIP        10.0.0.2
 523 #define CONFIG_NETMASK          255.255.255.0
 524 #define CONFIG_ROOTPATH         /nfsroot/
 525
 526 #define CONFIG_BOOTDELAY 2      /* -1 disables auto-boot */
 527 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 528
 529 #define CONFIG_EXTRA_ENV_SETTINGS \
 530    "netdev=eth0\0"\
 531    "consoledev=ttyS0\0"\
 532    "loadaddr=a00000\0"\
 533    "fdtaddr=900000\0"\
 534    "fdtfile=dtb\0"\
 535    "fsfile=fs\0"\
 536    "ubootfile=u-boot.bin\0"\
 537    "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
 538    "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
 539                 "$mtdparts panic=1\0"\
 540    "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
 541    "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
 542                 "$gatewayip:$netmask:$hostname:$netdev:off "\
 543                 "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
 544    "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
 545                 "rootfstype=jffs2 rw\0"\
 546    "tftp_get_uboot=tftp 100000 $ubootfile\0"\
 547    "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
 548    "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
 549    "tftp_get_fs=tftp c00000 $fsfile\0"\
 550    "nand_erase_kernel=nand erase 0 400000\0"\
 551    "nand_erase_dtb=nand erase 400000 20000\0"\
 552    "nand_erase_fs=nand erase 420000 3be0000\0"\
 553    "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
 554    "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
 555    "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
 556    "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
 557    "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
 558    "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
 559                 "cp.b 100000 ff800000 $filesize\0"\
 560    "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
 561                 "nand_write_kernel\0"\
 562    "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
 563    "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
 564    "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
 565                 "nand_reflash_fs\0"\
 566    "boot_m=bootm $loadaddr - $fdtaddr\0"\
 567    "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
 568    "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
 569                 "boot_m\0"\
 570    "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
 571                 "boot_m\0"\
 572    ""
 573
 574 #define CONFIG_BOOTCOMMAND "run dhcpboot"
 575
 576 #endif /* __CONFIG_H */