include/configs/MPC837XEMDS.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  * Dave Liu <daveliu@freescale.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #ifndef __CONFIG_H
  22 #define __CONFIG_H
  23
  24 #undef DEBUG
  25
  26 /*
  27  * High Level Configuration Options
  28  */
  29 #define CONFIG_E300             1 /* E300 family */
  30 #define CONFIG_MPC83XX          1 /* MPC83XX family */
  31 #define CONFIG_MPC837X          1 /* MPC837X CPU specific */
  32 #define CONFIG_MPC837XEMDS      1 /* MPC837XEMDS board specific */
  33
  34 /*
  35  * System Clock Setup
  36  */
  37 #ifdef CONFIG_PCISLAVE
  38 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
  39 #else
  40 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
  41 #endif
  42
  43 #ifndef CONFIG_SYS_CLK_FREQ
  44 #define CONFIG_SYS_CLK_FREQ     66000000
  45 #endif
  46
  47 /*
  48  * Hardware Reset Configuration Word
  49  * if CLKIN is 66MHz, then
  50  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
  51  */
  52 #define CFG_HRCW_LOW (\
  53         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  54         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  55         HRCWL_SVCOD_DIV_2 |\
  56         HRCWL_CSB_TO_CLKIN_6X1 |\
  57         HRCWL_CORE_TO_CSB_1_5X1)
  58
  59 #ifdef CONFIG_PCISLAVE
  60 #define CFG_HRCW_HIGH (\
  61         HRCWH_PCI_AGENT |\
  62         HRCWH_PCI1_ARBITER_DISABLE |\
  63         HRCWH_CORE_ENABLE |\
  64         HRCWH_FROM_0XFFF00100 |\
  65         HRCWH_BOOTSEQ_DISABLE |\
  66         HRCWH_SW_WATCHDOG_DISABLE |\
  67         HRCWH_ROM_LOC_LOCAL_16BIT |\
  68         HRCWH_RL_EXT_LEGACY |\
  69         HRCWH_TSEC1M_IN_RGMII |\
  70         HRCWH_TSEC2M_IN_RGMII |\
  71         HRCWH_BIG_ENDIAN |\
  72         HRCWH_LDP_CLEAR)
  73 #else
  74 #define CFG_HRCW_HIGH (\
  75         HRCWH_PCI_HOST |\
  76         HRCWH_PCI1_ARBITER_ENABLE |\
  77         HRCWH_CORE_ENABLE |\
  78         HRCWH_FROM_0X00000100 |\
  79         HRCWH_BOOTSEQ_DISABLE |\
  80         HRCWH_SW_WATCHDOG_DISABLE |\
  81         HRCWH_ROM_LOC_LOCAL_16BIT |\
  82         HRCWH_RL_EXT_LEGACY |\
  83         HRCWH_TSEC1M_IN_RGMII |\
  84         HRCWH_TSEC2M_IN_RGMII |\
  85         HRCWH_BIG_ENDIAN |\
  86         HRCWH_LDP_CLEAR)
  87 #endif
  88
  89 /*
  90  * eTSEC Clock Config
  91  */
  92 #define CFG_SCCR_TSEC1CM        1       /* CSB:eTSEC1 = 1:1 */
  93 #define CFG_SCCR_TSEC2CM        1       /* CSB:eTSEC2 = 1:1 */
  94
  95 /*
  96  * System IO Config
  97  */
  98 #define CFG_SICRH               0x00000000
  99 #define CFG_SICRL               0x00000000
 100
 101 /*
 102  * Output Buffer Impedance
 103  */
 104 #define CFG_OBIR                0x31100000
 105
 106 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 107 #define CONFIG_BOARD_EARLY_INIT_R
 108
 109 /*
 110  * IMMR new address
 111  */
 112 #define CFG_IMMR                0xE0000000
 113
 114 /*
 115  * DDR Setup
 116  */
 117 #define CFG_DDR_BASE            0x00000000 /* DDR is system memory */
 118 #define CFG_SDRAM_BASE          CFG_DDR_BASE
 119 #define CFG_DDR_SDRAM_BASE      CFG_DDR_BASE
 120 #define CFG_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 121 #define CFG_83XX_DDR_USES_CS0
 122 #define CFG_DDRCDR_VALUE        0x80080001 /* ODT 150ohm on SoC */
 123
 124 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 125 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 126
 127 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 128 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
 129
 130 #if defined(CONFIG_SPD_EEPROM)
 131 #define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
 132 #else
 133 /*
 134  * Manually set up DDR parameters
 135  * WHITE ELECTRONIC DESGGNS - W3HG64M72EEU403PD4 SO-DIMM
 136  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
 137  */
 138 #define CFG_DDR_SIZE            512 /* MB */
 139 #define CFG_DDR_CS0_BNDS        0x0000001f
 140 #define CFG_DDR_CS0_CONFIG      ( CSCONFIG_EN \
 141                                 | 0x00010000  /* ODT_WR to CSn */ \
 142                                 | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
 143                                 /* 0x80010202 */
 144 #define CFG_DDR_TIMING_3        0x00000000
 145 #define CFG_DDR_TIMING_0        ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 146                                 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 147                                 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 148                                 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
 149                                 | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
 150                                 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
 151                                 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 152                                 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 153                                 /* 0x00620802 */
 154 #define CFG_DDR_TIMING_1        ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
 155                                 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 156                                 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
 157                                 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
 158                                 | (13 << TIMING_CFG1_REFREC_SHIFT ) \
 159                                 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
 160                                 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 161                                 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 162                                 /* 0x3935d322 */
 163 #define CFG_DDR_TIMING_2        ( ( 2 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 164                                 | ( 6 << TIMING_CFG2_CPO_SHIFT ) \
 165                                 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 166                                 | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 167                                 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 168                                 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 169                                 | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 170                                 /* 0x231088c8 */
 171 #define CFG_DDR_INTERVAL        ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 172                                 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 173                                 /* 0x03E00100 */
 174 #define CFG_DDR_SDRAM_CFG       0x43000000
 175 #define CFG_DDR_SDRAM_CFG2      0x00001000 /* 1 posted refresh */
 176 #define CFG_DDR_MODE            ( ( 0x0450 << SDRAM_MODE_ESD_SHIFT ) \
 177                                 | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
 178                                 /* ODT 150ohm CL=3, AL=2 on SDRAM */
 179 #define CFG_DDR_MODE2           0x00000000
 180 #endif
 181
 182 /*
 183  * Memory test
 184  */
 185 #undef CFG_DRAM_TEST            /* memory test, takes time */
 186 #define CFG_MEMTEST_START       0x00040000 /* memtest region */
 187 #define CFG_MEMTEST_END         0x00140000
 188
 189 /*
 190  * The reserved memory
 191  */
 192 #define CFG_MONITOR_BASE        TEXT_BASE /* start of monitor */
 193
 194 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 195 #define CFG_RAMBOOT
 196 #else
 197 #undef CFG_RAMBOOT
 198 #endif
 199
 200 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 201 #define CFG_MALLOC_LEN          (512 * 1024) /* Reserved for malloc */
 202
 203 /*
 204  * Initial RAM Base Address Setup
 205  */
 206 #define CFG_INIT_RAM_LOCK       1
 207 #define CFG_INIT_RAM_ADDR       0xE6000000 /* Initial RAM address */
 208 #define CFG_INIT_RAM_END        0x1000 /* End of used area in RAM */
 209 #define CFG_GBL_DATA_SIZE       0x100 /* num bytes initial data */
 210 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 211
 212 /*
 213  * Local Bus Configuration & Clock Setup
 214  */
 215 #define CFG_LCRR                (LCRR_DBYP | LCRR_CLKDIV_8)
 216 #define CFG_LBC_LBCR            0x00000000
 217
 218 /*
 219  * FLASH on the Local Bus
 220  */
 221 #define CFG_FLASH_CFI           /* use the Common Flash Interface */
 222 #define CFG_FLASH_CFI_DRIVER    /* use the CFI driver */
 223 #define CFG_FLASH_BASE          0xFE000000 /* FLASH base address */
 224 #define CFG_FLASH_SIZE          32 /* max FLASH size is 32M */
 225
 226 #define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE /* Window base at flash base */
 227 #define CFG_LBLAWAR0_PRELIM     0x80000018 /* 32MB window size */
 228
 229 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE | /* Flash Base address */ \
 230                                 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 231                                 BR_V) /* valid */
 232 #define CFG_OR0_PRELIM          ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 233                                 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 234                                 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 235
 236 #define CFG_MAX_FLASH_BANKS     1 /* number of banks */
 237 #define CFG_MAX_FLASH_SECT      256 /* max sectors per device */
 238
 239 #undef CFG_FLASH_CHECKSUM
 240 #define CFG_FLASH_ERASE_TOUT    60000 /* Flash Erase Timeout (ms) */
 241 #define CFG_FLASH_WRITE_TOUT    500 /* Flash Write Timeout (ms) */
 242
 243 /*
 244  * BCSR on the Local Bus
 245  */
 246 #define CFG_BCSR                0xF8000000
 247 #define CFG_LBLAWBAR1_PRELIM    CFG_BCSR /* Access window base at BCSR base */
 248 #define CFG_LBLAWAR1_PRELIM     0x8000000E /* Access window size 32K */
 249
 250 #define CFG_BR1_PRELIM          (CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
 251 #define CFG_OR1_PRELIM          0xFFFFE9f7 /* length 32K */
 252
 253 /*
 254  * NAND Flash on the Local Bus
 255  */
 256 #define CFG_NAND_BASE           0xE0600000      /* 0xE0600000 */
 257 #define CFG_BR3_PRELIM          ( CFG_NAND_BASE \
 258                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 259                                 | BR_PS_8               /* Port Size = 8 bit */ \
 260                                 | BR_MS_FCM             /* MSEL = FCM */ \
 261                                 | BR_V )                /* valid */
 262 #define CFG_OR3_PRELIM          ( 0xFFFF8000            /* length 32K */ \
 263                                 | OR_FCM_CSCT \
 264                                 | OR_FCM_CST \
 265                                 | OR_FCM_CHT \
 266                                 | OR_FCM_SCY_1 \
 267                                 | OR_FCM_TRLX \
 268                                 | OR_FCM_EHTR )
 269                                 /* 0xFFFF8396 */
 270
 271 #define CFG_LBLAWBAR3_PRELIM    CFG_NAND_BASE
 272 #define CFG_LBLAWAR3_PRELIM     0x8000000E      /* 32KB  */
 273
 274 /*
 275  * Serial Port
 276  */
 277 #define CONFIG_CONS_INDEX       1
 278 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 279 #define CFG_NS16550
 280 #define CFG_NS16550_SERIAL
 281 #define CFG_NS16550_REG_SIZE    1
 282 #define CFG_NS16550_CLK         get_bus_freq(0)
 283
 284 #define CFG_BAUDRATE_TABLE  \
 285         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 286
 287 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
 288 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 289
 290 /* Use the HUSH parser */
 291 #define CFG_HUSH_PARSER
 292 #ifdef CFG_HUSH_PARSER
 293 #define CFG_PROMPT_HUSH_PS2 "> "
 294 #endif
 295
 296 /* Pass open firmware flat tree */
 297 #define CONFIG_OF_LIBFDT        1
 298 #define CONFIG_OF_BOARD_SETUP   1
 299 #define CONFIG_OF_HAS_BD_T      1
 300 #define CONFIG_OF_HAS_UBOOT_ENV 1
 301
 302 #define OF_CPU                  "PowerPC,837x@0"
 303 #define OF_SOC                  "soc837x@e0000000"
 304 #define OF_TBCLK                (bd->bi_busfreq / 4)
 305 #define OF_STDOUT_PATH          "/soc837x@e0000000/serial@4500"
 306
 307 /* I2C */
 308 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 309 #undef CONFIG_SOFT_I2C          /* I2C bit-banged */
 310 #define CONFIG_FSL_I2C
 311 #define CFG_I2C_SPEED           400000 /* I2C speed and slave address */
 312 #define CFG_I2C_SLAVE           0x7F
 313 #define CFG_I2C_NOPROBES        {0x51} /* Don't probe these addrs */
 314 #define CFG_I2C_OFFSET          0x3000
 315 #define CFG_I2C2_OFFSET         0x3100
 316
 317 /*
 318  * Config on-board RTC
 319  */
 320 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 321 #define CFG_I2C_RTC_ADDR        0x68 /* at address 0x68 */
 322
 323 /*
 324  * General PCI
 325  * Addresses are mapped 1-1.
 326  */
 327 #define CFG_PCI_MEM_BASE        0x80000000
 328 #define CFG_PCI_MEM_PHYS        CFG_PCI_MEM_BASE
 329 #define CFG_PCI_MEM_SIZE        0x10000000 /* 256M */
 330 #define CFG_PCI_MMIO_BASE       0x90000000
 331 #define CFG_PCI_MMIO_PHYS       CFG_PCI_MMIO_BASE
 332 #define CFG_PCI_MMIO_SIZE       0x10000000 /* 256M */
 333 #define CFG_PCI_IO_BASE         0xE0300000
 334 #define CFG_PCI_IO_PHYS         0xE0300000
 335 #define CFG_PCI_IO_SIZE         0x100000 /* 1M */
 336
 337 #define CFG_PCI_SLV_MEM_LOCAL   CFG_SDRAM_BASE
 338 #define CFG_PCI_SLV_MEM_BUS     0x00000000
 339 #define CFG_PCI_SLV_MEM_SIZE    0x80000000
 340
 341 #ifdef CONFIG_PCI
 342 #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
 343 #define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */
 344
 345 #define CONFIG_NET_MULTI
 346 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 347
 348 #undef CONFIG_EEPRO100
 349 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 350 #define CFG_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 351 #endif /* CONFIG_PCI */
 352
 353 #ifndef CONFIG_NET_MULTI
 354 #define CONFIG_NET_MULTI        1
 355 #endif
 356
 357 /*
 358  * TSEC
 359  */
 360 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 361 #define CFG_TSEC1_OFFSET        0x24000
 362 #define CFG_TSEC1               (CFG_IMMR+CFG_TSEC1_OFFSET)
 363 #define CFG_TSEC2_OFFSET        0x25000
 364 #define CFG_TSEC2               (CFG_IMMR+CFG_TSEC2_OFFSET)
 365
 366 /*
 367  * TSEC ethernet configuration
 368  */
 369 #define CONFIG_MII              1 /* MII PHY management */
 370 #define CONFIG_TSEC1            1
 371 #define CONFIG_TSEC1_NAME       "eTSEC0"
 372 #define CONFIG_TSEC2            1
 373 #define CONFIG_TSEC2_NAME       "eTSEC1"
 374 #define TSEC1_PHY_ADDR          2
 375 #define TSEC2_PHY_ADDR          3
 376 #define TSEC1_PHYIDX            0
 377 #define TSEC2_PHYIDX            0
 378 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 379 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 380
 381 /* Options are: TSEC[0-1] */
 382 #define CONFIG_ETHPRIME         "eTSEC1"
 383
 384 /*
 385  * Environment
 386  */
 387 #ifndef CFG_RAMBOOT
 388         #define CFG_ENV_IS_IN_FLASH     1
 389         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 390         #define CFG_ENV_SECT_SIZE       0x20000 /* 128K(one sector) for env */
 391         #define CFG_ENV_SIZE            0x2000
 392 #else
 393         #define CFG_NO_FLASH            1       /* Flash is not usable now */
 394         #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only */
 395         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
 396         #define CFG_ENV_SIZE            0x2000
 397 #endif
 398
 399 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 400 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 401
 402 /*
 403  * BOOTP options
 404  */
 405 #define CONFIG_BOOTP_BOOTFILESIZE
 406 #define CONFIG_BOOTP_BOOTPATH
 407 #define CONFIG_BOOTP_GATEWAY
 408 #define CONFIG_BOOTP_HOSTNAME
 409
 410
 411 /*
 412  * Command line configuration.
 413  */
 414 #include <config_cmd_default.h>
 415
 416 #define CONFIG_CMD_PING
 417 #define CONFIG_CMD_I2C
 418 #define CONFIG_CMD_MII
 419 #define CONFIG_CMD_DATE
 420
 421 #if defined(CONFIG_PCI)
 422     #define CONFIG_CMD_PCI
 423 #endif
 424
 425 #if defined(CFG_RAMBOOT)
 426     #undef CONFIG_CMD_ENV
 427     #undef CONFIG_CMD_LOADS
 428 #endif
 429
 430 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 431
 432 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 433
 434 /*
 435  * Miscellaneous configurable options
 436  */
 437 #define CFG_LONGHELP            /* undef to save memory */
 438 #define CFG_LOAD_ADDR           0x2000000 /* default load address */
 439 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
 440
 441 #if defined(CONFIG_CMD_KGDB)
 442         #define CFG_CBSIZE      1024 /* Console I/O Buffer Size */
 443 #else
 444         #define CFG_CBSIZE      256 /* Console I/O Buffer Size */
 445 #endif
 446
 447 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 448 #define CFG_MAXARGS     16              /* max number of command args */
 449 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 450 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 451
 452 /*
 453  * For booting Linux, the board info and command line data
 454  * have to be in the first 8 MB of memory, since this is
 455  * the maximum mapped by the Linux kernel during initialization.
 456  */
 457 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 458
 459 /*
 460  * Core HID Setup
 461  */
 462 #define CFG_HID0_INIT           0x000000000
 463 #define CFG_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
 464 #define CFG_HID2                HID2_HBE
 465
 466 /*
 467  * Cache Config
 468  */
 469 #define CFG_DCACHE_SIZE         32768
 470 #define CFG_CACHELINE_SIZE      32
 471 #if defined(CONFIG_CMD_KGDB)
 472 #define CFG_CACHELINE_SHIFT     5 /*log base 2 of the above value */
 473 #endif
 474
 475 /*
 476  * MMU Setup
 477  */
 478
 479 /* DDR: cache cacheable */
 480 #define CFG_SDRAM_LOWER         CFG_SDRAM_BASE
 481 #define CFG_SDRAM_UPPER         (CFG_SDRAM_BASE + 0x10000000)
 482
 483 #define CFG_IBAT0L      (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
 484 #define CFG_IBAT0U      (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
 485 #define CFG_DBAT0L      CFG_IBAT0L
 486 #define CFG_DBAT0U      CFG_IBAT0U
 487
 488 #define CFG_IBAT1L      (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
 489 #define CFG_IBAT1U      (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
 490 #define CFG_DBAT1L      CFG_IBAT1L
 491 #define CFG_DBAT1U      CFG_IBAT1U
 492
 493 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 494 #define CFG_IBAT2L      (CFG_IMMR | BATL_PP_10 | \
 495                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 496 #define CFG_IBAT2U      (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
 497 #define CFG_DBAT2L      CFG_IBAT2L
 498 #define CFG_DBAT2U      CFG_IBAT2U
 499
 500 /* BCSR: cache-inhibit and guarded */
 501 #define CFG_IBAT3L      (CFG_BCSR | BATL_PP_10 | \
 502                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 503 #define CFG_IBAT3U      (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
 504 #define CFG_DBAT3L      CFG_IBAT3L
 505 #define CFG_DBAT3U      CFG_IBAT3U
 506
 507 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 508 #define CFG_IBAT4L      (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 509 #define CFG_IBAT4U      (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 510 #define CFG_DBAT4L      (CFG_FLASH_BASE | BATL_PP_10 | \
 511                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 512 #define CFG_DBAT4U      CFG_IBAT4U
 513
 514 /* Stack in dcache: cacheable, no memory coherence */
 515 #define CFG_IBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_10)
 516 #define CFG_IBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 517 #define CFG_DBAT5L      CFG_IBAT5L
 518 #define CFG_DBAT5U      CFG_IBAT5U
 519
 520 #ifdef CONFIG_PCI
 521 /* PCI MEM space: cacheable */
 522 #define CFG_IBAT6L      (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 523 #define CFG_IBAT6U      (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 524 #define CFG_DBAT6L      CFG_IBAT6L
 525 #define CFG_DBAT6U      CFG_IBAT6U
 526 /* PCI MMIO space: cache-inhibit and guarded */
 527 #define CFG_IBAT7L      (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
 528                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 529 #define CFG_IBAT7U      (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 530 #define CFG_DBAT7L      CFG_IBAT7L
 531 #define CFG_DBAT7U      CFG_IBAT7U
 532 #else
 533 #define CFG_IBAT6L      (0)
 534 #define CFG_IBAT6U      (0)
 535 #define CFG_IBAT7L      (0)
 536 #define CFG_IBAT7U      (0)
 537 #define CFG_DBAT6L      CFG_IBAT6L
 538 #define CFG_DBAT6U      CFG_IBAT6U
 539 #define CFG_DBAT7L      CFG_IBAT7L
 540 #define CFG_DBAT7U      CFG_IBAT7U
 541 #endif
 542
 543 /*
 544  * Internal Definitions
 545  *
 546  * Boot Flags
 547  */
 548 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 549 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 550
 551 #if defined(CONFIG_CMD_KGDB)
 552 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 553 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 554 #endif
 555
 556 /*
 557  * Environment Configuration
 558  */
 559
 560 #define CONFIG_ENV_OVERWRITE
 561
 562 #if defined(CONFIG_TSEC_ENET)
 563 #define CONFIG_HAS_ETH0
 564 #define CONFIG_ETHADDR          00:E0:0C:00:83:79
 565 #define CONFIG_HAS_ETH1
 566 #define CONFIG_ETH1ADDR         00:E0:0C:00:83:78
 567 #endif
 568
 569 #define CONFIG_BAUDRATE 115200
 570
 571 #define CONFIG_LOADADDR 200000  /* default location for tftp and bootm */
 572
 573 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 574 #undef CONFIG_BOOTARGS          /* the boot command will set bootargs */
 575
 576 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 577    "netdev=eth0\0"                                                      \
 578    "consoledev=ttyS0\0"                                                 \
 579    "ramdiskaddr=1000000\0"                                              \
 580    "ramdiskfile=ramfs.83xx\0"                                           \
 581    "fdtaddr=400000\0"                                                   \
 582    "fdtfile=mpc837xemds.dtb\0"                                          \
 583    ""
 584
 585 #define CONFIG_NFSBOOTCOMMAND                                           \
 586    "setenv bootargs root=/dev/nfs rw "                                  \
 587       "nfsroot=$serverip:$rootpath "                                    \
 588       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 589       "console=$consoledev,$baudrate $othbootargs;"                     \
 590    "tftp $loadaddr $bootfile;"                                          \
 591    "tftp $fdtaddr $fdtfile;"                                            \
 592    "bootm $loadaddr - $fdtaddr"
 593
 594 #define CONFIG_RAMBOOTCOMMAND                                           \
 595    "setenv bootargs root=/dev/ram rw "                                  \
 596       "console=$consoledev,$baudrate $othbootargs;"                     \
 597    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 598    "tftp $loadaddr $bootfile;"                                          \
 599    "tftp $fdtaddr $fdtfile;"                                            \
 600    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 601
 602
 603 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 604
 605 #endif  /* __CONFIG_H */