include/configs/MPC837XEMDS.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  * Dave Liu <daveliu@freescale.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #ifndef __CONFIG_H
  22 #define __CONFIG_H
  23
  24 /*
  25  * High Level Configuration Options
  26  */
  27 #define CONFIG_E300             1 /* E300 family */
  28 #define CONFIG_MPC83XX          1 /* MPC83XX family */
  29 #define CONFIG_MPC837X          1 /* MPC837X CPU specific */
  30 #define CONFIG_MPC837XEMDS      1 /* MPC837XEMDS board specific */
  31
  32 /*
  33  * System Clock Setup
  34  */
  35 #ifdef CONFIG_PCISLAVE
  36 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
  37 #else
  38 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
  39 #endif
  40
  41 #ifndef CONFIG_SYS_CLK_FREQ
  42 #define CONFIG_SYS_CLK_FREQ     66000000
  43 #endif
  44
  45 /*
  46  * Hardware Reset Configuration Word
  47  * if CLKIN is 66MHz, then
  48  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
  49  */
  50 #define CONFIG_SYS_HRCW_LOW (\
  51         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  52         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  53         HRCWL_SVCOD_DIV_2 |\
  54         HRCWL_CSB_TO_CLKIN_6X1 |\
  55         HRCWL_CORE_TO_CSB_1_5X1)
  56
  57 #ifdef CONFIG_PCISLAVE
  58 #define CONFIG_SYS_HRCW_HIGH (\
  59         HRCWH_PCI_AGENT |\
  60         HRCWH_PCI1_ARBITER_DISABLE |\
  61         HRCWH_CORE_ENABLE |\
  62         HRCWH_FROM_0XFFF00100 |\
  63         HRCWH_BOOTSEQ_DISABLE |\
  64         HRCWH_SW_WATCHDOG_DISABLE |\
  65         HRCWH_ROM_LOC_LOCAL_16BIT |\
  66         HRCWH_RL_EXT_LEGACY |\
  67         HRCWH_TSEC1M_IN_RGMII |\
  68         HRCWH_TSEC2M_IN_RGMII |\
  69         HRCWH_BIG_ENDIAN |\
  70         HRCWH_LDP_CLEAR)
  71 #else
  72 #define CONFIG_SYS_HRCW_HIGH (\
  73         HRCWH_PCI_HOST |\
  74         HRCWH_PCI1_ARBITER_ENABLE |\
  75         HRCWH_CORE_ENABLE |\
  76         HRCWH_FROM_0X00000100 |\
  77         HRCWH_BOOTSEQ_DISABLE |\
  78         HRCWH_SW_WATCHDOG_DISABLE |\
  79         HRCWH_ROM_LOC_LOCAL_16BIT |\
  80         HRCWH_RL_EXT_LEGACY |\
  81         HRCWH_TSEC1M_IN_RGMII |\
  82         HRCWH_TSEC2M_IN_RGMII |\
  83         HRCWH_BIG_ENDIAN |\
  84         HRCWH_LDP_CLEAR)
  85 #endif
  86
  87 /* Arbiter Configuration Register */
  88 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth is 4 */
  89 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count is 4 */
  90
  91 /* System Priority Control Register */
  92 #define CONFIG_SYS_SPCR_TSECEP          3       /* eTSEC1/2 emergency has highest priority */
  93
  94 /*
  95  * IP blocks clock configuration
  96  */
  97 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* CSB:eTSEC1 = 1:1 */
  98 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* CSB:eTSEC2 = 1:1 */
  99 #define CONFIG_SYS_SCCR_SATACM          SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */
 100
 101 /*
 102  * System IO Config
 103  */
 104 #define CONFIG_SYS_SICRH                0x00000000
 105 #define CONFIG_SYS_SICRL                0x00000000
 106
 107 /*
 108  * Output Buffer Impedance
 109  */
 110 #define CONFIG_SYS_OBIR         0x31100000
 111
 112 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 113 #define CONFIG_BOARD_EARLY_INIT_R
 114
 115 /*
 116  * IMMR new address
 117  */
 118 #define CONFIG_SYS_IMMR         0xE0000000
 119
 120 /*
 121  * DDR Setup
 122  */
 123 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 124 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 125 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 126 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 127 #define CONFIG_SYS_83XX_DDR_USES_CS0
 128 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */
 129
 130 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 131 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 132
 133 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 134 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
 135
 136 #if defined(CONFIG_SPD_EEPROM)
 137 #define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
 138 #else
 139 /*
 140  * Manually set up DDR parameters
 141  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
 142  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
 143  */
 144 #define CONFIG_SYS_DDR_SIZE             512 /* MB */
 145 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
 146 #define CONFIG_SYS_DDR_CS0_CONFIG       ( CSCONFIG_EN \
 147                                 | 0x00010000  /* ODT_WR to CSn */ \
 148                                 | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
 149                                 /* 0x80010202 */
 150 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 151 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 152                                 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 153                                 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 154                                 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
 155                                 | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
 156                                 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
 157                                 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 158                                 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 159                                 /* 0x00620802 */
 160 #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
 161                                 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 162                                 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
 163                                 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
 164                                 | (13 << TIMING_CFG1_REFREC_SHIFT ) \
 165                                 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
 166                                 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 167                                 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 168                                 /* 0x3935d322 */
 169 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 170                                 | ( 6 << TIMING_CFG2_CPO_SHIFT ) \
 171                                 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 172                                 | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 173                                 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 174                                 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 175                                 | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 176                                 /* 0x131088c8 */
 177 #define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 178                                 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 179                                 /* 0x03E00100 */
 180 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 181 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 182 #define CONFIG_SYS_DDR_MODE             ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
 183                                 | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
 184                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 185 #define CONFIG_SYS_DDR_MODE2            0x00000000
 186 #endif
 187
 188 /*
 189  * Memory test
 190  */
 191 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 192 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 193 #define CONFIG_SYS_MEMTEST_END          0x00140000
 194
 195 /*
 196  * The reserved memory
 197  */
 198 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 199
 200 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 201 #define CONFIG_SYS_RAMBOOT
 202 #else
 203 #undef CONFIG_SYS_RAMBOOT
 204 #endif
 205
 206 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 207 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 208 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024) /* Reserved for malloc */
 209
 210 /*
 211  * Initial RAM Base Address Setup
 212  */
 213 #define CONFIG_SYS_INIT_RAM_LOCK        1
 214 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 215 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 216 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 217 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 218
 219 /*
 220  * Local Bus Configuration & Clock Setup
 221  */
 222 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_CLKDIV_8)
 223 #define CONFIG_SYS_LBC_LBCR             0x00000000
 224
 225 /*
 226  * FLASH on the Local Bus
 227  */
 228 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 229 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 230 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 231 #define CONFIG_SYS_FLASH_SIZE           32 /* max FLASH size is 32M */
 232 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
 233
 234 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 235 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018 /* 32MB window size */
 236
 237 #define CONFIG_SYS_BR0_PRELIM           ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
 238                                 | (2 << BR_PS_SHIFT)    /* 16 bit port size */ \
 239                                 | BR_V )                /* valid */
 240 #define CONFIG_SYS_OR0_PRELIM           ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 241                                 | OR_UPM_XAM \
 242                                 | OR_GPCM_CSNT \
 243                                 | OR_GPCM_ACS_DIV2 \
 244                                 | OR_GPCM_XACS \
 245                                 | OR_GPCM_SCY_15 \
 246                                 | OR_GPCM_TRLX \
 247                                 | OR_GPCM_EHTR \
 248                                 | OR_GPCM_EAD )
 249                                 /* 0xFE000FF7 */
 250
 251 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 252 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 253
 254 #undef CONFIG_SYS_FLASH_CHECKSUM
 255 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 256 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 257
 258 /*
 259  * BCSR on the Local Bus
 260  */
 261 #define CONFIG_SYS_BCSR         0xF8000000
 262 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR /* Access window base at BCSR base */
 263 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E /* Access window size 32K */
 264
 265 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
 266 #define CONFIG_SYS_OR1_PRELIM           0xFFFFE9f7 /* length 32K */
 267
 268 /*
 269  * NAND Flash on the Local Bus
 270  */
 271 #define CONFIG_SYS_NAND_BASE            0xE0600000      /* 0xE0600000 */
 272 #define CONFIG_SYS_BR3_PRELIM           ( CONFIG_SYS_NAND_BASE \
 273                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 274                                 | BR_PS_8               /* Port Size = 8 bit */ \
 275                                 | BR_MS_FCM             /* MSEL = FCM */ \
 276                                 | BR_V )                /* valid */
 277 #define CONFIG_SYS_OR3_PRELIM           ( 0xFFFF8000            /* length 32K */ \
 278                                 | OR_FCM_CSCT \
 279                                 | OR_FCM_CST \
 280                                 | OR_FCM_CHT \
 281                                 | OR_FCM_SCY_1 \
 282                                 | OR_FCM_TRLX \
 283                                 | OR_FCM_EHTR )
 284                                 /* 0xFFFF8396 */
 285
 286 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_NAND_BASE
 287 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000E      /* 32KB  */
 288
 289 /*
 290  * Serial Port
 291  */
 292 #define CONFIG_CONS_INDEX       1
 293 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 294 #define CONFIG_SYS_NS16550
 295 #define CONFIG_SYS_NS16550_SERIAL
 296 #define CONFIG_SYS_NS16550_REG_SIZE     1
 297 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 298
 299 #define CONFIG_SYS_BAUDRATE_TABLE  \
 300         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 301
 302 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 303 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 304
 305 /* Use the HUSH parser */
 306 #define CONFIG_SYS_HUSH_PARSER
 307 #ifdef CONFIG_SYS_HUSH_PARSER
 308 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 309 #endif
 310
 311 /* Pass open firmware flat tree */
 312 #define CONFIG_OF_LIBFDT        1
 313 #define CONFIG_OF_BOARD_SETUP   1
 314 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 315
 316 /* I2C */
 317 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 318 #undef CONFIG_SOFT_I2C          /* I2C bit-banged */
 319 #define CONFIG_FSL_I2C
 320 #define CONFIG_SYS_I2C_SPEED            400000 /* I2C speed and slave address */
 321 #define CONFIG_SYS_I2C_SLAVE            0x7F
 322 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
 323 #define CONFIG_SYS_I2C_OFFSET           0x3000
 324 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 325
 326 /*
 327  * Config on-board RTC
 328  */
 329 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 330 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 331
 332 /*
 333  * General PCI
 334  * Addresses are mapped 1-1.
 335  */
 336 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
 337 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
 338 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
 339 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 340 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 341 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 342 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 343 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 344 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 345
 346 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 347 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 348 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 349
 350 #ifdef CONFIG_PCI
 351 #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
 352 #define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */
 353
 354 #define CONFIG_NET_MULTI
 355 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 356
 357 #undef CONFIG_EEPRO100
 358 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 359 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 360 #endif /* CONFIG_PCI */
 361
 362 #ifndef CONFIG_NET_MULTI
 363 #define CONFIG_NET_MULTI        1
 364 #endif
 365
 366 /*
 367  * TSEC
 368  */
 369 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 370 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 371 #define CONFIG_SYS_TSEC1                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 372 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 373 #define CONFIG_SYS_TSEC2                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 374
 375 /*
 376  * TSEC ethernet configuration
 377  */
 378 #define CONFIG_MII              1 /* MII PHY management */
 379 #define CONFIG_TSEC1            1
 380 #define CONFIG_TSEC1_NAME       "eTSEC0"
 381 #define CONFIG_TSEC2            1
 382 #define CONFIG_TSEC2_NAME       "eTSEC1"
 383 #define TSEC1_PHY_ADDR          2
 384 #define TSEC2_PHY_ADDR          3
 385 #define TSEC1_PHYIDX            0
 386 #define TSEC2_PHYIDX            0
 387 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 388 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 389
 390 /* Options are: TSEC[0-1] */
 391 #define CONFIG_ETHPRIME         "eTSEC1"
 392
 393 /* SERDES */
 394 #define CONFIG_FSL_SERDES
 395 #define CONFIG_FSL_SERDES1      0xe3000
 396 #define CONFIG_FSL_SERDES2      0xe3100
 397
 398 /*
 399  * SATA
 400  */
 401 #define CONFIG_LIBATA
 402 #define CONFIG_FSL_SATA
 403
 404 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 405 #define CONFIG_SATA1
 406 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 407 #define CONFIG_SYS_SATA1                (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 408 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 409 #define CONFIG_SATA2
 410 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 411 #define CONFIG_SYS_SATA2                (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 412 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 413
 414 #ifdef CONFIG_FSL_SATA
 415 #define CONFIG_LBA48
 416 #define CONFIG_CMD_SATA
 417 #define CONFIG_DOS_PARTITION
 418 #define CONFIG_CMD_EXT2
 419 #endif
 420
 421 /*
 422  * Environment
 423  */
 424 #ifndef CONFIG_SYS_RAMBOOT
 425         #define CONFIG_ENV_IS_IN_FLASH  1
 426         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 427         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 428         #define CONFIG_ENV_SIZE         0x2000
 429 #else
 430         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 431         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 432         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 433         #define CONFIG_ENV_SIZE         0x2000
 434 #endif
 435
 436 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 437 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 438
 439 /*
 440  * BOOTP options
 441  */
 442 #define CONFIG_BOOTP_BOOTFILESIZE
 443 #define CONFIG_BOOTP_BOOTPATH
 444 #define CONFIG_BOOTP_GATEWAY
 445 #define CONFIG_BOOTP_HOSTNAME
 446
 447
 448 /*
 449  * Command line configuration.
 450  */
 451 #include <config_cmd_default.h>
 452
 453 #define CONFIG_CMD_PING
 454 #define CONFIG_CMD_I2C
 455 #define CONFIG_CMD_MII
 456 #define CONFIG_CMD_DATE
 457
 458 #if defined(CONFIG_PCI)
 459     #define CONFIG_CMD_PCI
 460 #endif
 461
 462 #if defined(CONFIG_SYS_RAMBOOT)
 463     #undef CONFIG_CMD_ENV
 464     #undef CONFIG_CMD_LOADS
 465 #endif
 466
 467 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 468
 469 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 470
 471 /*
 472  * Miscellaneous configurable options
 473  */
 474 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 475 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 476 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 477
 478 #if defined(CONFIG_CMD_KGDB)
 479         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 480 #else
 481         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 482 #endif
 483
 484 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 485 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 486 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 487 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 488
 489 /*
 490  * For booting Linux, the board info and command line data
 491  * have to be in the first 8 MB of memory, since this is
 492  * the maximum mapped by the Linux kernel during initialization.
 493  */
 494 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 495
 496 /*
 497  * Core HID Setup
 498  */
 499 #define CONFIG_SYS_HID0_INIT            0x000000000
 500 #define CONFIG_SYS_HID0_FINAL           HID0_ENABLE_MACHINE_CHECK
 501 #define CONFIG_SYS_HID2         HID2_HBE
 502
 503 /*
 504  * MMU Setup
 505  */
 506 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 507
 508 /* DDR: cache cacheable */
 509 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
 510 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 511
 512 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
 513 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
 514 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 515 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 516
 517 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
 518 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
 519 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 520 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 521
 522 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 523 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 524                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 525 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
 526 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 527 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 528
 529 /* BCSR: cache-inhibit and guarded */
 530 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_BCSR | BATL_PP_10 | \
 531                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 532 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
 533 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 534 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 535
 536 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 537 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 538 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 539 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 540                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 541 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 542
 543 /* Stack in dcache: cacheable, no memory coherence */
 544 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 545 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 546 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 547 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 548
 549 #ifdef CONFIG_PCI
 550 /* PCI MEM space: cacheable */
 551 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 552 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 553 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 554 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 555 /* PCI MMIO space: cache-inhibit and guarded */
 556 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
 557                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 558 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 559 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 560 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 561 #else
 562 #define CONFIG_SYS_IBAT6L       (0)
 563 #define CONFIG_SYS_IBAT6U       (0)
 564 #define CONFIG_SYS_IBAT7L       (0)
 565 #define CONFIG_SYS_IBAT7U       (0)
 566 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 567 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 568 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 569 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 570 #endif
 571
 572 /*
 573  * Internal Definitions
 574  *
 575  * Boot Flags
 576  */
 577 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 578 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 579
 580 #if defined(CONFIG_CMD_KGDB)
 581 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 582 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 583 #endif
 584
 585 /*
 586  * Environment Configuration
 587  */
 588
 589 #define CONFIG_ENV_OVERWRITE
 590
 591 #if defined(CONFIG_TSEC_ENET)
 592 #define CONFIG_HAS_ETH0
 593 #define CONFIG_ETHADDR          00:E0:0C:00:83:79
 594 #define CONFIG_HAS_ETH1
 595 #define CONFIG_ETH1ADDR         00:E0:0C:00:83:78
 596 #endif
 597
 598 #define CONFIG_BAUDRATE 115200
 599
 600 #define CONFIG_LOADADDR 500000  /* default location for tftp and bootm */
 601
 602 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 603 #undef CONFIG_BOOTARGS          /* the boot command will set bootargs */
 604
 605 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 606    "netdev=eth0\0"                                                      \
 607    "consoledev=ttyS0\0"                                                 \
 608    "ramdiskaddr=1000000\0"                                              \
 609    "ramdiskfile=ramfs.83xx\0"                                           \
 610    "fdtaddr=400000\0"                                                   \
 611    "fdtfile=mpc8379_mds.dtb\0"                                          \
 612    ""
 613
 614 #define CONFIG_NFSBOOTCOMMAND                                           \
 615    "setenv bootargs root=/dev/nfs rw "                                  \
 616       "nfsroot=$serverip:$rootpath "                                    \
 617       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 618       "console=$consoledev,$baudrate $othbootargs;"                     \
 619    "tftp $loadaddr $bootfile;"                                          \
 620    "tftp $fdtaddr $fdtfile;"                                            \
 621    "bootm $loadaddr - $fdtaddr"
 622
 623 #define CONFIG_RAMBOOTCOMMAND                                           \
 624    "setenv bootargs root=/dev/ram rw "                                  \
 625       "console=$consoledev,$baudrate $othbootargs;"                     \
 626    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 627    "tftp $loadaddr $bootfile;"                                          \
 628    "tftp $fdtaddr $fdtfile;"                                            \
 629    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 630
 631
 632 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 633
 634 #endif  /* __CONFIG_H */