include/configs/MPC8536DS.h

   1 /*
   2  * Copyright 2007-2009,2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8536ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #include "../board/freescale/common/ics307_clk.h"
  31
  32 #ifdef CONFIG_MK_36BIT
  33 #define CONFIG_PHYS_64BIT       1
  34 #endif
  35
  36 #ifdef CONFIG_MK_NAND
  37 #define CONFIG_NAND_U_BOOT              1
  38 #define CONFIG_RAMBOOT_NAND             1
  39 #define CONFIG_RAMBOOT_TEXT_BASE        0xf8f82000
  40 #endif
  41
  42 #ifdef CONFIG_MK_SDCARD
  43 #define CONFIG_RAMBOOT_SDCARD           1
  44 #define CONFIG_RAMBOOT_TEXT_BASE        0xf8f80000
  45 #endif
  46
  47 #ifdef CONFIG_MK_SPIFLASH
  48 #define CONFIG_RAMBOOT_SPIFLASH         1
  49 #define CONFIG_RAMBOOT_TEXT_BASE        0xf8f80000
  50 #endif
  51
  52 /* High Level Configuration Options */
  53 #define CONFIG_BOOKE            1       /* BOOKE */
  54 #define CONFIG_E500             1       /* BOOKE e500 family */
  55 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  56 #define CONFIG_MPC8536          1
  57 #define CONFIG_MPC8536DS        1
  58
  59 #define CONFIG_FSL_ELBC         1       /* Has Enhanced localbus controller */
  60 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  61 #define CONFIG_PCI1             1       /* Enable PCI controller 1 */
  62 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  63 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  64 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  65 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  66 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  67 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  68 #define CONFIG_SYS_HAS_SERDES           /* has SERDES */
  69
  70 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  71 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
  72
  73 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  74 #define CONFIG_ENV_OVERWRITE
  75
  76 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  77 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  78 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  79
  80 /*
  81  * These can be toggled for performance analysis, otherwise use default.
  82  */
  83 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  84 #define CONFIG_BTB                      /* toggle branch predition */
  85
  86 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  87
  88 #define CONFIG_ENABLE_36BIT_PHYS        1
  89
  90 #ifdef CONFIG_PHYS_64BIT
  91 #define CONFIG_ADDR_MAP                 1
  92 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  93 #endif
  94
  95 #define CONFIG_SYS_MEMTEST_START 0x00010000     /* skip exception vectors */
  96 #define CONFIG_SYS_MEMTEST_END   0x1f000000     /* skip u-boot at top of RAM */
  97 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  98
  99 /*
 100  * Config the L2 Cache as L2 SRAM
 101  */
 102 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 103 #ifdef CONFIG_PHYS_64BIT
 104 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 105 #else
 106 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 107 #endif
 108 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 109 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 110
 111 /*
 112  * Base addresses -- Note these are effective addresses where the
 113  * actual resources get mapped (not physical addresses)
 114  */
 115 #define CONFIG_SYS_CCSRBAR              0xffe00000      /* relocated CCSRBAR */
 116 #ifdef CONFIG_PHYS_64BIT
 117 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
 118 #else
 119 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
 120 #endif
 121 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 122
 123 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
 124 #define CONFIG_SYS_CCSRBAR_DEFAULT      CONFIG_SYS_CCSRBAR
 125 #else
 126 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 127 #endif
 128
 129 /* DDR Setup */
 130 #define CONFIG_VERY_BIG_RAM
 131 #define CONFIG_FSL_DDR2
 132 #undef CONFIG_FSL_DDR_INTERACTIVE
 133 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 134 #define CONFIG_DDR_SPD
 135 #undef CONFIG_DDR_DLL
 136
 137 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 138 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 139
 140 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 141 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 142
 143 #define CONFIG_NUM_DDR_CONTROLLERS      1
 144 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 145 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 146
 147 /* I2C addresses of SPD EEPROMs */
 148 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 149 #define CONFIG_SYS_SPD_BUS_NUM          1
 150
 151 /* These are used when DDR doesn't use SPD. */
 152 #define CONFIG_SYS_SDRAM_SIZE           256     /* DDR is 256MB */
 153 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
 154 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102 /* Enable, no interleaving */
 155 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 156 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 157 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
 158 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 159 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 160 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 161 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 162 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 163 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 164 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 165 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 166 #define CONFIG_SYS_DDR_CONTROL  0xC3008000      /* Type = DDR2 */
 167 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 168
 169 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 170 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 171 #define CONFIG_SYS_DDR_SBE              0x00010000
 172
 173 /* Make sure required options are set */
 174 #ifndef CONFIG_SPD_EEPROM
 175 #error ("CONFIG_SPD_EEPROM is required")
 176 #endif
 177
 178 #undef CONFIG_CLOCKS_IN_MHZ
 179
 180
 181 /*
 182  * Memory map -- xxx -this is wrong, needs updating
 183  *
 184  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 185  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 186  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 187  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 188  *
 189  * Localbus cacheable (TBD)
 190  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 191  *
 192  * Localbus non-cacheable
 193  * 0xe000_0000  0xe7ff_ffff     Promjet/free            128M non-cacheable
 194  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 195  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 196  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 197  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 198  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 199  */
 200
 201 /*
 202  * Local Bus Definitions
 203  */
 204 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 205 #ifdef CONFIG_PHYS_64BIT
 206 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 207 #else
 208 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 209 #endif
 210
 211 #define CONFIG_FLASH_BR_PRELIM \
 212                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
 213                  | BR_PS_16 | BR_V)
 214 #define CONFIG_FLASH_OR_PRELIM  0xf8000ff7
 215
 216 #define CONFIG_SYS_BR1_PRELIM \
 217                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 218                  | BR_PS_16 | BR_V)
 219 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 220
 221 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
 222                                       CONFIG_SYS_FLASH_BASE_PHYS }
 223 #define CONFIG_SYS_FLASH_QUIET_TEST
 224 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 225
 226 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 227 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 228 #undef  CONFIG_SYS_FLASH_CHECKSUM
 229 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 230 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 231
 232 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 233
 234 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
 235         || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 236 #define CONFIG_SYS_RAMBOOT
 237 #else
 238 #undef CONFIG_SYS_RAMBOOT
 239 #endif
 240
 241 #define CONFIG_FLASH_CFI_DRIVER
 242 #define CONFIG_SYS_FLASH_CFI
 243 #define CONFIG_SYS_FLASH_EMPTY_INFO
 244 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 245
 246 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 247
 248 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 249 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 250 #ifdef CONFIG_PHYS_64BIT
 251 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 252 #else
 253 #define PIXIS_BASE_PHYS PIXIS_BASE
 254 #endif
 255
 256 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 257 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 258
 259 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 260 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 261 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 262 #define PIXIS_CSR               0x3     /* PIXIS General control/status register */
 263 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 264 #define PIXIS_PWR               0x5     /* PIXIS Power status register */
 265 #define PIXIS_AUX               0x6     /* Auxiliary 1 register */
 266 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 267 #define PIXIS_AUX2              0x8     /* Auxiliary 2 register */
 268 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 269 #define PIXIS_VSTAT             0x11    /* VELA Status Register */
 270 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 271 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 272 #define PIXIS_VCORE0            0x14    /* VELA VCORE0 Register */
 273 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 274 #define PIXIS_VBOOT_LBMAP       0xe0    /* VBOOT - CFG_LBMAP */
 275 #define PIXIS_VBOOT_LBMAP_NOR0  0x00    /* cfg_lbmap - boot from NOR 0 */
 276 #define PIXIS_VBOOT_LBMAP_NOR1  0x01    /* cfg_lbmap - boot from NOR 1 */
 277 #define PIXIS_VBOOT_LBMAP_NOR2  0x02    /* cfg_lbmap - boot from NOR 2 */
 278 #define PIXIS_VBOOT_LBMAP_NOR3  0x03    /* cfg_lbmap - boot from NOR 3 */
 279 #define PIXIS_VBOOT_LBMAP_PJET  0x04    /* cfg_lbmap - boot from projet */
 280 #define PIXIS_VBOOT_LBMAP_NAND  0x05    /* cfg_lbmap - boot from NAND */
 281 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 282 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 283 #define PIXIS_VSPEED2           0x19    /* VELA VSpeed 2 */
 284 #define PIXIS_VSYSCLK0          0x1A    /* VELA SYSCLK0 Register */
 285 #define PIXIS_VSYSCLK1          0x1B    /* VELA SYSCLK1 Register */
 286 #define PIXIS_VSYSCLK2          0x1C    /* VELA SYSCLK2 Register */
 287 #define PIXIS_VDDRCLK0          0x1D    /* VELA DDRCLK0 Register */
 288 #define PIXIS_VDDRCLK1          0x1E    /* VELA DDRCLK1 Register */
 289 #define PIXIS_VDDRCLK2          0x1F    /* VELA DDRCLK2 Register */
 290 #define PIXIS_VWATCH            0x24    /* Watchdog Register */
 291 #define PIXIS_LED               0x25    /* LED Register */
 292
 293 #define PIXIS_SPD_SYSCLK        0x7     /* SYSCLK option */
 294
 295 /* old pixis referenced names */
 296 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 297 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 298 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0xc0
 299
 300 #define CONFIG_SYS_INIT_RAM_LOCK        1
 301 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 302 #define CONFIG_SYS_INIT_RAM_END 0x00004000      /* End of used area in RAM */
 303
 304 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 305 #define CONFIG_SYS_GBL_DATA_OFFSET \
 306                 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 307 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 308
 309 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024) /* Reserve 256 kB for Mon */
 310 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)   /* Reserved for malloc */
 311
 312 #ifndef CONFIG_NAND_SPL
 313 #define CONFIG_SYS_NAND_BASE            0xffa00000
 314 #ifdef CONFIG_PHYS_64BIT
 315 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 316 #else
 317 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 318 #endif
 319 #else
 320 #define CONFIG_SYS_NAND_BASE            0xfff00000
 321 #ifdef CONFIG_PHYS_64BIT
 322 #define CONFIG_SYS_NAND_BASE_PHYS       0xffff00000ull
 323 #else
 324 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 325 #endif
 326 #endif
 327 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 328                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 329                                 CONFIG_SYS_NAND_BASE + 0x80000, \
 330                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 331 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 332 #define CONFIG_MTD_NAND_VERIFY_WRITE
 333 #define CONFIG_CMD_NAND         1
 334 #define CONFIG_NAND_FSL_ELBC    1
 335 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 336
 337 /* NAND boot: 4K NAND loader config */
 338 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 339 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 340 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 341 #define CONFIG_SYS_NAND_U_BOOT_START \
 342                 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 343 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 344 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 345 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 346
 347 /* NAND flash config */
 348 #define CONFIG_NAND_BR_PRELIM \
 349                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 350                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 351                 | BR_PS_8               /* Port Size = 8 bit */ \
 352                 | BR_MS_FCM             /* MSEL = FCM */ \
 353                 | BR_V)                 /* valid */
 354 #define CONFIG_NAND_OR_PRELIM   (0xFFFC0000     /* length 256K */ \
 355                 | OR_FCM_PGS            /* Large Page*/ \
 356                 | OR_FCM_CSCT \
 357                 | OR_FCM_CST \
 358                 | OR_FCM_CHT \
 359                 | OR_FCM_SCY_1 \
 360                 | OR_FCM_TRLX \
 361                 | OR_FCM_EHTR)
 362
 363 #ifdef CONFIG_RAMBOOT_NAND
 364 #define CONFIG_SYS_BR0_PRELIM  CONFIG_NAND_BR_PRELIM    /* NAND Base Address */
 365 #define CONFIG_SYS_OR0_PRELIM  CONFIG_NAND_OR_PRELIM    /* NAND Options */
 366 #define CONFIG_SYS_BR2_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 367 #define CONFIG_SYS_OR2_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 368 #else
 369 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 370 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 371 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM    /* NAND Base Address */
 372 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM    /* NAND Options */
 373 #endif
 374
 375 #define CONFIG_SYS_BR4_PRELIM \
 376                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
 377                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 378                 | BR_PS_8               /* Port Size = 8 bit */ \
 379                 | BR_MS_FCM             /* MSEL = FCM */ \
 380                 | BR_V)                 /* valid */
 381 #define CONFIG_SYS_OR4_PRELIM   CONFIG_NAND_OR_PRELIM   /* NAND Options */
 382 #define CONFIG_SYS_BR5_PRELIM \
 383                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
 384                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 385                 | BR_PS_8               /* Port Size = 8 bit */ \
 386                 | BR_MS_FCM             /* MSEL = FCM */ \
 387                 | BR_V)                 /* valid */
 388 #define CONFIG_SYS_OR5_PRELIM   CONFIG_NAND_OR_PRELIM   /* NAND Options */
 389
 390 #define CONFIG_SYS_BR6_PRELIM \
 391                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
 392                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 393                 | BR_PS_8               /* Port Size = 8 bit */ \
 394                 | BR_MS_FCM             /* MSEL = FCM */ \
 395                 | BR_V)                 /* valid */
 396 #define CONFIG_SYS_OR6_PRELIM   CONFIG_NAND_OR_PRELIM   /* NAND Options */
 397
 398 /* Serial Port - controlled on board with jumper J8
 399  * open - index 2
 400  * shorted - index 1
 401  */
 402 #define CONFIG_CONS_INDEX       1
 403 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 404 #define CONFIG_SYS_NS16550
 405 #define CONFIG_SYS_NS16550_SERIAL
 406 #define CONFIG_SYS_NS16550_REG_SIZE     1
 407 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 408 #ifdef CONFIG_NAND_SPL
 409 #define CONFIG_NS16550_MIN_FUNCTIONS
 410 #endif
 411
 412 #define CONFIG_SYS_BAUDRATE_TABLE       \
 413         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 414
 415 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 416 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 417
 418 /* Use the HUSH parser */
 419 #define CONFIG_SYS_HUSH_PARSER
 420 #ifdef  CONFIG_SYS_HUSH_PARSER
 421 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 422 #endif
 423
 424 /*
 425  * Pass open firmware flat tree
 426  */
 427 #define CONFIG_OF_LIBFDT                1
 428 #define CONFIG_OF_BOARD_SETUP           1
 429 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 430
 431 /*
 432  * I2C
 433  */
 434 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 435 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 436 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 437 #define CONFIG_I2C_MULTI_BUS
 438 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 439 #define CONFIG_SYS_I2C_SLAVE            0x7F
 440 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}     /* Don't probe these addrs */
 441 #define CONFIG_SYS_I2C_OFFSET           0x3000
 442 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 443
 444 /*
 445  * I2C2 EEPROM
 446  */
 447 #define CONFIG_ID_EEPROM
 448 #ifdef CONFIG_ID_EEPROM
 449 #define CONFIG_SYS_I2C_EEPROM_NXID
 450 #endif
 451 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 452 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 453 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 454
 455 /*
 456  * General PCI
 457  * Memory space is mapped 1-1, but I/O space must start from 0.
 458  */
 459
 460 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 461 #ifdef CONFIG_PHYS_64BIT
 462 #define CONFIG_SYS_PCI1_MEM_BUS         0xf0000000
 463 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc00000000ull
 464 #else
 465 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 466 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 467 #endif
 468 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 469 #define CONFIG_SYS_PCI1_IO_VIRT         0xffc00000
 470 #define CONFIG_SYS_PCI1_IO_BUS          0x00000000
 471 #ifdef CONFIG_PHYS_64BIT
 472 #define CONFIG_SYS_PCI1_IO_PHYS         0xfffc00000ull
 473 #else
 474 #define CONFIG_SYS_PCI1_IO_PHYS         0xffc00000
 475 #endif
 476 #define CONFIG_SYS_PCI1_IO_SIZE         0x00010000      /* 64k */
 477
 478 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 479 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x90000000
 480 #ifdef CONFIG_PHYS_64BIT
 481 #define CONFIG_SYS_PCIE1_MEM_BUS        0xf8000000
 482 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc10000000ull
 483 #else
 484 #define CONFIG_SYS_PCIE1_MEM_BUS        0x90000000
 485 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x90000000
 486 #endif
 487 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x08000000      /* 128M */
 488 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc10000
 489 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 490 #ifdef CONFIG_PHYS_64BIT
 491 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc10000ull
 492 #else
 493 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc10000
 494 #endif
 495 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 496
 497 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 498 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x98000000
 499 #ifdef CONFIG_PHYS_64BIT
 500 #define CONFIG_SYS_PCIE2_MEM_BUS        0xf8000000
 501 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc18000000ull
 502 #else
 503 #define CONFIG_SYS_PCIE2_MEM_BUS        0x98000000
 504 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x98000000
 505 #endif
 506 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x08000000      /* 128M */
 507 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
 508 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 509 #ifdef CONFIG_PHYS_64BIT
 510 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc20000ull
 511 #else
 512 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
 513 #endif
 514 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 515
 516 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 517 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 518 #ifdef CONFIG_PHYS_64BIT
 519 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 520 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 521 #else
 522 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 523 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 524 #endif
 525 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 526 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc30000
 527 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 528 #ifdef CONFIG_PHYS_64BIT
 529 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc30000ull
 530 #else
 531 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc30000
 532 #endif
 533 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 534
 535 #if defined(CONFIG_PCI)
 536
 537 #define CONFIG_NET_MULTI
 538 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 539
 540 /*PCIE video card used*/
 541 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE3_IO_VIRT
 542
 543 /*PCI video card used*/
 544 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 545
 546 /* video */
 547 #define CONFIG_VIDEO
 548
 549 #if defined(CONFIG_VIDEO)
 550 #define CONFIG_BIOSEMU
 551 #define CONFIG_CFB_CONSOLE
 552 #define CONFIG_VIDEO_SW_CURSOR
 553 #define CONFIG_VGA_AS_SINGLE_DEVICE
 554 #define CONFIG_ATI_RADEON_FB
 555 #define CONFIG_VIDEO_LOGO
 556 /*#define CONFIG_CONSOLE_CURSOR*/
 557 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
 558 #endif
 559
 560 #undef CONFIG_EEPRO100
 561 #undef CONFIG_TULIP
 562 #undef CONFIG_RTL8139
 563
 564 #ifndef CONFIG_PCI_PNP
 565         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
 566         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
 567         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 568 #endif
 569
 570 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 571
 572 #endif  /* CONFIG_PCI */
 573
 574 /* SATA */
 575 #define CONFIG_LIBATA
 576 #define CONFIG_FSL_SATA
 577
 578 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 579 #define CONFIG_SATA1
 580 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 581 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 582 #define CONFIG_SATA2
 583 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 584 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 585
 586 #ifdef CONFIG_FSL_SATA
 587 #define CONFIG_LBA48
 588 #define CONFIG_CMD_SATA
 589 #define CONFIG_DOS_PARTITION
 590 #define CONFIG_CMD_EXT2
 591 #endif
 592
 593 #if defined(CONFIG_TSEC_ENET)
 594
 595 #ifndef CONFIG_NET_MULTI
 596 #define CONFIG_NET_MULTI        1
 597 #endif
 598
 599 #define CONFIG_MII              1       /* MII PHY management */
 600 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 601 #define CONFIG_TSEC1    1
 602 #define CONFIG_TSEC1_NAME       "eTSEC1"
 603 #define CONFIG_TSEC3    1
 604 #define CONFIG_TSEC3_NAME       "eTSEC3"
 605
 606 #define CONFIG_FSL_SGMII_RISER  1
 607 #define SGMII_RISER_PHY_OFFSET  0x1c
 608
 609 #define TSEC1_PHY_ADDR          1       /* TSEC1 -> PHY1 */
 610 #define TSEC3_PHY_ADDR          0       /* TSEC3 -> PHY0 */
 611
 612 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 613 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 614
 615 #define TSEC1_PHYIDX            0
 616 #define TSEC3_PHYIDX            0
 617
 618 #define CONFIG_ETHPRIME         "eTSEC1"
 619
 620 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 621
 622 #endif  /* CONFIG_TSEC_ENET */
 623
 624 /*
 625  * Environment
 626  */
 627
 628 #if defined(CONFIG_SYS_RAMBOOT)
 629 #if defined(CONFIG_RAMBOOT_NAND)
 630         #define CONFIG_ENV_IS_IN_NAND   1
 631         #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 632         #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 633 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 634         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 635         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 636         #define CONFIG_ENV_SIZE         0x2000
 637 #endif
 638 #else
 639         #define CONFIG_ENV_IS_IN_FLASH  1
 640         #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 641         #define CONFIG_ENV_ADDR         0xfff80000
 642         #else
 643         #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 644         #endif
 645         #define CONFIG_ENV_SIZE         0x2000
 646         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 647 #endif
 648
 649 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 650 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 651
 652 /*
 653  * Command line configuration.
 654  */
 655 #include <config_cmd_default.h>
 656
 657 #define CONFIG_CMD_IRQ
 658 #define CONFIG_CMD_PING
 659 #define CONFIG_CMD_I2C
 660 #define CONFIG_CMD_MII
 661 #define CONFIG_CMD_ELF
 662 #define CONFIG_CMD_IRQ
 663 #define CONFIG_CMD_SETEXPR
 664 #define CONFIG_CMD_REGINFO
 665
 666 #if defined(CONFIG_PCI)
 667 #define CONFIG_CMD_PCI
 668 #define CONFIG_CMD_NET
 669 #endif
 670
 671 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 672
 673 #define CONFIG_MMC     1
 674
 675 #ifdef CONFIG_MMC
 676 #define CONFIG_FSL_ESDHC
 677 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 678 #define CONFIG_CMD_MMC
 679 #define CONFIG_GENERIC_MMC
 680 #define CONFIG_CMD_EXT2
 681 #define CONFIG_CMD_FAT
 682 #define CONFIG_DOS_PARTITION
 683 #endif
 684
 685 /*
 686  * Miscellaneous configurable options
 687  */
 688 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 689 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 690 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 691 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 692 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 693 #if defined(CONFIG_CMD_KGDB)
 694 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 695 #else
 696 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 697 #endif
 698 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE \
 699                 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 700 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 701 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
 702 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 703
 704 /*
 705  * For booting Linux, the board info and command line data
 706  * have to be in the first 16 MB of memory, since this is
 707  * the maximum mapped by the Linux kernel during initialization.
 708  */
 709 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20) /* Initial Memory map for Linux */
 710
 711 /*
 712  * Internal Definitions
 713  *
 714  * Boot Flags
 715  */
 716 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 717 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 718
 719 #if defined(CONFIG_CMD_KGDB)
 720 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 721 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 722 #endif
 723
 724 /*
 725  * Environment Configuration
 726  */
 727
 728 /* The mac addresses for all ethernet interface */
 729 #if defined(CONFIG_TSEC_ENET)
 730 #define CONFIG_HAS_ETH0
 731 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 732 #define CONFIG_HAS_ETH1
 733 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 734 #define CONFIG_HAS_ETH2
 735 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 736 #define CONFIG_HAS_ETH3
 737 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 738 #endif
 739
 740 #define CONFIG_IPADDR           192.168.1.254
 741
 742 #define CONFIG_HOSTNAME         unknown
 743 #define CONFIG_ROOTPATH         /opt/nfsroot
 744 #define CONFIG_BOOTFILE         uImage
 745 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 746
 747 #define CONFIG_SERVERIP         192.168.1.1
 748 #define CONFIG_GATEWAYIP        192.168.1.1
 749 #define CONFIG_NETMASK          255.255.255.0
 750
 751 /* default location for tftp and bootm */
 752 #define CONFIG_LOADADDR         1000000
 753
 754 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 755 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 756
 757 #define CONFIG_BAUDRATE 115200
 758
 759 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 760  "netdev=eth0\0"                                                \
 761  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 762  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 763         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 764         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 765         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 766         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 767         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 768  "consoledev=ttyS0\0"                           \
 769  "ramdiskaddr=2000000\0"                        \
 770  "ramdiskfile=8536ds/ramdisk.uboot\0"           \
 771  "fdtaddr=c00000\0"                             \
 772  "fdtfile=8536ds/mpc8536ds.dtb\0"               \
 773  "bdev=sda3\0"                                  \
 774  "usb_phy_type=ulpi\0"
 775
 776 #define CONFIG_HDBOOT                           \
 777  "setenv bootargs root=/dev/$bdev rw "          \
 778  "console=$consoledev,$baudrate $othbootargs;"  \
 779  "tftp $loadaddr $bootfile;"                    \
 780  "tftp $fdtaddr $fdtfile;"                      \
 781  "bootm $loadaddr - $fdtaddr"
 782
 783 #define CONFIG_NFSBOOTCOMMAND           \
 784  "setenv bootargs root=/dev/nfs rw "    \
 785  "nfsroot=$serverip:$rootpath "         \
 786  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 787  "console=$consoledev,$baudrate $othbootargs;"  \
 788  "tftp $loadaddr $bootfile;"            \
 789  "tftp $fdtaddr $fdtfile;"              \
 790  "bootm $loadaddr - $fdtaddr"
 791
 792 #define CONFIG_RAMBOOTCOMMAND           \
 793  "setenv bootargs root=/dev/ram rw "    \
 794  "console=$consoledev,$baudrate $othbootargs;"  \
 795  "tftp $ramdiskaddr $ramdiskfile;"      \
 796  "tftp $loadaddr $bootfile;"            \
 797  "tftp $fdtaddr $fdtfile;"              \
 798  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 799
 800 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 801
 802 #endif  /* __CONFIG_H */