include/configs/MPC8536DS.h

   1 /*
   2  * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8536ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #include "../board/freescale/common/ics307_clk.h"
  31
  32 #ifdef CONFIG_36BIT
  33 #define CONFIG_PHYS_64BIT       1
  34 #endif
  35
  36 #ifdef CONFIG_NAND
  37 #define CONFIG_NAND_U_BOOT              1
  38 #define CONFIG_RAMBOOT_NAND             1
  39 #ifdef CONFIG_NAND_SPL
  40 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  42 #else
  43 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
  44 #define CONFIG_SYS_TEXT_BASE    0xf8f82000
  45 #endif /* CONFIG_NAND_SPL */
  46 #endif
  47
  48 #ifdef CONFIG_SDCARD
  49 #define CONFIG_RAMBOOT_SDCARD           1
  50 #define CONFIG_SYS_TEXT_BASE    0xf8f80000
  51 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  52 #endif
  53
  54 #ifdef CONFIG_SPIFLASH
  55 #define CONFIG_RAMBOOT_SPIFLASH         1
  56 #define CONFIG_SYS_TEXT_BASE    0xf8f80000
  57 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  58 #endif
  59
  60 #ifndef CONFIG_SYS_TEXT_BASE
  61 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  62 #endif
  63
  64 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  65 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  66 #endif
  67
  68 #ifndef CONFIG_SYS_MONITOR_BASE
  69 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  70 #endif
  71
  72 /* High Level Configuration Options */
  73 #define CONFIG_BOOKE            1       /* BOOKE */
  74 #define CONFIG_E500             1       /* BOOKE e500 family */
  75 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  76 #define CONFIG_MPC8536          1
  77 #define CONFIG_MPC8536DS        1
  78
  79 #define CONFIG_FSL_ELBC         1       /* Has Enhanced localbus controller */
  80 #define CONFIG_SPI_FLASH        1       /* Has SPI Flash */
  81 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  82 #define CONFIG_PCI1             1       /* Enable PCI controller 1 */
  83 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  84 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  85 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  86 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  87 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  88 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  89
  90 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  91 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
  92
  93 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  94 #define CONFIG_ENV_OVERWRITE
  95
  96 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  97 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  98 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
  99
 100 /*
 101  * These can be toggled for performance analysis, otherwise use default.
 102  */
 103 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 104 #define CONFIG_BTB                      /* toggle branch predition */
 105
 106 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
 107
 108 #define CONFIG_ENABLE_36BIT_PHYS        1
 109
 110 #ifdef CONFIG_PHYS_64BIT
 111 #define CONFIG_ADDR_MAP                 1
 112 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 113 #endif
 114
 115 #define CONFIG_SYS_MEMTEST_START 0x00010000     /* skip exception vectors */
 116 #define CONFIG_SYS_MEMTEST_END   0x1f000000     /* skip u-boot at top of RAM */
 117 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 118
 119 /*
 120  * Config the L2 Cache as L2 SRAM
 121  */
 122 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 123 #ifdef CONFIG_PHYS_64BIT
 124 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
 125 #else
 126 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 127 #endif
 128 #define CONFIG_SYS_L2_SIZE              (512 << 10)
 129 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 130
 131 #define CONFIG_SYS_CCSRBAR              0xffe00000
 132 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 133
 134 #if defined(CONFIG_NAND_SPL)
 135 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 136 #endif
 137
 138 /* DDR Setup */
 139 #define CONFIG_VERY_BIG_RAM
 140 #define CONFIG_FSL_DDR2
 141 #undef CONFIG_FSL_DDR_INTERACTIVE
 142 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 143 #define CONFIG_DDR_SPD
 144
 145 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 146 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 147
 148 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 149 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 150
 151 #define CONFIG_NUM_DDR_CONTROLLERS      1
 152 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 153 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 154
 155 /* I2C addresses of SPD EEPROMs */
 156 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 157 #define CONFIG_SYS_SPD_BUS_NUM          1
 158
 159 /* These are used when DDR doesn't use SPD. */
 160 #define CONFIG_SYS_SDRAM_SIZE           256     /* DDR is 256MB */
 161 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
 162 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80010102 /* Enable, no interleaving */
 163 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 164 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
 165 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
 166 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 167 #define CONFIG_SYS_DDR_MODE_1           0x00480432
 168 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 169 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
 170 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 171 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 172 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 173 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 174 #define CONFIG_SYS_DDR_CONTROL  0xC3008000      /* Type = DDR2 */
 175 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
 176
 177 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
 178 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 179 #define CONFIG_SYS_DDR_SBE              0x00010000
 180
 181 /* Make sure required options are set */
 182 #ifndef CONFIG_SPD_EEPROM
 183 #error ("CONFIG_SPD_EEPROM is required")
 184 #endif
 185
 186 #undef CONFIG_CLOCKS_IN_MHZ
 187
 188
 189 /*
 190  * Memory map -- xxx -this is wrong, needs updating
 191  *
 192  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 193  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 194  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 195  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 196  *
 197  * Localbus cacheable (TBD)
 198  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
 199  *
 200  * Localbus non-cacheable
 201  * 0xe000_0000  0xe7ff_ffff     Promjet/free            128M non-cacheable
 202  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
 203  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
 204  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
 205  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 206  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 207  */
 208
 209 /*
 210  * Local Bus Definitions
 211  */
 212 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
 213 #ifdef CONFIG_PHYS_64BIT
 214 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 215 #else
 216 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 217 #endif
 218
 219 #define CONFIG_FLASH_BR_PRELIM \
 220                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
 221                  | BR_PS_16 | BR_V)
 222 #define CONFIG_FLASH_OR_PRELIM  0xf8000ff7
 223
 224 #define CONFIG_SYS_BR1_PRELIM \
 225                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 226                  | BR_PS_16 | BR_V)
 227 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 228
 229 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
 230                                       CONFIG_SYS_FLASH_BASE_PHYS }
 231 #define CONFIG_SYS_FLASH_QUIET_TEST
 232 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 233
 234 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 235 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 236 #undef  CONFIG_SYS_FLASH_CHECKSUM
 237 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 238 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 239
 240 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
 241     defined(CONFIG_RAMBOOT_SPIFLASH)
 242 #define CONFIG_SYS_RAMBOOT
 243 #define CONFIG_SYS_EXTRA_ENV_RELOC
 244 #else
 245 #undef CONFIG_SYS_RAMBOOT
 246 #endif
 247
 248 #define CONFIG_FLASH_CFI_DRIVER
 249 #define CONFIG_SYS_FLASH_CFI
 250 #define CONFIG_SYS_FLASH_EMPTY_INFO
 251 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 252
 253 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 254
 255 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 256 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 257 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
 258 #ifdef CONFIG_PHYS_64BIT
 259 #define PIXIS_BASE_PHYS 0xfffdf0000ull
 260 #else
 261 #define PIXIS_BASE_PHYS PIXIS_BASE
 262 #endif
 263
 264 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 265 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 266
 267 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 268 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 269 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 270 #define PIXIS_CSR               0x3     /* PIXIS General control/status register */
 271 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 272 #define PIXIS_PWR               0x5     /* PIXIS Power status register */
 273 #define PIXIS_AUX               0x6     /* Auxiliary 1 register */
 274 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 275 #define PIXIS_AUX2              0x8     /* Auxiliary 2 register */
 276 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 277 #define PIXIS_VSTAT             0x11    /* VELA Status Register */
 278 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 279 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 280 #define PIXIS_VCORE0            0x14    /* VELA VCORE0 Register */
 281 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 282 #define PIXIS_VBOOT_LBMAP       0xe0    /* VBOOT - CFG_LBMAP */
 283 #define PIXIS_VBOOT_LBMAP_NOR0  0x00    /* cfg_lbmap - boot from NOR 0 */
 284 #define PIXIS_VBOOT_LBMAP_NOR1  0x01    /* cfg_lbmap - boot from NOR 1 */
 285 #define PIXIS_VBOOT_LBMAP_NOR2  0x02    /* cfg_lbmap - boot from NOR 2 */
 286 #define PIXIS_VBOOT_LBMAP_NOR3  0x03    /* cfg_lbmap - boot from NOR 3 */
 287 #define PIXIS_VBOOT_LBMAP_PJET  0x04    /* cfg_lbmap - boot from projet */
 288 #define PIXIS_VBOOT_LBMAP_NAND  0x05    /* cfg_lbmap - boot from NAND */
 289 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 290 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 291 #define PIXIS_VSPEED2           0x19    /* VELA VSpeed 2 */
 292 #define PIXIS_VSYSCLK0          0x1A    /* VELA SYSCLK0 Register */
 293 #define PIXIS_VSYSCLK1          0x1B    /* VELA SYSCLK1 Register */
 294 #define PIXIS_VSYSCLK2          0x1C    /* VELA SYSCLK2 Register */
 295 #define PIXIS_VDDRCLK0          0x1D    /* VELA DDRCLK0 Register */
 296 #define PIXIS_VDDRCLK1          0x1E    /* VELA DDRCLK1 Register */
 297 #define PIXIS_VDDRCLK2          0x1F    /* VELA DDRCLK2 Register */
 298 #define PIXIS_VWATCH            0x24    /* Watchdog Register */
 299 #define PIXIS_LED               0x25    /* LED Register */
 300
 301 #define PIXIS_SPD_SYSCLK        0x7     /* SYSCLK option */
 302
 303 /* old pixis referenced names */
 304 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 305 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 306 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x4e
 307
 308 #define CONFIG_SYS_INIT_RAM_LOCK        1
 309 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 310 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
 311
 312 #define CONFIG_SYS_GBL_DATA_OFFSET \
 313                 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 314 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 315
 316 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024) /* Reserve 256 kB for Mon */
 317 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)   /* Reserved for malloc */
 318
 319 #ifndef CONFIG_NAND_SPL
 320 #define CONFIG_SYS_NAND_BASE            0xffa00000
 321 #ifdef CONFIG_PHYS_64BIT
 322 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 323 #else
 324 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 325 #endif
 326 #else
 327 #define CONFIG_SYS_NAND_BASE            0xfff00000
 328 #ifdef CONFIG_PHYS_64BIT
 329 #define CONFIG_SYS_NAND_BASE_PHYS       0xffff00000ull
 330 #else
 331 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 332 #endif
 333 #endif
 334 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 335                                 CONFIG_SYS_NAND_BASE + 0x40000, \
 336                                 CONFIG_SYS_NAND_BASE + 0x80000, \
 337                                 CONFIG_SYS_NAND_BASE + 0xC0000}
 338 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 339 #define CONFIG_MTD_NAND_VERIFY_WRITE
 340 #define CONFIG_CMD_NAND         1
 341 #define CONFIG_NAND_FSL_ELBC    1
 342 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 343
 344 /* NAND boot: 4K NAND loader config */
 345 #define CONFIG_SYS_NAND_SPL_SIZE        0x1000
 346 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
 347 #define CONFIG_SYS_NAND_U_BOOT_DST      (CONFIG_SYS_INIT_L2_ADDR)
 348 #define CONFIG_SYS_NAND_U_BOOT_START \
 349                 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
 350 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (0)
 351 #define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
 352 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 353
 354 /* NAND flash config */
 355 #define CONFIG_SYS_NAND_BR_PRELIM \
 356                 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 357                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 358                 | BR_PS_8               /* Port Size = 8 bit */ \
 359                 | BR_MS_FCM             /* MSEL = FCM */ \
 360                 | BR_V)                 /* valid */
 361 #define CONFIG_SYS_NAND_OR_PRELIM       (0xFFFC0000     /* length 256K */ \
 362                 | OR_FCM_PGS            /* Large Page*/ \
 363                 | OR_FCM_CSCT \
 364                 | OR_FCM_CST \
 365                 | OR_FCM_CHT \
 366                 | OR_FCM_SCY_1 \
 367                 | OR_FCM_TRLX \
 368                 | OR_FCM_EHTR)
 369
 370 #ifdef CONFIG_RAMBOOT_NAND
 371 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 372 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 373 #define CONFIG_SYS_BR2_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 374 #define CONFIG_SYS_OR2_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 375 #else
 376 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM   /* NOR Base Address */
 377 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM   /* NOR Options */
 378 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 379 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 380 #endif
 381
 382 #define CONFIG_SYS_BR4_PRELIM \
 383                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
 384                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 385                 | BR_PS_8               /* Port Size = 8 bit */ \
 386                 | BR_MS_FCM             /* MSEL = FCM */ \
 387                 | BR_V)                 /* valid */
 388 #define CONFIG_SYS_OR4_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 389 #define CONFIG_SYS_BR5_PRELIM \
 390                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
 391                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 392                 | BR_PS_8               /* Port Size = 8 bit */ \
 393                 | BR_MS_FCM             /* MSEL = FCM */ \
 394                 | BR_V)                 /* valid */
 395 #define CONFIG_SYS_OR5_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 396
 397 #define CONFIG_SYS_BR6_PRELIM \
 398                 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
 399                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 400                 | BR_PS_8               /* Port Size = 8 bit */ \
 401                 | BR_MS_FCM             /* MSEL = FCM */ \
 402                 | BR_V)                 /* valid */
 403 #define CONFIG_SYS_OR6_PRELIM   CONFIG_SYS_NAND_OR_PRELIM       /* NAND Options */
 404
 405 /* Serial Port - controlled on board with jumper J8
 406  * open - index 2
 407  * shorted - index 1
 408  */
 409 #define CONFIG_CONS_INDEX       1
 410 #define CONFIG_SYS_NS16550
 411 #define CONFIG_SYS_NS16550_SERIAL
 412 #define CONFIG_SYS_NS16550_REG_SIZE     1
 413 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 414 #ifdef CONFIG_NAND_SPL
 415 #define CONFIG_NS16550_MIN_FUNCTIONS
 416 #endif
 417
 418 #define CONFIG_SYS_BAUDRATE_TABLE       \
 419         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 420
 421 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 422 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 423
 424 /* Use the HUSH parser */
 425 #define CONFIG_SYS_HUSH_PARSER
 426
 427 /*
 428  * Pass open firmware flat tree
 429  */
 430 #define CONFIG_OF_LIBFDT                1
 431 #define CONFIG_OF_BOARD_SETUP           1
 432 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 433
 434 /*
 435  * I2C
 436  */
 437 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 438 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 439 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 440 #define CONFIG_I2C_MULTI_BUS
 441 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 442 #define CONFIG_SYS_I2C_SLAVE            0x7F
 443 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}     /* Don't probe these addrs */
 444 #define CONFIG_SYS_I2C_OFFSET           0x3000
 445 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 446
 447 /*
 448  * I2C2 EEPROM
 449  */
 450 #define CONFIG_ID_EEPROM
 451 #ifdef CONFIG_ID_EEPROM
 452 #define CONFIG_SYS_I2C_EEPROM_NXID
 453 #endif
 454 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 455 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 456 #define CONFIG_SYS_EEPROM_BUS_NUM       1
 457
 458 /*
 459  * eSPI - Enhanced SPI
 460  */
 461 #define CONFIG_HARD_SPI
 462 #define CONFIG_FSL_ESPI
 463
 464 #if defined(CONFIG_SPI_FLASH)
 465 #define CONFIG_SPI_FLASH_SPANSION
 466 #define CONFIG_CMD_SF
 467 #define CONFIG_SF_DEFAULT_SPEED 10000000
 468 #define CONFIG_SF_DEFAULT_MODE  0
 469 #endif
 470
 471 /*
 472  * General PCI
 473  * Memory space is mapped 1-1, but I/O space must start from 0.
 474  */
 475
 476 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 477 #ifdef CONFIG_PHYS_64BIT
 478 #define CONFIG_SYS_PCI1_MEM_BUS         0xf0000000
 479 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc00000000ull
 480 #else
 481 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 482 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 483 #endif
 484 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 485 #define CONFIG_SYS_PCI1_IO_VIRT         0xffc00000
 486 #define CONFIG_SYS_PCI1_IO_BUS          0x00000000
 487 #ifdef CONFIG_PHYS_64BIT
 488 #define CONFIG_SYS_PCI1_IO_PHYS         0xfffc00000ull
 489 #else
 490 #define CONFIG_SYS_PCI1_IO_PHYS         0xffc00000
 491 #endif
 492 #define CONFIG_SYS_PCI1_IO_SIZE         0x00010000      /* 64k */
 493
 494 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 495 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
 496 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x90000000
 497 #ifdef CONFIG_PHYS_64BIT
 498 #define CONFIG_SYS_PCIE1_MEM_BUS        0xf8000000
 499 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc10000000ull
 500 #else
 501 #define CONFIG_SYS_PCIE1_MEM_BUS        0x90000000
 502 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x90000000
 503 #endif
 504 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x08000000      /* 128M */
 505 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc10000
 506 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 507 #ifdef CONFIG_PHYS_64BIT
 508 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc10000ull
 509 #else
 510 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc10000
 511 #endif
 512 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 513
 514 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
 515 #define CONFIG_SYS_PCIE2_NAME           "Slot 2"
 516 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x98000000
 517 #ifdef CONFIG_PHYS_64BIT
 518 #define CONFIG_SYS_PCIE2_MEM_BUS        0xf8000000
 519 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc18000000ull
 520 #else
 521 #define CONFIG_SYS_PCIE2_MEM_BUS        0x98000000
 522 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x98000000
 523 #endif
 524 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x08000000      /* 128M */
 525 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
 526 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 527 #ifdef CONFIG_PHYS_64BIT
 528 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc20000ull
 529 #else
 530 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
 531 #endif
 532 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 533
 534 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
 535 #define CONFIG_SYS_PCIE3_NAME           "Slot 3"
 536 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 537 #ifdef CONFIG_PHYS_64BIT
 538 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 539 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 540 #else
 541 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 542 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 543 #endif
 544 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 545 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc30000
 546 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 547 #ifdef CONFIG_PHYS_64BIT
 548 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc30000ull
 549 #else
 550 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc30000
 551 #endif
 552 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 553
 554 #if defined(CONFIG_PCI)
 555
 556 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 557
 558 /*PCIE video card used*/
 559 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE3_IO_VIRT
 560
 561 /*PCI video card used*/
 562 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 563
 564 /* video */
 565 #define CONFIG_VIDEO
 566
 567 #if defined(CONFIG_VIDEO)
 568 #define CONFIG_BIOSEMU
 569 #define CONFIG_CFB_CONSOLE
 570 #define CONFIG_VIDEO_SW_CURSOR
 571 #define CONFIG_VGA_AS_SINGLE_DEVICE
 572 #define CONFIG_ATI_RADEON_FB
 573 #define CONFIG_VIDEO_LOGO
 574 /*#define CONFIG_CONSOLE_CURSOR*/
 575 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
 576 #endif
 577
 578 #undef CONFIG_EEPRO100
 579 #undef CONFIG_TULIP
 580 #undef CONFIG_RTL8139
 581
 582 #ifndef CONFIG_PCI_PNP
 583         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
 584         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
 585         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 586 #endif
 587
 588 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 589
 590 #endif  /* CONFIG_PCI */
 591
 592 /* SATA */
 593 #define CONFIG_LIBATA
 594 #define CONFIG_FSL_SATA
 595
 596 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 597 #define CONFIG_SATA1
 598 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 599 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 600 #define CONFIG_SATA2
 601 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 602 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 603
 604 #ifdef CONFIG_FSL_SATA
 605 #define CONFIG_LBA48
 606 #define CONFIG_CMD_SATA
 607 #define CONFIG_DOS_PARTITION
 608 #define CONFIG_CMD_EXT2
 609 #endif
 610
 611 #if defined(CONFIG_TSEC_ENET)
 612
 613 #define CONFIG_MII              1       /* MII PHY management */
 614 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 615 #define CONFIG_TSEC1    1
 616 #define CONFIG_TSEC1_NAME       "eTSEC1"
 617 #define CONFIG_TSEC3    1
 618 #define CONFIG_TSEC3_NAME       "eTSEC3"
 619
 620 #define CONFIG_FSL_SGMII_RISER  1
 621 #define SGMII_RISER_PHY_OFFSET  0x1c
 622
 623 #define TSEC1_PHY_ADDR          1       /* TSEC1 -> PHY1 */
 624 #define TSEC3_PHY_ADDR          0       /* TSEC3 -> PHY0 */
 625
 626 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 627 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 628
 629 #define TSEC1_PHYIDX            0
 630 #define TSEC3_PHYIDX            0
 631
 632 #define CONFIG_ETHPRIME         "eTSEC1"
 633
 634 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 635
 636 #endif  /* CONFIG_TSEC_ENET */
 637
 638 /*
 639  * Environment
 640  */
 641
 642 #if defined(CONFIG_SYS_RAMBOOT)
 643 #if defined(CONFIG_RAMBOOT_NAND)
 644 #define CONFIG_ENV_IS_IN_NAND   1
 645 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 646 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 647 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 648 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
 649 #define CONFIG_ENV_IS_IN_SPI_FLASH
 650 #define CONFIG_ENV_SPI_BUS      0
 651 #define CONFIG_ENV_SPI_CS       0
 652 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 653 #define CONFIG_ENV_SPI_MODE     0
 654 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 655 #define CONFIG_ENV_OFFSET       0xF0000
 656 #define CONFIG_ENV_SECT_SIZE    0x10000
 657 #elif defined(CONFIG_RAMBOOT_SDCARD)
 658 #define CONFIG_ENV_IS_IN_MMC
 659 #define CONFIG_FSL_FIXED_MMC_LOCATION
 660 #define CONFIG_ENV_SIZE         0x2000
 661 #define CONFIG_SYS_MMC_ENV_DEV  0
 662 #else
 663         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 664         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 665         #define CONFIG_ENV_SIZE         0x2000
 666 #endif
 667 #else
 668         #define CONFIG_ENV_IS_IN_FLASH  1
 669         #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 670         #define CONFIG_ENV_ADDR         0xfff80000
 671         #else
 672         #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 673         #endif
 674         #define CONFIG_ENV_SIZE         0x2000
 675         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 676 #endif
 677
 678 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 679 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 680
 681 /*
 682  * Command line configuration.
 683  */
 684 #include <config_cmd_default.h>
 685
 686 #define CONFIG_CMD_IRQ
 687 #define CONFIG_CMD_PING
 688 #define CONFIG_CMD_I2C
 689 #define CONFIG_CMD_MII
 690 #define CONFIG_CMD_ELF
 691 #define CONFIG_CMD_IRQ
 692 #define CONFIG_CMD_SETEXPR
 693 #define CONFIG_CMD_REGINFO
 694
 695 #if defined(CONFIG_PCI)
 696 #define CONFIG_CMD_PCI
 697 #define CONFIG_CMD_NET
 698 #endif
 699
 700 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 701
 702 #define CONFIG_MMC     1
 703
 704 #ifdef CONFIG_MMC
 705 #define CONFIG_FSL_ESDHC
 706 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 707 #define CONFIG_CMD_MMC
 708 #define CONFIG_GENERIC_MMC
 709 #endif
 710
 711 /*
 712  * USB
 713  */
 714 #define CONFIG_HAS_FSL_MPH_USB
 715 #ifdef CONFIG_HAS_FSL_MPH_USB
 716 #define CONFIG_USB_EHCI
 717
 718 #ifdef CONFIG_USB_EHCI
 719 #define CONFIG_CMD_USB
 720 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 721 #define CONFIG_USB_EHCI_FSL
 722 #define CONFIG_USB_STORAGE
 723 #endif
 724 #endif
 725
 726 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 727 #define CONFIG_CMD_EXT2
 728 #define CONFIG_CMD_FAT
 729 #define CONFIG_DOS_PARTITION
 730 #endif
 731
 732 /*
 733  * Miscellaneous configurable options
 734  */
 735 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 736 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 737 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 738 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 739 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 740 #if defined(CONFIG_CMD_KGDB)
 741 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 742 #else
 743 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 744 #endif
 745 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE \
 746                 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 747 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 748 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
 749 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 750
 751 /*
 752  * For booting Linux, the board info and command line data
 753  * have to be in the first 64 MB of memory, since this is
 754  * the maximum mapped by the Linux kernel during initialization.
 755  */
 756 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 757 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 758
 759 #if defined(CONFIG_CMD_KGDB)
 760 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 761 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 762 #endif
 763
 764 /*
 765  * Environment Configuration
 766  */
 767
 768 /* The mac addresses for all ethernet interface */
 769 #if defined(CONFIG_TSEC_ENET)
 770 #define CONFIG_HAS_ETH0
 771 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 772 #define CONFIG_HAS_ETH1
 773 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 774 #define CONFIG_HAS_ETH2
 775 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 776 #define CONFIG_HAS_ETH3
 777 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 778 #endif
 779
 780 #define CONFIG_IPADDR           192.168.1.254
 781
 782 #define CONFIG_HOSTNAME         unknown
 783 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 784 #define CONFIG_BOOTFILE         "uImage"
 785 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 786
 787 #define CONFIG_SERVERIP         192.168.1.1
 788 #define CONFIG_GATEWAYIP        192.168.1.1
 789 #define CONFIG_NETMASK          255.255.255.0
 790
 791 /* default location for tftp and bootm */
 792 #define CONFIG_LOADADDR         1000000
 793
 794 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 795 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 796
 797 #define CONFIG_BAUDRATE 115200
 798
 799 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 800  "netdev=eth0\0"                                                \
 801  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 802  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 803         "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
 804         "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
 805         "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
 806         "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
 807         "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
 808  "consoledev=ttyS0\0"                           \
 809  "ramdiskaddr=2000000\0"                        \
 810  "ramdiskfile=8536ds/ramdisk.uboot\0"           \
 811  "fdtaddr=c00000\0"                             \
 812  "fdtfile=8536ds/mpc8536ds.dtb\0"               \
 813  "bdev=sda3\0"                                  \
 814  "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 815
 816 #define CONFIG_HDBOOT                           \
 817  "setenv bootargs root=/dev/$bdev rw "          \
 818  "console=$consoledev,$baudrate $othbootargs;"  \
 819  "tftp $loadaddr $bootfile;"                    \
 820  "tftp $fdtaddr $fdtfile;"                      \
 821  "bootm $loadaddr - $fdtaddr"
 822
 823 #define CONFIG_NFSBOOTCOMMAND           \
 824  "setenv bootargs root=/dev/nfs rw "    \
 825  "nfsroot=$serverip:$rootpath "         \
 826  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 827  "console=$consoledev,$baudrate $othbootargs;"  \
 828  "tftp $loadaddr $bootfile;"            \
 829  "tftp $fdtaddr $fdtfile;"              \
 830  "bootm $loadaddr - $fdtaddr"
 831
 832 #define CONFIG_RAMBOOTCOMMAND           \
 833  "setenv bootargs root=/dev/ram rw "    \
 834  "console=$consoledev,$baudrate $othbootargs;"  \
 835  "tftp $ramdiskaddr $ramdiskfile;"      \
 836  "tftp $loadaddr $bootfile;"            \
 837  "tftp $fdtaddr $fdtfile;"              \
 838  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 839
 840 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 841
 842 #endif  /* __CONFIG_H */