include/configs/MPC8540EVAL.h

   1 /*
   2  * (C) Copyright 2002,2003 Motorola,Inc.
   3  * Modified by Lunsheng Wang, lunsheng@sohu.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* mpc8540eval board configuration file */
  25 /* please refer to doc/README.mpc85xxads for more info */
  26 /* make sure you change the MAC address and other network params first,
  27  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1           /* BOOKE                    */
  34 #define CONFIG_E500             1           /* BOOKE e500 family        */
  35 #define CONFIG_MPC85xx          1           /* MPC8540/MPC8560          */
  36 #define CONFIG_MPC8540          1           /* MPC8540 specific         */
  37 #define CONFIG_MPC8540EVAL      1           /* MPC8540EVAL board specific */
  38
  39 #undef  CONFIG_PCI                          /* pci ethernet support     */
  40 #define CONFIG_TSEC_ENET                    /* tsec ethernet support  */
  41 #define CONFIG_ENV_OVERWRITE
  42
  43 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  44
  45 /* Using Localbus SDRAM to emulate flash before we can program the flash,
  46  * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
  47  * Not availabe for EVAL board
  48  */
  49 #undef CONFIG_RAM_AS_FLASH
  50
  51 /* sysclk for MPC8540EVAL */
  52 #if defined(CONFIG_SYSCLK_66M)
  53         /*
  54          * the oscillator on board is 66Mhz
  55          * can also get 66M clock from external PCI
  56          */
  57         #define CONFIG_SYS_CLK_FREQ   66000000
  58 #else
  59         #define CONFIG_SYS_CLK_FREQ   33000000   /* most pci cards are 33Mhz */
  60 #endif
  61
  62 /* below can be toggled for performance analysis. otherwise use default */
  63 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  64 #undef  CONFIG_BTB                          /* toggle branch predition */
  65 #undef  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
  66
  67 #define CONFIG_BOARD_PRE_INIT   1           /* Call board_pre_init      */
  68
  69 #undef  CFG_DRAM_TEST                       /* memory test, takes time  */
  70 #define CFG_MEMTEST_START       0x00200000      /* memtest works on     */
  71 #define CFG_MEMTEST_END         0x00400000
  72
  73 #if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
  74 #error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
  75 #endif
  76
  77 /*
  78  * Base addresses -- Note these are effective addresses where the
  79  * actual resources get mapped (not physical addresses)
  80  */
  81 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default      */
  82 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR    */
  83 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
  84 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
  85
  86 #define CFG_SDRAM_SIZE          256             /* DDR is now 256MB     */
  87
  88 #if defined(CONFIG_RAM_AS_FLASH)
  89 #define CFG_LBC_SDRAM_BASE      0xfc000000      /* Localbus SDRAM */
  90 #else
  91 #define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
  92 #endif
  93 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 0MB     */
  94
  95 #if defined(CONFIG_RAM_AS_FLASH)
  96 #define CFG_FLASH_BASE          0xf8000000      /* start of FLASH  16M  */
  97 #define CFG_BR0_PRELIM          0xf8001801      /* port size 32bit */
  98 #else /* Boot from real Flash */
  99 #define CFG_FLASH_BASE          0xff800000      /* start of FLASH 8M    */
 100 #define CFG_BR0_PRELIM          0xff801001      /* port size 16bit      */
 101 #endif
 102
 103 #define CFG_OR0_PRELIM          0xff806f67      /* 8MB Flash            */
 104 #define CFG_MAX_FLASH_BANKS     1               /* number of banks      */
 105 #define CFG_MAX_FLASH_SECT      64              /* sectors per device   */
 106 #undef  CFG_FLASH_CHECKSUM
 107 #define CFG_FLASH_ERASE_TOUT    60000   /* Timeout for Flash Erase (in ms)*/
 108 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)*/
 109 #define CFG_FLASH_CFI           1
 110
 111 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 112
 113 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 114 #define CFG_RAMBOOT
 115 #else
 116 #undef  CFG_RAMBOOT
 117 #endif
 118
 119 /* DDR Setup */
 120 #define CONFIG_FSL_DDR1
 121 #undef CONFIG_FSL_DDR_INTERACTIVE
 122 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 123 #define CONFIG_DDR_SPD
 124 #define CONFIG_DDR_DLL                      /* possible DLL fix needed */
 125
 126 #undef  CONFIG_DDR_ECC                      /* only for ECC DDR module */
 127 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER        /* DDR controller or DMA? */
 128 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 129
 130 #define CFG_DDR_SDRAM_BASE      0x00000000
 131 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 132 #define CONFIG_VERY_BIG_RAM
 133
 134 #define CONFIG_NUM_DDR_CONTROLLERS      1
 135 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 136 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 137
 138 /* I2C addresses of SPD EEPROMs */
 139 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 140
 141 #undef CONFIG_CLOCKS_IN_MHZ
 142
 143 /* local bus definitions */
 144 #define CFG_BR2_PRELIM          0xf0001861      /* 64MB localbus SDRAM  */
 145 #define CFG_OR2_PRELIM          0xfc006901
 146 #define CFG_LBC_LCRR            0x00030004      /* local bus freq divider*/
 147 #define CFG_LBC_LBCR            0x00000000
 148 #define CFG_LBC_LSRT            0x20000000
 149 #define CFG_LBC_MRTPR           0x20000000
 150 #define CFG_LBC_LSDMR_1         0x2861b723
 151 #define CFG_LBC_LSDMR_2         0x0861b723
 152 #define CFG_LBC_LSDMR_3         0x0861b723
 153 #define CFG_LBC_LSDMR_4         0x1861b723
 154 #define CFG_LBC_LSDMR_5         0x4061b723
 155
 156 #if defined(CONFIG_RAM_AS_FLASH)
 157 #define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
 158 #else
 159 #define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
 160 #endif
 161 #define CFG_OR4_PRELIM          0xffffe1f1
 162 #define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
 163
 164 #define CONFIG_L1_INIT_RAM
 165 #define CFG_INIT_RAM_LOCK       1
 166 #define CFG_INIT_RAM_ADDR       0x40000000      /* Initial RAM address  */
 167 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 168
 169 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 170 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 171 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 172
 173 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 174 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 175
 176 /* Serial Port */
 177 #define CONFIG_CONS_INDEX     1
 178 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 179 #define CFG_NS16550
 180 #define CFG_NS16550_SERIAL
 181 #define CFG_NS16550_REG_SIZE    1
 182 #define CFG_NS16550_CLK         get_bus_freq(0)
 183 #define CONFIG_BAUDRATE         115200
 184
 185 #define CFG_BAUDRATE_TABLE  \
 186         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 187
 188 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 189 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 190
 191 /* Use the HUSH parser */
 192 #define CFG_HUSH_PARSER
 193 #ifdef  CFG_HUSH_PARSER
 194 #define CFG_PROMPT_HUSH_PS2 "> "
 195 #endif
 196
 197 /*
 198  * I2C
 199  */
 200 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 201 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 202 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 203 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 204 #define CFG_I2C_SLAVE           0x7F
 205 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 206 #define CFG_I2C_OFFSET          0x3000
 207
 208 /* General PCI */
 209 #define CFG_PCI_MEM_BASE        0x80000000
 210 #define CFG_PCI_MEM_PHYS        0x80000000
 211 #define CFG_PCI_MEM_SIZE        0x20000000
 212 #define CFG_PCI_IO_BASE         0xe2000000
 213
 214 #if defined(CONFIG_PCI)
 215 #define CONFIG_NET_MULTI
 216 #undef CONFIG_EEPRO100
 217 #define CONFIG_TULIP
 218 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 219 #if !defined(CONFIG_PCI_PNP)
 220 #define PCI_ENET0_IOADDR      0xe0000000
 221 #define PCI_ENET0_MEMADDR     0xe0000000
 222 #define PCI_IDSEL_NUMBER      0x0c      /*slot0->3(IDSEL)=12->15*/
 223 #endif
 224 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 225 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 226 #define CFG_PCI_SUBSYS_DEVICEID 0x0008
 227 #elif defined(CONFIG_TSEC_ENET)
 228 #define CONFIG_NET_MULTI        1
 229 #define CONFIG_MII              1       /* MII PHY management   */
 230 #define CONFIG_TSEC1    1
 231 #define CONFIG_HAS_ETH0
 232 #define CONFIG_TSEC1_NAME      "TSEC0"
 233 #define CONFIG_TSEC2    1
 234 #define CONFIG_HAS_ETH1
 235 #define CONFIG_TSEC2_NAME      "TSEC1"
 236 #define CONFIG_MPC85XX_FEC      1
 237 #define CONFIG_HAS_ETH2
 238 #define CONFIG_MPC85XX_FEC_NAME                "FEC"
 239 #define TSEC1_PHY_ADDR          7
 240 #define TSEC2_PHY_ADDR          4
 241 #define FEC_PHY_ADDR            2
 242 #define TSEC1_PHYIDX            0
 243 #define TSEC2_PHYIDX            0
 244 #define FEC_PHYIDX              0
 245 #define TSEC1_FLAGS             TSEC_GIGABIT
 246 #define TSEC2_FLAGS             TSEC_GIGABIT
 247 #define FEC_FLAGS               0
 248
 249 /* Options are: TSEC[0-1], FEC */
 250 #define CONFIG_ETHPRIME                "TSEC0"
 251
 252 #define CONFIG_PHY_M88E1011     1       /* GigaBit Ether PHY    */
 253 #define INTEL_LXT971_PHY        1
 254 #endif
 255
 256 /* Environment */
 257 #ifndef CFG_RAMBOOT
 258 #if defined(CONFIG_RAM_AS_FLASH)
 259 #define CFG_ENV_IS_NOWHERE
 260 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x100000)
 261 #define CFG_ENV_SIZE            0x2000
 262 #else
 263 #define CFG_ENV_IS_IN_FLASH     1
 264 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 265 #define CFG_ENV_SECT_SIZE       0x40000 /* 256K(one sector) for env */
 266 #endif
 267 #define CFG_ENV_SIZE            0x2000
 268 #else
 269 /* #define CFG_NO_FLASH         1 */    /* Flash is not usable now      */
 270 #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only     */
 271 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
 272 #define CFG_ENV_SIZE            0x2000
 273 #endif
 274
 275 #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
 276 #define CONFIG_BOOTCOMMAND      "bootm 0xff800000 0xffa00000"
 277 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 278
 279 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 280 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 281
 282
 283 /*
 284  * BOOTP options
 285  */
 286 #define CONFIG_BOOTP_BOOTFILESIZE
 287 #define CONFIG_BOOTP_BOOTPATH
 288 #define CONFIG_BOOTP_GATEWAY
 289 #define CONFIG_BOOTP_HOSTNAME
 290
 291
 292 /*
 293  * Command line configuration.
 294  */
 295 #include <config_cmd_default.h>
 296
 297 #define CONFIG_CMD_PING
 298 #define CONFIG_CMD_I2C
 299
 300 #if defined(CONFIG_PCI)
 301     #define CONFIG_CMD_PCI
 302 #endif
 303
 304 #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
 305     #undef CONFIG_CMD_ENV
 306     #undef CONFIG_CMD_LOADS
 307 #endif
 308
 309
 310 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 311
 312 /*
 313  * Miscellaneous configurable options
 314  */
 315 #define CFG_LONGHELP                    /* undef to save memory         */
 316 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 317 #define CFG_PROMPT      "MPC8540EVAL=> "/* Monitor Command Prompt       */
 318 #if defined(CONFIG_CMD_KGDB)
 319 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 320 #else
 321 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 322 #endif
 323 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 324 #define CFG_MAXARGS     16              /* max number of command args   */
 325 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 326 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 327
 328 /*
 329  * For booting Linux, the board info and command line data
 330  * have to be in the first 8 MB of memory, since this is
 331  * the maximum mapped by the Linux kernel during initialization.
 332  */
 333 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux */
 334
 335 /*
 336  * Internal Definitions
 337  *
 338  * Boot Flags
 339  */
 340 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 341 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 342
 343 #if defined(CONFIG_CMD_KGDB)
 344 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 345 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 346 #endif
 347
 348 /*****************************/
 349 /* Environment Configuration */
 350 /*****************************/
 351 /* The mac addresses for all ethernet interface */
 352 /* NOTE: change below for your network setting!!! */
 353 #if defined(CONFIG_TSEC_ENET)
 354 #define CONFIG_ETHADDR  00:01:af:07:9b:8a
 355 #define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
 356 #define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
 357 #endif
 358
 359 #define CONFIG_ROOTPATH  /nfsroot
 360 #define CONFIG_BOOTFILE  your.uImage
 361
 362 #define CONFIG_SERVERIP         192.168.101.1
 363 #define CONFIG_IPADDR           192.168.101.11
 364 #define CONFIG_GATEWAYIP        192.168.101.0
 365 #define CONFIG_NETMASK          255.255.255.0
 366
 367 #define CONFIG_LOADADDR  200000   /* default location for tftp and bootm */
 368
 369 #define CONFIG_HOSTNAME         MPC8540EVAL
 370
 371 #endif  /* __CONFIG_H */