include/configs/MPC8540EVAL.h

   1 /*
   2  * (C) Copyright 2002,2003 Motorola,Inc.
   3  * Modified by Lunsheng Wang, lunsheng@sohu.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* mpc8540eval board configuration file */
  25 /* please refer to doc/README.mpc85xxads for more info */
  26 /* make sure you change the MAC address and other network params first,
  27  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1           /* BOOKE                    */
  34 #define CONFIG_E500             1           /* BOOKE e500 family        */
  35 #define CONFIG_MPC85xx          1           /* MPC8540/MPC8560          */
  36 #define CONFIG_MPC8540          1           /* MPC8540 specific         */
  37 #define CONFIG_MPC8540EVAL      1           /* MPC8540EVAL board specific */
  38
  39 #undef  CONFIG_PCI                          /* pci ethernet support     */
  40 #define CONFIG_TSEC_ENET                    /* tsec ethernet support  */
  41 #define CONFIG_ENV_OVERWRITE
  42 #define CONFIG_SPD_EEPROM                   /* Use SPD EEPROM for DDR setup */
  43 #undef  CONFIG_DDR_ECC                      /* only for ECC DDR module */
  44 #define CONFIG_DDR_DLL                      /* possible DLL fix needed */
  45
  46 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  47
  48 /* Using Localbus SDRAM to emulate flash before we can program the flash,
  49  * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
  50  * Not availabe for EVAL board
  51  */
  52 #undef CONFIG_RAM_AS_FLASH
  53
  54 /* sysclk for MPC8540EVAL */
  55 #if defined(CONFIG_SYSCLK_66M)
  56         /*
  57          * the oscillator on board is 66Mhz
  58          * can also get 66M clock from external PCI
  59          */
  60         #define CONFIG_SYS_CLK_FREQ   66000000
  61 #else
  62         #define CONFIG_SYS_CLK_FREQ   33000000   /* most pci cards are 33Mhz */
  63 #endif
  64
  65 /* below can be toggled for performance analysis. otherwise use default */
  66 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  67 #undef  CONFIG_BTB                          /* toggle branch predition */
  68 #undef  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
  69
  70 #define CONFIG_BOARD_PRE_INIT   1           /* Call board_pre_init      */
  71
  72 #undef  CFG_DRAM_TEST                       /* memory test, takes time  */
  73 #define CFG_MEMTEST_START       0x00200000      /* memtest works on     */
  74 #define CFG_MEMTEST_END         0x00400000
  75
  76 #if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
  77 #error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
  78 #endif
  79
  80 /*
  81  * Base addresses -- Note these are effective addresses where the
  82  * actual resources get mapped (not physical addresses)
  83  */
  84 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default      */
  85 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR    */
  86 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
  87
  88 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory  */
  89 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
  90 #define CFG_SDRAM_SIZE          256             /* DDR is now 256MB     */
  91
  92 #if defined(CONFIG_RAM_AS_FLASH)
  93 #define CFG_LBC_SDRAM_BASE      0xfc000000      /* Localbus SDRAM */
  94 #else
  95 #define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
  96 #endif
  97 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 0MB     */
  98
  99 #if defined(CONFIG_RAM_AS_FLASH)
 100 #define CFG_FLASH_BASE          0xf8000000      /* start of FLASH  16M  */
 101 #define CFG_BR0_PRELIM          0xf8001801      /* port size 32bit */
 102 #else /* Boot from real Flash */
 103 #define CFG_FLASH_BASE          0xff800000      /* start of FLASH 8M    */
 104 #define CFG_BR0_PRELIM          0xff801001      /* port size 16bit      */
 105 #endif
 106
 107 #define CFG_OR0_PRELIM          0xff806f67      /* 8MB Flash            */
 108 #define CFG_MAX_FLASH_BANKS     1               /* number of banks      */
 109 #define CFG_MAX_FLASH_SECT      64              /* sectors per device   */
 110 #undef  CFG_FLASH_CHECKSUM
 111 #define CFG_FLASH_ERASE_TOUT    60000   /* Timeout for Flash Erase (in ms)*/
 112 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)*/
 113 #define CFG_FLASH_CFI           1
 114
 115 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 116
 117 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 118 #define CFG_RAMBOOT
 119 #else
 120 #undef  CFG_RAMBOOT
 121 #endif
 122
 123 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 124
 125 /* Here some DDR setting should be added */
 126
 127
 128 #undef CONFIG_CLOCKS_IN_MHZ
 129
 130 /* local bus definitions */
 131 #define CFG_BR2_PRELIM          0xf0001861      /* 64MB localbus SDRAM  */
 132 #define CFG_OR2_PRELIM          0xfc006901
 133 #define CFG_LBC_LCRR            0x00030004      /* local bus freq divider*/
 134 #define CFG_LBC_LBCR            0x00000000
 135 #define CFG_LBC_LSRT            0x20000000
 136 #define CFG_LBC_MRTPR           0x20000000
 137 #define CFG_LBC_LSDMR_1         0x2861b723
 138 #define CFG_LBC_LSDMR_2         0x0861b723
 139 #define CFG_LBC_LSDMR_3         0x0861b723
 140 #define CFG_LBC_LSDMR_4         0x1861b723
 141 #define CFG_LBC_LSDMR_5         0x4061b723
 142
 143 #if defined(CONFIG_RAM_AS_FLASH)
 144 #define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
 145 #else
 146 #define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
 147 #endif
 148 #define CFG_OR4_PRELIM          0xffffe1f1
 149 #define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
 150
 151 #define CONFIG_L1_INIT_RAM
 152 #define CFG_INIT_RAM_LOCK       1
 153 #define CFG_INIT_RAM_ADDR       0x40000000      /* Initial RAM address  */
 154 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 155
 156 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 157 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 158 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 159
 160 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 161 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 162
 163 /* Serial Port */
 164 #define CONFIG_CONS_INDEX     1
 165 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 166 #define CFG_NS16550
 167 #define CFG_NS16550_SERIAL
 168 #define CFG_NS16550_REG_SIZE    1
 169 #define CFG_NS16550_CLK         get_bus_freq(0)
 170 #define CONFIG_BAUDRATE         115200
 171
 172 #define CFG_BAUDRATE_TABLE  \
 173         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 174
 175 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 176 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 177
 178 /* Use the HUSH parser */
 179 #define CFG_HUSH_PARSER
 180 #ifdef  CFG_HUSH_PARSER
 181 #define CFG_PROMPT_HUSH_PS2 "> "
 182 #endif
 183
 184 /*
 185  * I2C
 186  */
 187 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 188 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 189 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 190 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 191 #define CFG_I2C_SLAVE           0x7F
 192 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 193 #define CFG_I2C_OFFSET          0x3000
 194
 195 /* General PCI */
 196 #define CFG_PCI_MEM_BASE        0x80000000
 197 #define CFG_PCI_MEM_PHYS        0x80000000
 198 #define CFG_PCI_MEM_SIZE        0x20000000
 199 #define CFG_PCI_IO_BASE         0xe2000000
 200
 201 #if defined(CONFIG_PCI)
 202 #define CONFIG_NET_MULTI
 203 #undef CONFIG_EEPRO100
 204 #define CONFIG_TULIP
 205 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 206 #if !defined(CONFIG_PCI_PNP)
 207 #define PCI_ENET0_IOADDR      0xe0000000
 208 #define PCI_ENET0_MEMADDR     0xe0000000
 209 #define PCI_IDSEL_NUMBER      0x0c      /*slot0->3(IDSEL)=12->15*/
 210 #endif
 211 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 212 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 213 #define CFG_PCI_SUBSYS_DEVICEID 0x0008
 214 #elif defined(CONFIG_TSEC_ENET)
 215 #define CONFIG_NET_MULTI        1
 216 #define CONFIG_MII              1       /* MII PHY management   */
 217 #define CONFIG_TSEC1    1
 218 #define CONFIG_HAS_ETH0
 219 #define CONFIG_TSEC1_NAME      "TSEC0"
 220 #define CONFIG_TSEC2    1
 221 #define CONFIG_HAS_ETH1
 222 #define CONFIG_TSEC2_NAME      "TSEC1"
 223 #define CONFIG_MPC85XX_FEC      1
 224 #define CONFIG_HAS_ETH2
 225 #define CONFIG_MPC85XX_FEC_NAME                "FEC"
 226 #define TSEC1_PHY_ADDR          7
 227 #define TSEC2_PHY_ADDR          4
 228 #define FEC_PHY_ADDR            2
 229 #define TSEC1_PHYIDX            0
 230 #define TSEC2_PHYIDX            0
 231 #define FEC_PHYIDX              0
 232 #define TSEC1_FLAGS             TSEC_GIGABIT
 233 #define TSEC2_FLAGS             TSEC_GIGABIT
 234 #define FEC_FLAGS               0
 235
 236 /* Options are: TSEC[0-1], FEC */
 237 #define CONFIG_ETHPRIME                "TSEC0"
 238
 239 #define CONFIG_PHY_M88E1011     1       /* GigaBit Ether PHY    */
 240 #define INTEL_LXT971_PHY        1
 241 #endif
 242
 243 #undef DEBUG
 244
 245 /* Environment */
 246 #ifndef CFG_RAMBOOT
 247 #if defined(CONFIG_RAM_AS_FLASH)
 248 #define CFG_ENV_IS_NOWHERE
 249 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x100000)
 250 #define CFG_ENV_SIZE            0x2000
 251 #else
 252 #define CFG_ENV_IS_IN_FLASH     1
 253 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 254 #define CFG_ENV_SECT_SIZE       0x40000 /* 256K(one sector) for env */
 255 #endif
 256 #define CFG_ENV_SIZE            0x2000
 257 #else
 258 /* #define CFG_NO_FLASH         1 */    /* Flash is not usable now      */
 259 #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only     */
 260 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
 261 #define CFG_ENV_SIZE            0x2000
 262 #endif
 263
 264 #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
 265 #define CONFIG_BOOTCOMMAND      "bootm 0xff800000 0xffa00000"
 266 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 267
 268 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 269 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 270
 271
 272 /*
 273  * BOOTP options
 274  */
 275 #define CONFIG_BOOTP_BOOTFILESIZE
 276 #define CONFIG_BOOTP_BOOTPATH
 277 #define CONFIG_BOOTP_GATEWAY
 278 #define CONFIG_BOOTP_HOSTNAME
 279
 280
 281 /*
 282  * Command line configuration.
 283  */
 284 #include <config_cmd_default.h>
 285
 286 #define CONFIG_CMD_PING
 287 #define CONFIG_CMD_I2C
 288
 289 #if defined(CONFIG_PCI)
 290     #define CONFIG_CMD_PCI
 291 #endif
 292
 293 #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
 294     #undef CONFIG_CMD_ENV
 295     #undef CONFIG_CMD_LOADS
 296 #endif
 297
 298
 299 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 300
 301 /*
 302  * Miscellaneous configurable options
 303  */
 304 #define CFG_LONGHELP                    /* undef to save memory         */
 305 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 306 #define CFG_PROMPT      "MPC8540EVAL=> "/* Monitor Command Prompt       */
 307 #if defined(CONFIG_CMD_KGDB)
 308 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 309 #else
 310 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 311 #endif
 312 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 313 #define CFG_MAXARGS     16              /* max number of command args   */
 314 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 315 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 316
 317 /*
 318  * For booting Linux, the board info and command line data
 319  * have to be in the first 8 MB of memory, since this is
 320  * the maximum mapped by the Linux kernel during initialization.
 321  */
 322 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux */
 323
 324 /*
 325  * Internal Definitions
 326  *
 327  * Boot Flags
 328  */
 329 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 330 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 331
 332 #if defined(CONFIG_CMD_KGDB)
 333 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 334 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 335 #endif
 336
 337 /*****************************/
 338 /* Environment Configuration */
 339 /*****************************/
 340 /* The mac addresses for all ethernet interface */
 341 /* NOTE: change below for your network setting!!! */
 342 #if defined(CONFIG_TSEC_ENET)
 343 #define CONFIG_ETHADDR  00:01:af:07:9b:8a
 344 #define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
 345 #define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
 346 #endif
 347
 348 #define CONFIG_ROOTPATH  /nfsroot
 349 #define CONFIG_BOOTFILE  your.uImage
 350
 351 #define CONFIG_SERVERIP         192.168.101.1
 352 #define CONFIG_IPADDR           192.168.101.11
 353 #define CONFIG_GATEWAYIP        192.168.101.0
 354 #define CONFIG_NETMASK          255.255.255.0
 355
 356 #define CONFIG_LOADADDR  200000   /* default location for tftp and bootm */
 357
 358 #define CONFIG_HOSTNAME         MPC8540EVAL
 359
 360 #endif  /* __CONFIG_H */