include/configs/MPC8544DS.h

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8544ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_BOOKE            1       /* BOOKE */
  32 #define CONFIG_E500             1       /* BOOKE e500 family */
  33 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  34 #define CONFIG_MPC8544          1
  35 #define CONFIG_MPC8544DS        1
  36
  37 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  38 #define CONFIG_PCI1             1       /* PCI controller 1 */
  39 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  40 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  41 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  42 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  43
  44 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  45 #define CONFIG_ENV_OVERWRITE
  46 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  47 #undef CONFIG_DDR_DLL
  48 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
  49
  50 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  52 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  53
  54 #define CONFIG_DDR_ECC_CMD
  55 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  56
  57 /*
  58  * When initializing flash, if we cannot find the manufacturer ID,
  59  * assume this is the AMD flash associated with the CDS board.
  60  * This allows booting from a promjet.
  61  */
  62 #define CONFIG_ASSUME_AMD_FLASH
  63
  64 #define MPC85xx_DDR_SDRAM_CLK_CNTL      /* 85xx has clock control reg */
  65
  66 #ifndef __ASSEMBLY__
  67 extern unsigned long get_board_sys_clk(unsigned long dummy);
  68 #endif
  69 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  70
  71 /*
  72  * These can be toggled for performance analysis, otherwise use default.
  73  */
  74 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  75 #define CONFIG_BTB                      /* toggle branch predition */
  76 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  77 #define CONFIG_CLEAR_LAW0               /* Clear LAW0 in cpu_init_r */
  78
  79 /*
  80  * Only possible on E500 Version 2 or newer cores.
  81  */
  82 #define CONFIG_ENABLE_36BIT_PHYS        1
  83
  84 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  85
  86 #undef  CFG_DRAM_TEST                   /* memory test, takes time */
  87 #define CFG_MEMTEST_START       0x00200000      /* memtest works on */
  88 #define CFG_MEMTEST_END         0x00400000
  89 #define CFG_ALT_MEMTEST
  90 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  91
  92 /*
  93  * Base addresses -- Note these are effective addresses where the
  94  * actual resources get mapped (not physical addresses)
  95  */
  96 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
  97 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
  98 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
  99
 100 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
 101 #define CFG_PCIE1_ADDR          (CFG_CCSRBAR+0xa000)
 102 #define CFG_PCIE2_ADDR          (CFG_CCSRBAR+0x9000)
 103 #define CFG_PCIE3_ADDR          (CFG_CCSRBAR+0xb000)
 104
 105 /*
 106  * DDR Setup
 107  */
 108 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 109 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 110
 111 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 112
 113 /*
 114  * Make sure required options are set
 115  */
 116 #ifndef CONFIG_SPD_EEPROM
 117 #error ("CONFIG_SPD_EEPROM is required")
 118 #endif
 119
 120 #undef CONFIG_CLOCKS_IN_MHZ
 121
 122 /*
 123  * Memory map
 124  *
 125  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 126  *
 127  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 128  *
 129  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 130  *
 131  * 0xe000_0000  0xe00f_ffff     CCSR                    1M non-cacheable
 132  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 133  *
 134  * Localbus cacheable
 135  *
 136  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M Cacheable
 137  * 0xf401_0000  0xf401_3fff     L1 for stack            4K Cacheable TLB0
 138  *
 139  * Localbus non-cacheable
 140  *
 141  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS (*)        1M non-cacheable
 142  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M non-cacheable
 143  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M non-cacheable
 144  *
 145  */
 146
 147 /*
 148  * Local Bus Definitions
 149  */
 150 #define CFG_BOOT_BLOCK          0xfc000000      /* boot TLB */
 151
 152 #define CFG_LBC_CACHE_BASE      0xf0000000      /* Localbus cacheable */
 153
 154 #define CFG_FLASH_BASE          0xff800000      /* start of FLASH 8M */
 155
 156 #define CFG_BR0_PRELIM          0xff801001
 157 #define CFG_BR1_PRELIM          0xfe801001
 158
 159 #define CFG_OR0_PRELIM          0xff806e65
 160 #define CFG_OR1_PRELIM          0xff806e65
 161
 162 #define CFG_FLASH_BANKS_LIST    {0xfe800000,CFG_FLASH_BASE}
 163
 164 #define CFG_MAX_FLASH_BANKS     2               /* number of banks */
 165 #define CFG_MAX_FLASH_SECT      128             /* sectors per device */
 166 #undef  CFG_FLASH_CHECKSUM
 167 #define CFG_FLASH_ERASE_TOUT    60000           /* Flash Erase Timeout (ms) */
 168 #define CFG_FLASH_WRITE_TOUT    500             /* Flash Write Timeout (ms) */
 169
 170 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 171
 172 #define CFG_FLASH_CFI_DRIVER
 173 #define CFG_FLASH_CFI
 174 #define CFG_FLASH_EMPTY_INFO
 175
 176 #define CFG_LBC_NONCACHE_BASE   0xf8000000
 177
 178 #define CFG_BR2_PRELIM          0xf8201001      /* port size 16bit */
 179 #define CFG_OR2_PRELIM          0xfff06ff7      /* 1MB Compact Flash area*/
 180
 181 #define CFG_BR3_PRELIM          0xf8100801      /* port size 8bit */
 182 #define CFG_OR3_PRELIM          0xfff06ff7      /* 1MB PIXIS area*/
 183
 184 #define PIXIS_BASE      0xf8100000      /* PIXIS registers */
 185 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 186 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 187 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 188 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 189 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch
 190                                          * register */
 191 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 192 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 193 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 194 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 195 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 196 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 197 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 198 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 199 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 200
 201
 202 /* define to use L1 as initial stack */
 203 #define CONFIG_L1_INIT_RAM      1
 204 #define CFG_INIT_L1_LOCK        1
 205 #define CFG_INIT_L1_ADDR        0xf4010000      /* Initial L1 address */
 206 #define CFG_INIT_L1_END         0x00004000      /* End of used area in RAM */
 207
 208 /* define to use L2SRAM as initial stack */
 209 #undef CONFIG_L2_INIT_RAM
 210 #define CFG_INIT_L2_ADDR        0xf8fc0000
 211 #define CFG_INIT_L2_END         0x00040000      /* End of used area in RAM */
 212
 213 #ifdef CONFIG_L1_INIT_RAM
 214 #define CFG_INIT_RAM_ADDR       CFG_INIT_L1_ADDR
 215 #define CFG_INIT_RAM_END        CFG_INIT_L1_END
 216 #else
 217 #define CFG_INIT_RAM_ADDR       CFG_INIT_L2_ADDR
 218 #define CFG_INIT_RAM_END        CFG_INIT_L2_END
 219 #endif
 220
 221 #define CFG_GBL_DATA_SIZE       128     /* num bytes initial data */
 222 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 223 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 224
 225 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 226 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 227
 228 /* Serial Port - controlled on board with jumper J8
 229  * open - index 2
 230  * shorted - index 1
 231  */
 232 #define CONFIG_CONS_INDEX       1
 233 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 234 #define CFG_NS16550
 235 #define CFG_NS16550_SERIAL
 236 #define CFG_NS16550_REG_SIZE    1
 237 #define CFG_NS16550_CLK         get_bus_freq(0)
 238
 239 #define CFG_BAUDRATE_TABLE      \
 240         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 241
 242 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 243 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 244
 245 /* Use the HUSH parser */
 246 #define CFG_HUSH_PARSER
 247 #ifdef  CFG_HUSH_PARSER
 248 #define CFG_PROMPT_HUSH_PS2 "> "
 249 #endif
 250
 251 /* pass open firmware flat tree */
 252 #define CONFIG_OF_FLAT_TREE     1
 253 #define CONFIG_OF_BOARD_SETUP   1
 254
 255 /* maximum size of the flat tree (8K) */
 256 #define OF_FLAT_TREE_MAX_SIZE   8192
 257
 258 #define OF_CPU                  "PowerPC,8544@0"
 259 #define OF_SOC                  "soc8544@e0000000"
 260 #define OF_TBCLK                (bd->bi_busfreq / 8)
 261 #define OF_STDOUT_PATH          "/soc8544@e0000000/serial@4500"
 262
 263 /* I2C */
 264 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 265 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 266 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 267 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 268 #define CFG_I2C_EEPROM_ADDR     0x57
 269 #define CFG_I2C_SLAVE           0x7F
 270 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 271 #define CFG_I2C_OFFSET          0x3100
 272
 273 /*
 274  * General PCI
 275  * Memory space is mapped 1-1, but I/O space must start from 0.
 276  */
 277 #define CFG_PCIE_PHYS           0x80000000      /* 1G PCIE TLB */
 278 #define CFG_PCI_PHYS            0xc0000000      /* 512M PCI TLB */
 279
 280 #define CFG_PCI1_MEM_BASE       0xc0000000
 281 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 282 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 283 #define CFG_PCI1_IO_BASE        0x00000000
 284 #define CFG_PCI1_IO_PHYS        0xe1000000
 285 #define CFG_PCI1_IO_SIZE        0x00010000      /* 64k */
 286
 287 /* PCI view of System Memory */
 288 #define CFG_PCI_MEMORY_BUS      0x00000000
 289 #define CFG_PCI_MEMORY_PHYS     0x00000000
 290 #define CFG_PCI_MEMORY_SIZE     0x80000000
 291
 292 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
 293 #define CFG_PCIE2_MEM_BASE      0x80000000
 294 #define CFG_PCIE2_MEM_PHYS      CFG_PCIE2_MEM_BASE
 295 #define CFG_PCIE2_MEM_SIZE      0x20000000      /* 512M */
 296 #define CFG_PCIE2_IO_BASE       0x00000000
 297 #define CFG_PCIE2_IO_PHYS       0xe1010000
 298 #define CFG_PCIE2_IO_SIZE       0x00010000      /* 64k */
 299
 300 /* controller 1, Slot 2,tgtid 2, Base address a000 */
 301 #define CFG_PCIE1_MEM_BASE      0xa0000000
 302 #define CFG_PCIE1_MEM_PHYS      CFG_PCIE1_MEM_BASE
 303 #define CFG_PCIE1_MEM_SIZE      0x10000000      /* 256M */
 304 #define CFG_PCIE1_IO_BASE       0x00000000
 305 #define CFG_PCIE1_IO_PHYS       0xe1020000
 306 #define CFG_PCIE1_IO_SIZE       0x00010000      /* 64k */
 307
 308 /* controller 3, direct to uli, tgtid 3, Base address b000 */
 309 #define CFG_PCIE3_MEM_BASE      0xb0000000
 310 #define CFG_PCIE3_MEM_PHYS      CFG_PCIE3_MEM_BASE
 311 #define CFG_PCIE3_MEM_SIZE      0x00100000      /* 1M */
 312 #define CFG_PCIE3_IO_BASE       0x00000000
 313 #define CFG_PCIE3_IO_PHYS       0xb0100000      /* reuse mem LAW */
 314 #define CFG_PCIE3_IO_SIZE       0x00100000      /* 1M */
 315
 316 #if defined(CONFIG_PCI)
 317
 318 #define CONFIG_NET_MULTI
 319 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 320
 321 #undef CONFIG_EEPRO100
 322 #undef CONFIG_TULIP
 323 #define CONFIG_RTL8139
 324
 325 #ifdef CONFIG_RTL8139
 326 /* This macro is used by RTL8139 but not defined in PPC architecture */
 327 #define KSEG1ADDR(x)            (x)
 328 #define _IO_BASE        0x00000000
 329 #endif
 330
 331 #ifndef CONFIG_PCI_PNP
 332         #define PCI_ENET0_IOADDR        CFG_PCI1_IO_BASE
 333         #define PCI_ENET0_MEMADDR       CFG_PCI1_IO_BASE
 334         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 335 #endif
 336
 337 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 338 #define CONFIG_DOS_PARTITION
 339 #define CONFIG_SCSI_AHCI
 340
 341 #ifdef CONFIG_SCSI_AHCI
 342 #define CONFIG_SATA_ULI5288
 343 #define CFG_SCSI_MAX_SCSI_ID    4
 344 #define CFG_SCSI_MAX_LUN        1
 345 #define CFG_SCSI_MAX_DEVICE     (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
 346 #define CFG_SCSI_MAXDEVICE      CFG_SCSI_MAX_DEVICE
 347 #endif /* SCSCI */
 348
 349 #endif  /* CONFIG_PCI */
 350
 351
 352 #if defined(CONFIG_TSEC_ENET)
 353
 354 #ifndef CONFIG_NET_MULTI
 355 #define CONFIG_NET_MULTI        1
 356 #endif
 357
 358 #define CONFIG_MII              1       /* MII PHY management */
 359 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 360 #define CONFIG_TSEC1    1
 361 #define CONFIG_TSEC1_NAME       "eTSEC1"
 362 #define CONFIG_TSEC3    1
 363 #define CONFIG_TSEC3_NAME       "eTSEC3"
 364
 365 #define TSEC1_PHY_ADDR          0
 366 #define TSEC3_PHY_ADDR          1
 367
 368 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 369 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 370
 371 #define TSEC1_PHYIDX            0
 372 #define TSEC3_PHYIDX            0
 373
 374 #define CONFIG_ETHPRIME         "eTSEC1"
 375
 376 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 377 #endif  /* CONFIG_TSEC_ENET */
 378
 379 /*
 380  * Environment
 381  */
 382 #define CFG_ENV_IS_IN_FLASH     1
 383 #if CFG_MONITOR_BASE > 0xfff80000
 384 #define CFG_ENV_ADDR            0xfff80000
 385 #else
 386 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 387 #endif
 388 #define CFG_ENV_SIZE            0x2000
 389 #define CFG_ENV_SECT_SIZE       0x10000 /* 64K (one sector) */
 390
 391 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 392 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 393
 394 /*
 395  * BOOTP options
 396  */
 397 #define CONFIG_BOOTP_BOOTFILESIZE
 398 #define CONFIG_BOOTP_BOOTPATH
 399 #define CONFIG_BOOTP_GATEWAY
 400 #define CONFIG_BOOTP_HOSTNAME
 401
 402
 403 /*
 404  * Command line configuration.
 405  */
 406 #include <config_cmd_default.h>
 407
 408 #define CONFIG_CMD_PING
 409 #define CONFIG_CMD_I2C
 410 #define CONFIG_CMD_MII
 411
 412 #if defined(CONFIG_PCI)
 413     #define CONFIG_CMD_PCI
 414     #define CONFIG_CMD_BEDBUG
 415     #define CONFIG_CMD_NET
 416     #define CONFIG_CMD_SCSI
 417     #define CONFIG_CMD_EXT2
 418 #endif
 419
 420
 421 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 422
 423 /*
 424  * Miscellaneous configurable options
 425  */
 426 #define CFG_LONGHELP                    /* undef to save memory */
 427 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 428 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 429 #if defined(CONFIG_CMD_KGDB)
 430 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 431 #else
 432 #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 433 #endif
 434 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 435 #define CFG_MAXARGS     16              /* max number of command args */
 436 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 437 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 438
 439 /*
 440  * For booting Linux, the board info and command line data
 441  * have to be in the first 8 MB of memory, since this is
 442  * the maximum mapped by the Linux kernel during initialization.
 443  */
 444 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 445
 446 /* Cache Configuration */
 447 #define CFG_DCACHE_SIZE         32768
 448 #define CFG_CACHELINE_SIZE      32
 449 #if defined(CONFIG_CMD_KGDB)
 450 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value*/
 451 #endif
 452
 453 /*
 454  * Internal Definitions
 455  *
 456  * Boot Flags
 457  */
 458 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 459 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 460
 461 #if defined(CONFIG_CMD_KGDB)
 462 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 463 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 464 #endif
 465
 466 /*
 467  * Environment Configuration
 468  */
 469
 470 /* The mac addresses for all ethernet interface */
 471 #if defined(CONFIG_TSEC_ENET)
 472 #define CONFIG_HAS_ETH0
 473 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 474 #define CONFIG_HAS_ETH1
 475 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 476 #define CONFIG_HAS_ETH2
 477 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 478 #define CONFIG_HAS_ETH3
 479 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 480 #endif
 481
 482 #define CONFIG_IPADDR   192.168.1.251
 483
 484 #define CONFIG_HOSTNAME 8544ds_unknown
 485 #define CONFIG_ROOTPATH /nfs/mpc85xx
 486 #define CONFIG_BOOTFILE 8544ds/uImage.uboot
 487 #define CONFIG_UBOOTPATH        8544ds/u-boot.bin       /* TFTP server */
 488
 489 #define CONFIG_SERVERIP 192.168.0.1
 490 #define CONFIG_GATEWAYIP 192.168.0.1
 491 #define CONFIG_NETMASK  255.255.0.0
 492
 493 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 494
 495 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 496 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 497
 498 #define CONFIG_BAUDRATE 115200
 499
 500 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
 501 #define PCIE_ENV \
 502  "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
 503         "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
 504  "pcieerr=md ${a}020 1; md ${a}e00 e;"          \
 505         "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"  \
 506         "pci d.w $b.0 56 1;"                    \
 507         "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
 508  "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;"   \
 509         "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \
 510         "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
 511         "pci w $b.0 130 ffffffff\0" \
 512  "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"       \
 513  "pcie1regs=setenv a e000a; run pciereg\0"      \
 514  "pcie2regs=setenv a e0009; run pciereg\0"      \
 515  "pcie3regs=setenv a e000b; run pciereg\0"      \
 516  "pcie1cfg=setenv b 3; run pciecfg\0" \
 517  "pcie2cfg=setenv b 5; run pciecfg\0" \
 518  "pcie3cfg=setenv b 0; run pciecfg\0" \
 519  "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0"   \
 520  "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0"   \
 521  "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0"   \
 522  "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
 523  "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
 524  "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
 525 #else
 526 #define PCIE_ENV ""
 527 #endif
 528
 529 #if defined(CONFIG_PCI1)
 530 #define PCI_ENV \
 531  "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
 532         "echo e;md ${a}e00 9\0"                 \
 533  "pci1regs=setenv a e0008; run pcireg\0"        \
 534  "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
 535         "pci d.w $b.0 56 1\0"                   \
 536  "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
 537         "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"          \
 538  "pci1err=setenv a e0008; setenv b 7; run pcierr\0"             \
 539  "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
 540 #else
 541 #define PCI_ENV ""
 542 #endif
 543
 544 #if defined(CONFIG_TSEC_ENET)
 545 #define ENET_ENV \
 546  "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
 547         "md ${a}098 2\0" \
 548  "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
 549  "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
 550  "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
 551         "echo mib;md ${a}680 31\0" \
 552  "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
 553  "enet1regs=setenv a e0024; run enetreg\0" \
 554  "enet3regs=setenv a e0026; run enetreg\0"
 555 #else
 556 #define ENET_ENV ""
 557 #endif
 558
 559 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 560  "netdev=eth0\0"                                                \
 561  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 562  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 563         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 564         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 565         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 566         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 567         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 568  "consoledev=ttyS0\0"                           \
 569  "ramdiskaddr=2000000\0"                        \
 570  "ramdiskfile=8544ds/ramdisk.uboot\0"           \
 571  "dtbaddr=c00000\0"                             \
 572  "dtbfile=8544ds/mpc8544ds.dtb\0"               \
 573  "bdev=sda3\0"                                  \
 574  "eoi=mw e00400b0 0\0"                          \
 575  "iack=md e00400a0 1\0"                         \
 576  "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
 577         "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
 578  "ddrregs=setenv a e0002; run ddrreg\0"         \
 579  "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
 580         "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0"   \
 581  "guregs=setenv a e00e0; run gureg\0"           \
 582  "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
 583  "ecmregs=setenv a e0001; run ecmreg\0"         \
 584  "lawregs=md e0000c08 4b\0" \
 585  "lbcregs=md e0005000 36\0" \
 586  "dma0regs=md e0021100 12\0" \
 587  "dma1regs=md e0021180 12\0" \
 588  "dma2regs=md e0021200 12\0" \
 589  "dma3regs=md e0021280 12\0" \
 590  PCIE_ENV       \
 591  PCI_ENV        \
 592  ENET_ENV
 593
 594
 595 #define CONFIG_NFSBOOTCOMMAND           \
 596  "setenv bootargs root=/dev/nfs rw "    \
 597  "nfsroot=$serverip:$rootpath "         \
 598  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 599  "console=$consoledev,$baudrate $othbootargs;"  \
 600  "tftp $loadaddr $bootfile;"            \
 601  "tftp $dtbaddr $dtbfile;"              \
 602  "bootm $loadaddr - $dtbaddr"
 603
 604
 605 #define CONFIG_RAMBOOTCOMMAND           \
 606  "setenv bootargs root=/dev/ram rw "    \
 607  "console=$consoledev,$baudrate $othbootargs;"  \
 608  "tftp $ramdiskaddr $ramdiskfile;"      \
 609  "tftp $loadaddr $bootfile;"            \
 610  "tftp $dtbaddr $dtbfile;"              \
 611  "bootm $loadaddr $ramdiskaddr $dtbaddr"
 612
 613 #define CONFIG_BOOTCOMMAND              \
 614  "setenv bootargs root=/dev/$bdev rw "  \
 615  "console=$consoledev,$baudrate $othbootargs;"  \
 616  "tftp $loadaddr $bootfile;"            \
 617  "tftp $dtbaddr $dtbfile;"              \
 618  "bootm $loadaddr - $dtbaddr"
 619
 620 #endif  /* __CONFIG_H */