include/configs/MPC8544DS.h

   1 /*
   2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8544ds board configuration file
   9  *
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_PCI1             1       /* PCI controller 1 */
  15 #define CONFIG_PCIE1            1       /* PCIE controller 1 (slot 1) */
  16 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot 2) */
  17 #define CONFIG_PCIE3            1       /* PCIE controller 3 (ULI bridge) */
  18 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  19 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  20 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  21 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  22
  23 #define CONFIG_ENV_OVERWRITE
  24 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  25
  26 #ifndef __ASSEMBLY__
  27 extern unsigned long get_board_sys_clk(unsigned long dummy);
  28 #endif
  29 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  30
  31 /*
  32  * These can be toggled for performance analysis, otherwise use default.
  33  */
  34 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  35 #define CONFIG_BTB                      /* toggle branch predition */
  36
  37 /*
  38  * Only possible on E500 Version 2 or newer cores.
  39  */
  40 #define CONFIG_ENABLE_36BIT_PHYS        1
  41
  42 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  43 #define CONFIG_SYS_MEMTEST_END          0x00400000
  44
  45 #define CONFIG_SYS_CCSRBAR              0xe0000000
  46 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  47
  48 /* DDR Setup */
  49 #undef CONFIG_FSL_DDR_INTERACTIVE
  50 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  51 #define CONFIG_DDR_SPD
  52
  53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  54 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  55
  56 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  57 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  58 #define CONFIG_VERY_BIG_RAM
  59
  60 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  61 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
  62
  63 /* I2C addresses of SPD EEPROMs */
  64 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
  65
  66 /* Make sure required options are set */
  67 #ifndef CONFIG_SPD_EEPROM
  68 #error ("CONFIG_SPD_EEPROM is required")
  69 #endif
  70
  71 #undef CONFIG_CLOCKS_IN_MHZ
  72
  73 /*
  74  * Memory map
  75  *
  76  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
  77  *
  78  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
  79  *
  80  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
  81  *
  82  * 0xe000_0000  0xe00f_ffff     CCSR                    1M non-cacheable
  83  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
  84  *
  85  * Localbus cacheable
  86  *
  87  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M Cacheable
  88  * 0xf401_0000  0xf401_3fff     L1 for stack            4K Cacheable TLB0
  89  *
  90  * Localbus non-cacheable
  91  *
  92  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS (*)        1M non-cacheable
  93  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M non-cacheable
  94  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M non-cacheable
  95  *
  96  */
  97
  98 /*
  99  * Local Bus Definitions
 100  */
 101 #define CONFIG_SYS_BOOT_BLOCK           0xfc000000      /* boot TLB */
 102
 103 #define CONFIG_SYS_FLASH_BASE           0xff800000      /* start of FLASH 8M */
 104
 105 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 106 #define CONFIG_SYS_BR1_PRELIM           0xfe801001
 107
 108 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 109 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 110
 111 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 112
 113 #define CONFIG_SYS_FLASH_QUIET_TEST
 114 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 115 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 116 #undef  CONFIG_SYS_FLASH_CHECKSUM
 117 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 118 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 119 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 120
 121 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 122
 123 #define CONFIG_FLASH_CFI_DRIVER
 124 #define CONFIG_SYS_FLASH_CFI
 125 #define CONFIG_SYS_FLASH_EMPTY_INFO
 126
 127 #define CONFIG_SYS_LBC_NONCACHE_BASE    0xf8000000
 128
 129 #define CONFIG_SYS_BR2_PRELIM           0xf8201001      /* port size 16bit */
 130 #define CONFIG_SYS_OR2_PRELIM           0xfff06ff7      /* 1MB Compact Flash area*/
 131
 132 #define CONFIG_SYS_BR3_PRELIM           0xf8100801      /* port size 8bit */
 133 #define CONFIG_SYS_OR3_PRELIM           0xfff06ff7      /* 1MB PIXIS area*/
 134
 135 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 136 #define PIXIS_BASE      0xf8100000      /* PIXIS registers */
 137 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 138 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 139 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 140 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 141 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch
 142                                          * register */
 143 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 144 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 145 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 146 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 147 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 148 #define PIXIS_VBOOT_FMAP        0x80    /* VBOOT - CFG_FLASHMAP */
 149 #define PIXIS_VBOOT_FBANK       0x40    /* VBOOT - CFG_FLASHBANK */
 150 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 151 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 152 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 153 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 154 #define PIXIS_VSPEED2           0x1d    /* VELA VSpeed 2 */
 155 #define CONFIG_SYS_PIXIS_VBOOT_MASK     0x40    /* Reset altbank mask*/
 156 #define PIXIS_VSPEED2_TSEC1SER  0x2
 157 #define PIXIS_VSPEED2_TSEC3SER  0x1
 158 #define PIXIS_VCFGEN1_TSEC1SER  0x20
 159 #define PIXIS_VCFGEN1_TSEC3SER  0x40
 160 #define PIXIS_VSPEED2_MASK      (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
 161 #define PIXIS_VCFGEN1_MASK      (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
 162
 163 #define CONFIG_SYS_INIT_RAM_LOCK      1
 164 #define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
 165 #define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
 166
 167 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 168 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 169
 170 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 171 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 172
 173 /* Serial Port - controlled on board with jumper J8
 174  * open - index 2
 175  * shorted - index 1
 176  */
 177 #define CONFIG_SYS_NS16550_SERIAL
 178 #define CONFIG_SYS_NS16550_REG_SIZE     1
 179 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 180
 181 #define CONFIG_SYS_BAUDRATE_TABLE       \
 182         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 183
 184 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 185 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 186
 187 /* I2C */
 188 #define CONFIG_SYS_I2C
 189 #define CONFIG_SYS_I2C_FSL
 190 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 191 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 192 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 193 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 194 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 195
 196 /*
 197  * General PCI
 198  * Memory space is mapped 1-1, but I/O space must start from 0.
 199  */
 200 #define CONFIG_SYS_PCIE_VIRT            0x80000000      /* 1G PCIE TLB */
 201 #define CONFIG_SYS_PCIE_PHYS            0x80000000      /* 1G PCIE TLB */
 202 #define CONFIG_SYS_PCI_VIRT             0xc0000000      /* 512M PCI TLB */
 203 #define CONFIG_SYS_PCI_PHYS             0xc0000000      /* 512M PCI TLB */
 204
 205 #define CONFIG_SYS_PCI1_MEM_VIRT        0xc0000000
 206 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
 207 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc0000000
 208 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 209 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
 210 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 211 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
 212 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000      /* 64k */
 213
 214 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
 215 #define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 216 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x80000000
 217 #define CONFIG_SYS_PCIE2_MEM_BUS        0x80000000
 218 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x80000000
 219 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 220 #define CONFIG_SYS_PCIE2_IO_VIRT        0xe1010000
 221 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
 222 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe1010000
 223 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 224
 225 /* controller 1, Slot 2,tgtid 2, Base address a000 */
 226 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
 227 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 228 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 229 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 230 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 231 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe1020000
 232 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 233 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe1020000
 234 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 235
 236 /* controller 3, direct to uli, tgtid 3, Base address b000 */
 237 #define CONFIG_SYS_PCIE3_NAME           "ULI"
 238 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 239 #define CONFIG_SYS_PCIE3_MEM_BUS        0xb0000000
 240 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xb0000000
 241 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x00100000      /* 1M */
 242 #define CONFIG_SYS_PCIE3_IO_VIRT        0xb0100000      /* reuse mem LAW */
 243 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
 244 #define CONFIG_SYS_PCIE3_IO_PHYS        0xb0100000      /* reuse mem LAW */
 245 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00100000      /* 1M */
 246 #define CONFIG_SYS_PCIE3_MEM_VIRT2      0xb0200000
 247 #define CONFIG_SYS_PCIE3_MEM_BUS2       0xb0200000
 248 #define CONFIG_SYS_PCIE3_MEM_PHYS2      0xb0200000
 249 #define CONFIG_SYS_PCIE3_MEM_SIZE2      0x00200000      /* 1M */
 250
 251 #if defined(CONFIG_PCI)
 252
 253 /*PCIE video card used*/
 254 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE2_IO_VIRT
 255
 256 /*PCI video card used*/
 257 /*#define VIDEO_IO_OFFSET       CONFIG_SYS_PCI1_IO_VIRT*/
 258
 259 /* video */
 260
 261 #if defined(CONFIG_VIDEO)
 262 #define CONFIG_BIOSEMU
 263 #define CONFIG_ATI_RADEON_FB
 264 #define CONFIG_VIDEO_LOGO
 265 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 266 #endif
 267
 268 #undef CONFIG_EEPRO100
 269 #undef CONFIG_TULIP
 270
 271 #ifndef CONFIG_PCI_PNP
 272         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
 273         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
 274         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 275 #endif
 276
 277 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 278
 279 #ifdef CONFIG_SCSI_AHCI
 280 #define CONFIG_SATA_ULI5288
 281 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 282 #define CONFIG_SYS_SCSI_MAX_LUN 1
 283 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 284 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 285 #endif /* SCSCI */
 286
 287 #endif  /* CONFIG_PCI */
 288
 289 #if defined(CONFIG_TSEC_ENET)
 290
 291 #define CONFIG_MII              1       /* MII PHY management */
 292 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 293 #define CONFIG_TSEC1    1
 294 #define CONFIG_TSEC1_NAME       "eTSEC1"
 295 #define CONFIG_TSEC3    1
 296 #define CONFIG_TSEC3_NAME       "eTSEC3"
 297
 298 #define CONFIG_PIXIS_SGMII_CMD
 299 #define CONFIG_FSL_SGMII_RISER  1
 300 #define SGMII_RISER_PHY_OFFSET  0x1c
 301
 302 #define TSEC1_PHY_ADDR          0
 303 #define TSEC3_PHY_ADDR          1
 304
 305 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 306 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 307
 308 #define TSEC1_PHYIDX            0
 309 #define TSEC3_PHYIDX            0
 310
 311 #define CONFIG_ETHPRIME         "eTSEC1"
 312 #endif  /* CONFIG_TSEC_ENET */
 313
 314 /*
 315  * Environment
 316  */
 317 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) */
 318 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 319 #define CONFIG_ENV_ADDR         0xfff80000
 320 #else
 321 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 322 #endif
 323 #define CONFIG_ENV_SIZE         0x2000
 324
 325 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 326 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 327
 328 /*
 329  * BOOTP options
 330  */
 331 #define CONFIG_BOOTP_BOOTFILESIZE
 332
 333 /*
 334  * USB
 335  */
 336
 337 #ifdef CONFIG_USB_EHCI_HCD
 338 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 339 #define CONFIG_PCI_EHCI_DEVICE                  0
 340 #endif
 341
 342 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 343
 344 /*
 345  * Miscellaneous configurable options
 346  */
 347 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 348
 349 /*
 350  * For booting Linux, the board info and command line data
 351  * have to be in the first 64 MB of memory, since this is
 352  * the maximum mapped by the Linux kernel during initialization.
 353  */
 354 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 355 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 356
 357 #if defined(CONFIG_CMD_KGDB)
 358 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 359 #endif
 360
 361 /*
 362  * Environment Configuration
 363  */
 364
 365 /* The mac addresses for all ethernet interface */
 366 #if defined(CONFIG_TSEC_ENET)
 367 #define CONFIG_HAS_ETH0
 368 #define CONFIG_HAS_ETH1
 369 #endif
 370
 371 #define CONFIG_IPADDR   192.168.1.251
 372
 373 #define CONFIG_HOSTNAME "8544ds_unknown"
 374 #define CONFIG_ROOTPATH "/nfs/mpc85xx"
 375 #define CONFIG_BOOTFILE "8544ds/uImage.uboot"
 376 #define CONFIG_UBOOTPATH        8544ds/u-boot.bin       /* TFTP server */
 377
 378 #define CONFIG_SERVERIP 192.168.1.1
 379 #define CONFIG_GATEWAYIP 192.168.1.1
 380 #define CONFIG_NETMASK  255.255.0.0
 381
 382 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 383
 384 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 385 "netdev=eth0\0"                                         \
 386 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 387 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 388         "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 389                 " +$filesize; " \
 390         "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 391                 " +$filesize; " \
 392         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 393                 " $filesize; "  \
 394         "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 395                 " +$filesize; " \
 396         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 397                 " $filesize\0"  \
 398 "consoledev=ttyS0\0"                            \
 399 "ramdiskaddr=2000000\0"                 \
 400 "ramdiskfile=8544ds/ramdisk.uboot\0"            \
 401 "fdtaddr=1e00000\0"                             \
 402 "fdtfile=8544ds/mpc8544ds.dtb\0"                \
 403 "bdev=sda3\0"
 404
 405 #define CONFIG_NFSBOOTCOMMAND           \
 406  "setenv bootargs root=/dev/nfs rw "    \
 407  "nfsroot=$serverip:$rootpath "         \
 408  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 409  "console=$consoledev,$baudrate $othbootargs;"  \
 410  "tftp $loadaddr $bootfile;"            \
 411  "tftp $fdtaddr $fdtfile;"              \
 412  "bootm $loadaddr - $fdtaddr"
 413
 414 #define CONFIG_RAMBOOTCOMMAND           \
 415  "setenv bootargs root=/dev/ram rw "    \
 416  "console=$consoledev,$baudrate $othbootargs;"  \
 417  "tftp $ramdiskaddr $ramdiskfile;"      \
 418  "tftp $loadaddr $bootfile;"            \
 419  "tftp $fdtaddr $fdtfile;"              \
 420  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 421
 422 #define CONFIG_BOOTCOMMAND              \
 423  "setenv bootargs root=/dev/$bdev rw "  \
 424  "console=$consoledev,$baudrate $othbootargs;"  \
 425  "tftp $loadaddr $bootfile;"            \
 426  "tftp $fdtaddr $fdtfile;"              \
 427  "bootm $loadaddr - $fdtaddr"
 428
 429 #endif  /* __CONFIG_H */