include/configs/MPC8544DS.h

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8544ds board configuration file
  25  *
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_BOOKE            1       /* BOOKE */
  32 #define CONFIG_E500             1       /* BOOKE e500 family */
  33 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  34 #define CONFIG_MPC8544          1
  35 #define CONFIG_MPC8544DS        1
  36
  37 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  38 #define CONFIG_PCI1             1       /* PCI controller 1 */
  39 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  40 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  41 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
  42 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  43
  44 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  45 #define CONFIG_ENV_OVERWRITE
  46 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  47 #undef CONFIG_DDR_DLL
  48 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
  49
  50 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  52 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  53
  54 #define CONFIG_DDR_ECC_CMD
  55 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  56
  57 /*
  58  * When initializing flash, if we cannot find the manufacturer ID,
  59  * assume this is the AMD flash associated with the CDS board.
  60  * This allows booting from a promjet.
  61  */
  62 #define CONFIG_ASSUME_AMD_FLASH
  63
  64 #define MPC85xx_DDR_SDRAM_CLK_CNTL      /* 85xx has clock control reg */
  65
  66 #ifndef __ASSEMBLY__
  67 extern unsigned long get_board_sys_clk(unsigned long dummy);
  68 #endif
  69 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  70
  71 /*
  72  * These can be toggled for performance analysis, otherwise use default.
  73  */
  74 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  75 #define CONFIG_BTB                      /* toggle branch predition */
  76 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  77 #define CONFIG_CLEAR_LAW0               /* Clear LAW0 in cpu_init_r */
  78
  79 /*
  80  * Only possible on E500 Version 2 or newer cores.
  81  */
  82 #define CONFIG_ENABLE_36BIT_PHYS        1
  83
  84 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  85
  86 #undef  CFG_DRAM_TEST                   /* memory test, takes time */
  87 #define CFG_MEMTEST_START       0x00200000      /* memtest works on */
  88 #define CFG_MEMTEST_END         0x00400000
  89 #define CFG_ALT_MEMTEST
  90 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  91
  92 /*
  93  * Base addresses -- Note these are effective addresses where the
  94  * actual resources get mapped (not physical addresses)
  95  */
  96 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
  97 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
  98 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
  99
 100 #define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
 101 #define CFG_PCIE1_ADDR          (CFG_CCSRBAR+0xa000)
 102 #define CFG_PCIE2_ADDR          (CFG_CCSRBAR+0x9000)
 103 #define CFG_PCIE3_ADDR          (CFG_CCSRBAR+0xb000)
 104
 105 /*
 106  * DDR Setup
 107  */
 108 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 109 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 110
 111 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 112
 113 /*
 114  * Make sure required options are set
 115  */
 116 #ifndef CONFIG_SPD_EEPROM
 117 #error ("CONFIG_SPD_EEPROM is required")
 118 #endif
 119
 120 #undef CONFIG_CLOCKS_IN_MHZ
 121
 122 /*
 123  * Memory map
 124  *
 125  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 126  *
 127  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
 128  *
 129  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
 130  *
 131  * 0xe000_0000  0xe00f_ffff     CCSR                    1M non-cacheable
 132  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
 133  *
 134  * Localbus cacheable
 135  *
 136  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M Cacheable
 137  * 0xf401_0000  0xf401_3fff     L1 for stack            4K Cacheable TLB0
 138  *
 139  * Localbus non-cacheable
 140  *
 141  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS (*)        1M non-cacheable
 142  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M non-cacheable
 143  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M non-cacheable
 144  *
 145  */
 146
 147 /*
 148  * Local Bus Definitions
 149  */
 150 #define CFG_BOOT_BLOCK          0xfc000000      /* boot TLB */
 151
 152 #define CFG_LBC_CACHE_BASE      0xf0000000      /* Localbus cacheable */
 153
 154 #define CFG_FLASH_BASE          0xff800000      /* start of FLASH 8M */
 155
 156 #define CFG_BR0_PRELIM          0xff801001
 157 #define CFG_BR1_PRELIM          0xfe801001
 158
 159 #define CFG_OR0_PRELIM          0xff806e65
 160 #define CFG_OR1_PRELIM          0xff806e65
 161
 162 #define CFG_FLASH_BANKS_LIST    {0xfe800000,CFG_FLASH_BASE}
 163
 164 #define CFG_MAX_FLASH_BANKS     2               /* number of banks */
 165 #define CFG_MAX_FLASH_SECT      128             /* sectors per device */
 166 #undef  CFG_FLASH_CHECKSUM
 167 #define CFG_FLASH_ERASE_TOUT    60000           /* Flash Erase Timeout (ms) */
 168 #define CFG_FLASH_WRITE_TOUT    500             /* Flash Write Timeout (ms) */
 169
 170 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 171
 172 #define CFG_FLASH_CFI_DRIVER
 173 #define CFG_FLASH_CFI
 174 #define CFG_FLASH_EMPTY_INFO
 175
 176 #define CFG_LBC_NONCACHE_BASE   0xf8000000
 177
 178 #define CFG_BR2_PRELIM          0xf8201001      /* port size 16bit */
 179 #define CFG_OR2_PRELIM          0xfff06ff7      /* 1MB Compact Flash area*/
 180
 181 #define CFG_BR3_PRELIM          0xf8100801      /* port size 8bit */
 182 #define CFG_OR3_PRELIM          0xfff06ff7      /* 1MB PIXIS area*/
 183
 184 #define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 185 #define PIXIS_BASE      0xf8100000      /* PIXIS registers */
 186 #define PIXIS_ID                0x0     /* Board ID at offset 0 */
 187 #define PIXIS_VER               0x1     /* Board version at offset 1 */
 188 #define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 189 #define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 190 #define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch
 191                                          * register */
 192 #define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 193 #define PIXIS_VCTL              0x10    /* VELA Control Register */
 194 #define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 195 #define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 196 #define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 197 #define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 198 #define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 199 #define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 200 #define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 201
 202
 203 /* define to use L1 as initial stack */
 204 #define CONFIG_L1_INIT_RAM      1
 205 #define CFG_INIT_L1_LOCK        1
 206 #define CFG_INIT_L1_ADDR        0xf4010000      /* Initial L1 address */
 207 #define CFG_INIT_L1_END         0x00004000      /* End of used area in RAM */
 208
 209 /* define to use L2SRAM as initial stack */
 210 #undef CONFIG_L2_INIT_RAM
 211 #define CFG_INIT_L2_ADDR        0xf8fc0000
 212 #define CFG_INIT_L2_END         0x00040000      /* End of used area in RAM */
 213
 214 #ifdef CONFIG_L1_INIT_RAM
 215 #define CFG_INIT_RAM_ADDR       CFG_INIT_L1_ADDR
 216 #define CFG_INIT_RAM_END        CFG_INIT_L1_END
 217 #else
 218 #define CFG_INIT_RAM_ADDR       CFG_INIT_L2_ADDR
 219 #define CFG_INIT_RAM_END        CFG_INIT_L2_END
 220 #endif
 221
 222 #define CFG_GBL_DATA_SIZE       128     /* num bytes initial data */
 223 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 224 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 225
 226 #define CFG_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
 227 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 228
 229 /* Serial Port - controlled on board with jumper J8
 230  * open - index 2
 231  * shorted - index 1
 232  */
 233 #define CONFIG_CONS_INDEX       1
 234 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 235 #define CFG_NS16550
 236 #define CFG_NS16550_SERIAL
 237 #define CFG_NS16550_REG_SIZE    1
 238 #define CFG_NS16550_CLK         get_bus_freq(0)
 239
 240 #define CFG_BAUDRATE_TABLE      \
 241         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 242
 243 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 244 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 245
 246 /* Use the HUSH parser */
 247 #define CFG_HUSH_PARSER
 248 #ifdef  CFG_HUSH_PARSER
 249 #define CFG_PROMPT_HUSH_PS2 "> "
 250 #endif
 251
 252 /* pass open firmware flat tree */
 253 #define CONFIG_OF_FLAT_TREE     1
 254 #define CONFIG_OF_BOARD_SETUP   1
 255
 256 #define OF_CPU                  "PowerPC,8544@0"
 257 #define OF_SOC                  "soc8544@e0000000"
 258 #define OF_TBCLK                (bd->bi_busfreq / 8)
 259 #define OF_STDOUT_PATH          "/soc8544@e0000000/serial@4500"
 260
 261 /* I2C */
 262 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 263 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 264 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 265 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 266 #define CFG_I2C_EEPROM_ADDR     0x57
 267 #define CFG_I2C_SLAVE           0x7F
 268 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 269 #define CFG_I2C_OFFSET          0x3100
 270
 271 /*
 272  * General PCI
 273  * Memory space is mapped 1-1, but I/O space must start from 0.
 274  */
 275 #define CFG_PCIE_PHYS           0x80000000      /* 1G PCIE TLB */
 276 #define CFG_PCI_PHYS            0xc0000000      /* 512M PCI TLB */
 277
 278 #define CFG_PCI1_MEM_BASE       0xc0000000
 279 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 280 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 281 #define CFG_PCI1_IO_BASE        0x00000000
 282 #define CFG_PCI1_IO_PHYS        0xe1000000
 283 #define CFG_PCI1_IO_SIZE        0x00010000      /* 64k */
 284
 285 /* PCI view of System Memory */
 286 #define CFG_PCI_MEMORY_BUS      0x00000000
 287 #define CFG_PCI_MEMORY_PHYS     0x00000000
 288 #define CFG_PCI_MEMORY_SIZE     0x80000000
 289
 290 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
 291 #define CFG_PCIE2_MEM_BASE      0x80000000
 292 #define CFG_PCIE2_MEM_PHYS      CFG_PCIE2_MEM_BASE
 293 #define CFG_PCIE2_MEM_SIZE      0x20000000      /* 512M */
 294 #define CFG_PCIE2_IO_BASE       0x00000000
 295 #define CFG_PCIE2_IO_PHYS       0xe1010000
 296 #define CFG_PCIE2_IO_SIZE       0x00010000      /* 64k */
 297
 298 /* controller 1, Slot 2,tgtid 2, Base address a000 */
 299 #define CFG_PCIE1_MEM_BASE      0xa0000000
 300 #define CFG_PCIE1_MEM_PHYS      CFG_PCIE1_MEM_BASE
 301 #define CFG_PCIE1_MEM_SIZE      0x10000000      /* 256M */
 302 #define CFG_PCIE1_IO_BASE       0x00000000
 303 #define CFG_PCIE1_IO_PHYS       0xe1020000
 304 #define CFG_PCIE1_IO_SIZE       0x00010000      /* 64k */
 305
 306 /* controller 3, direct to uli, tgtid 3, Base address b000 */
 307 #define CFG_PCIE3_MEM_BASE      0xb0000000
 308 #define CFG_PCIE3_MEM_PHYS      CFG_PCIE3_MEM_BASE
 309 #define CFG_PCIE3_MEM_SIZE      0x00100000      /* 1M */
 310 #define CFG_PCIE3_IO_BASE       0x00000000
 311 #define CFG_PCIE3_IO_PHYS       0xb0100000      /* reuse mem LAW */
 312 #define CFG_PCIE3_IO_SIZE       0x00100000      /* 1M */
 313 #define CFG_PCIE3_MEM_BASE2     0xb0200000
 314 #define CFG_PCIE3_MEM_PHYS2     CFG_PCIE3_MEM_BASE2
 315 #define CFG_PCIE3_MEM_SIZE2     0x00200000      /* 1M */
 316
 317 #if defined(CONFIG_PCI)
 318
 319 #define CONFIG_NET_MULTI
 320 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 321
 322 #undef CONFIG_EEPRO100
 323 #undef CONFIG_TULIP
 324 #define CONFIG_RTL8139
 325
 326 #ifdef CONFIG_RTL8139
 327 /* This macro is used by RTL8139 but not defined in PPC architecture */
 328 #define KSEG1ADDR(x)            (x)
 329 #define _IO_BASE        0x00000000
 330 #endif
 331
 332 #ifndef CONFIG_PCI_PNP
 333         #define PCI_ENET0_IOADDR        CFG_PCI1_IO_BASE
 334         #define PCI_ENET0_MEMADDR       CFG_PCI1_IO_BASE
 335         #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 336 #endif
 337
 338 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 339 #define CONFIG_DOS_PARTITION
 340 #define CONFIG_SCSI_AHCI
 341
 342 #ifdef CONFIG_SCSI_AHCI
 343 #define CONFIG_SATA_ULI5288
 344 #define CFG_SCSI_MAX_SCSI_ID    4
 345 #define CFG_SCSI_MAX_LUN        1
 346 #define CFG_SCSI_MAX_DEVICE     (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
 347 #define CFG_SCSI_MAXDEVICE      CFG_SCSI_MAX_DEVICE
 348 #endif /* SCSCI */
 349
 350 #endif  /* CONFIG_PCI */
 351
 352
 353 #if defined(CONFIG_TSEC_ENET)
 354
 355 #ifndef CONFIG_NET_MULTI
 356 #define CONFIG_NET_MULTI        1
 357 #endif
 358
 359 #define CONFIG_MII              1       /* MII PHY management */
 360 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 361 #define CONFIG_TSEC1    1
 362 #define CONFIG_TSEC1_NAME       "eTSEC1"
 363 #define CONFIG_TSEC3    1
 364 #define CONFIG_TSEC3_NAME       "eTSEC3"
 365
 366 #define TSEC1_PHY_ADDR          0
 367 #define TSEC3_PHY_ADDR          1
 368
 369 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 370 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 371
 372 #define TSEC1_PHYIDX            0
 373 #define TSEC3_PHYIDX            0
 374
 375 #define CONFIG_ETHPRIME         "eTSEC1"
 376
 377 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 378 #endif  /* CONFIG_TSEC_ENET */
 379
 380 /*
 381  * Environment
 382  */
 383 #define CFG_ENV_IS_IN_FLASH     1
 384 #if CFG_MONITOR_BASE > 0xfff80000
 385 #define CFG_ENV_ADDR            0xfff80000
 386 #else
 387 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 388 #endif
 389 #define CFG_ENV_SIZE            0x2000
 390 #define CFG_ENV_SECT_SIZE       0x10000 /* 64K (one sector) */
 391
 392 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 393 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 394
 395 /*
 396  * BOOTP options
 397  */
 398 #define CONFIG_BOOTP_BOOTFILESIZE
 399 #define CONFIG_BOOTP_BOOTPATH
 400 #define CONFIG_BOOTP_GATEWAY
 401 #define CONFIG_BOOTP_HOSTNAME
 402
 403
 404 /*
 405  * Command line configuration.
 406  */
 407 #include <config_cmd_default.h>
 408
 409 #define CONFIG_CMD_PING
 410 #define CONFIG_CMD_I2C
 411 #define CONFIG_CMD_MII
 412
 413 #if defined(CONFIG_PCI)
 414     #define CONFIG_CMD_PCI
 415     #define CONFIG_CMD_BEDBUG
 416     #define CONFIG_CMD_NET
 417     #define CONFIG_CMD_SCSI
 418     #define CONFIG_CMD_EXT2
 419 #endif
 420
 421
 422 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 423
 424 /*
 425  * Miscellaneous configurable options
 426  */
 427 #define CFG_LONGHELP                    /* undef to save memory */
 428 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 429 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 430 #if defined(CONFIG_CMD_KGDB)
 431 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 432 #else
 433 #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 434 #endif
 435 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 436 #define CFG_MAXARGS     16              /* max number of command args */
 437 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 438 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 439
 440 /*
 441  * For booting Linux, the board info and command line data
 442  * have to be in the first 8 MB of memory, since this is
 443  * the maximum mapped by the Linux kernel during initialization.
 444  */
 445 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 446
 447 /* Cache Configuration */
 448 #define CFG_DCACHE_SIZE         32768
 449 #define CFG_CACHELINE_SIZE      32
 450 #if defined(CONFIG_CMD_KGDB)
 451 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value*/
 452 #endif
 453
 454 /*
 455  * Internal Definitions
 456  *
 457  * Boot Flags
 458  */
 459 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 460 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 461
 462 #if defined(CONFIG_CMD_KGDB)
 463 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 464 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 465 #endif
 466
 467 /*
 468  * Environment Configuration
 469  */
 470
 471 /* The mac addresses for all ethernet interface */
 472 #if defined(CONFIG_TSEC_ENET)
 473 #define CONFIG_HAS_ETH0
 474 #define CONFIG_ETHADDR  00:E0:0C:02:00:FD
 475 #define CONFIG_HAS_ETH1
 476 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
 477 #define CONFIG_HAS_ETH2
 478 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
 479 #define CONFIG_HAS_ETH3
 480 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
 481 #endif
 482
 483 #define CONFIG_IPADDR   192.168.1.251
 484
 485 #define CONFIG_HOSTNAME 8544ds_unknown
 486 #define CONFIG_ROOTPATH /nfs/mpc85xx
 487 #define CONFIG_BOOTFILE 8544ds/uImage.uboot
 488 #define CONFIG_UBOOTPATH        8544ds/u-boot.bin       /* TFTP server */
 489
 490 #define CONFIG_SERVERIP 192.168.0.1
 491 #define CONFIG_GATEWAYIP 192.168.0.1
 492 #define CONFIG_NETMASK  255.255.0.0
 493
 494 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 495
 496 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 497 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 498
 499 #define CONFIG_BAUDRATE 115200
 500
 501 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
 502 #define PCIE_ENV \
 503  "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
 504         "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
 505  "pcieerr=md ${a}020 1; md ${a}e00 e;"          \
 506         "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"  \
 507         "pci d.w $b.0 56 1;"                    \
 508         "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
 509  "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;"   \
 510         "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \
 511         "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
 512         "pci w $b.0 130 ffffffff\0" \
 513  "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"       \
 514  "pcie1regs=setenv a e000a; run pciereg\0"      \
 515  "pcie2regs=setenv a e0009; run pciereg\0"      \
 516  "pcie3regs=setenv a e000b; run pciereg\0"      \
 517  "pcie1cfg=setenv b 3; run pciecfg\0" \
 518  "pcie2cfg=setenv b 5; run pciecfg\0" \
 519  "pcie3cfg=setenv b 0; run pciecfg\0" \
 520  "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0"   \
 521  "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0"   \
 522  "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0"   \
 523  "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
 524  "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
 525  "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
 526 #else
 527 #define PCIE_ENV ""
 528 #endif
 529
 530 #if defined(CONFIG_PCI1)
 531 #define PCI_ENV \
 532  "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
 533         "echo e;md ${a}e00 9\0"                 \
 534  "pci1regs=setenv a e0008; run pcireg\0"        \
 535  "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
 536         "pci d.w $b.0 56 1\0"                   \
 537  "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
 538         "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"          \
 539  "pci1err=setenv a e0008; setenv b 7; run pcierr\0"             \
 540  "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
 541 #else
 542 #define PCI_ENV ""
 543 #endif
 544
 545 #if defined(CONFIG_TSEC_ENET)
 546 #define ENET_ENV \
 547  "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
 548         "md ${a}098 2\0" \
 549  "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
 550  "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
 551  "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
 552         "echo mib;md ${a}680 31\0" \
 553  "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
 554  "enet1regs=setenv a e0024; run enetreg\0" \
 555  "enet3regs=setenv a e0026; run enetreg\0"
 556 #else
 557 #define ENET_ENV ""
 558 #endif
 559
 560 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 561  "netdev=eth0\0"                                                \
 562  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 563  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 564         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 565         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 566         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 567         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 568         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 569  "consoledev=ttyS0\0"                           \
 570  "ramdiskaddr=2000000\0"                        \
 571  "ramdiskfile=8544ds/ramdisk.uboot\0"           \
 572  "dtbaddr=c00000\0"                             \
 573  "dtbfile=8544ds/mpc8544ds.dtb\0"               \
 574  "bdev=sda3\0"                                  \
 575  "eoi=mw e00400b0 0\0"                          \
 576  "iack=md e00400a0 1\0"                         \
 577  "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
 578         "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
 579  "ddrregs=setenv a e0002; run ddrreg\0"         \
 580  "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
 581         "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0"   \
 582  "guregs=setenv a e00e0; run gureg\0"           \
 583  "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
 584  "ecmregs=setenv a e0001; run ecmreg\0"         \
 585  "lawregs=md e0000c08 4b\0" \
 586  "lbcregs=md e0005000 36\0" \
 587  "dma0regs=md e0021100 12\0" \
 588  "dma1regs=md e0021180 12\0" \
 589  "dma2regs=md e0021200 12\0" \
 590  "dma3regs=md e0021280 12\0" \
 591  PCIE_ENV       \
 592  PCI_ENV        \
 593  ENET_ENV
 594
 595
 596 #define CONFIG_NFSBOOTCOMMAND           \
 597  "setenv bootargs root=/dev/nfs rw "    \
 598  "nfsroot=$serverip:$rootpath "         \
 599  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 600  "console=$consoledev,$baudrate $othbootargs;"  \
 601  "tftp $loadaddr $bootfile;"            \
 602  "tftp $dtbaddr $dtbfile;"              \
 603  "bootm $loadaddr - $dtbaddr"
 604
 605
 606 #define CONFIG_RAMBOOTCOMMAND           \
 607  "setenv bootargs root=/dev/ram rw "    \
 608  "console=$consoledev,$baudrate $othbootargs;"  \
 609  "tftp $ramdiskaddr $ramdiskfile;"      \
 610  "tftp $loadaddr $bootfile;"            \
 611  "tftp $dtbaddr $dtbfile;"              \
 612  "bootm $loadaddr $ramdiskaddr $dtbaddr"
 613
 614 #define CONFIG_BOOTCOMMAND              \
 615  "setenv bootargs root=/dev/$bdev rw "  \
 616  "console=$consoledev,$baudrate $othbootargs;"  \
 617  "tftp $loadaddr $bootfile;"            \
 618  "tftp $dtbaddr $dtbfile;"              \
 619  "bootm $loadaddr - $dtbaddr"
 620
 621 #endif  /* __CONFIG_H */