include/configs/MPC8548CDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * mpc8548cds board configuration file
   9  *
  10  * Please refer to doc/README.mpc85xxcds for more info.
  11  *
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #define CONFIG_SYS_SRIO
  17 #define CONFIG_SRIO1                    /* SRIO port 1 */
  18
  19 #define CONFIG_PCI1             /* PCI controller 1 */
  20 #define CONFIG_PCIE1            /* PCIE controller 1 (slot 1) */
  21 #undef CONFIG_PCI2
  22 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  23
  24 #define CONFIG_ENV_OVERWRITE
  25 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  26
  27 #define CONFIG_FSL_VIA
  28
  29 #ifndef __ASSEMBLY__
  30 extern unsigned long get_clock_freq(void);
  31 #endif
  32 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  33
  34 /*
  35  * These can be toggled for performance analysis, otherwise use default.
  36  */
  37 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  38 #define CONFIG_BTB                      /* toggle branch predition */
  39
  40 /*
  41  * Only possible on E500 Version 2 or newer cores.
  42  */
  43 #define CONFIG_ENABLE_36BIT_PHYS        1
  44
  45 #ifdef CONFIG_PHYS_64BIT
  46 #define CONFIG_ADDR_MAP
  47 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  48 #endif
  49
  50 #define CONFIG_SYS_CCSRBAR              0xe0000000
  51 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  52
  53 /* DDR Setup */
  54 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  55 #define CONFIG_DDR_SPD
  56
  57 #define CONFIG_DDR_ECC
  58 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  59 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  60
  61 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  62 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  63
  64 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  65 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  66
  67 /* I2C addresses of SPD EEPROMs */
  68 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  69
  70 /* Make sure required options are set */
  71 #ifndef CONFIG_SPD_EEPROM
  72 #error ("CONFIG_SPD_EEPROM is required")
  73 #endif
  74
  75 #undef CONFIG_CLOCKS_IN_MHZ
  76 /*
  77  * Physical Address Map
  78  *
  79  * 32bit:
  80  * 0x0000_0000  0x7fff_ffff     DDR                     2G      cacheable
  81  * 0x8000_0000  0x9fff_ffff     PCI1 MEM                512M    cacheable
  82  * 0xa000_0000  0xbfff_ffff     PCIe MEM                512M    cacheable
  83  * 0xc000_0000  0xdfff_ffff     RapidIO                 512M    cacheable
  84  * 0xe000_0000  0xe00f_ffff     CCSR                    1M      non-cacheable
  85  * 0xe200_0000  0xe20f_ffff     PCI1 IO                 1M      non-cacheable
  86  * 0xe300_0000  0xe30f_ffff     PCIe IO                 1M      non-cacheable
  87  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M     cacheable
  88  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS            1M      non-cacheable
  89  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M      non-cacheable
  90  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M      non-cacheable
  91  *
  92  * 36bit:
  93  * 0x00000_0000 0x07fff_ffff    DDR                     2G      cacheable
  94  * 0xc0000_0000 0xc1fff_ffff    PCI1 MEM                512M    cacheable
  95  * 0xc2000_0000 0xc3fff_ffff    PCIe MEM                512M    cacheable
  96  * 0xc4000_0000 0xc5fff_ffff    RapidIO                 512M    cacheable
  97  * 0xfe000_0000 0xfe00f_ffff    CCSR                    1M      non-cacheable
  98  * 0xfe200_0000 0xfe20f_ffff    PCI1 IO                 1M      non-cacheable
  99  * 0xfe300_0000 0xfe30f_ffff    PCIe IO                 1M      non-cacheable
 100  * 0xff000_0000 0xff3ff_ffff    SDRAM                   64M     cacheable
 101  * 0xff800_0000 0xff80f_ffff    NVRAM/CADMUS            1M      non-cacheable
 102  * 0xfff00_0000 0xfff7f_ffff    FLASH (2nd bank)        8M      non-cacheable
 103  * 0xfff80_0000 0xfffff_ffff    FLASH (boot bank)       8M      non-cacheable
 104  *
 105  */
 106
 107 /*
 108  * Local Bus Definitions
 109  */
 110
 111 /*
 112  * FLASH on the Local Bus
 113  * Two banks, 8M each, using the CFI driver.
 114  * Boot from BR0/OR0 bank at 0xff00_0000
 115  * Alternate BR1/OR1 bank at 0xff80_0000
 116  *
 117  * BR0, BR1:
 118  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 119  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 120  *    Port Size = 16 bits = BRx[19:20] = 10
 121  *    Use GPCM = BRx[24:26] = 000
 122  *    Valid = BRx[31] = 1
 123  *
 124  * 0    4    8    12   16   20   24   28
 125  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 126  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 127  *
 128  * OR0, OR1:
 129  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 130  *    Reserved ORx[17:18] = 11, confusion here?
 131  *    CSNT = ORx[20] = 1
 132  *    ACS = half cycle delay = ORx[21:22] = 11
 133  *    SCY = 6 = ORx[24:27] = 0110
 134  *    TRLX = use relaxed timing = ORx[29] = 1
 135  *    EAD = use external address latch delay = OR[31] = 1
 136  *
 137  * 0    4    8    12   16   20   24   28
 138  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 139  */
 140
 141 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 142 #ifdef CONFIG_PHYS_64BIT
 143 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfff000000ull
 144 #else
 145 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 146 #endif
 147
 148 #define CONFIG_SYS_BR0_PRELIM \
 149         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
 150 #define CONFIG_SYS_BR1_PRELIM \
 151         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 152
 153 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 154 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 155
 156 #define CONFIG_SYS_FLASH_BANKS_LIST \
 157         {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
 158 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 159 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 160 #undef  CONFIG_SYS_FLASH_CHECKSUM
 161 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 162 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 163
 164 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 165
 166 #define CONFIG_SYS_FLASH_EMPTY_INFO
 167
 168 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 169
 170 /*
 171  * SDRAM on the Local Bus
 172  */
 173 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 174 #ifdef CONFIG_PHYS_64BIT
 175 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS  0xff0000000ull
 176 #else
 177 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS  CONFIG_SYS_LBC_SDRAM_BASE
 178 #endif
 179 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 180
 181 /*
 182  * Base Register 2 and Option Register 2 configure SDRAM.
 183  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 184  *
 185  * For BR2, need:
 186  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 187  *    port-size = 32-bits = BR2[19:20] = 11
 188  *    no parity checking = BR2[21:22] = 00
 189  *    SDRAM for MSEL = BR2[24:26] = 011
 190  *    Valid = BR[31] = 1
 191  *
 192  * 0    4    8    12   16   20   24   28
 193  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 194  *
 195  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 196  * FIXME: the top 17 bits of BR2.
 197  */
 198
 199 #define CONFIG_SYS_BR2_PRELIM \
 200         (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
 201         | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
 202
 203 /*
 204  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 205  *
 206  * For OR2, need:
 207  *    64MB mask for AM, OR2[0:7] = 1111 1100
 208  *                 XAM, OR2[17:18] = 11
 209  *    9 columns OR2[19-21] = 010
 210  *    13 rows   OR2[23-25] = 100
 211  *    EAD set for extra time OR[31] = 1
 212  *
 213  * 0    4    8    12   16   20   24   28
 214  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 215  */
 216
 217 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 218
 219 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* LB clock ratio reg */
 220 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg */
 221 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 222 #define CONFIG_SYS_LBC_MRTPR            0x00000000      /* LB refresh timer prescal*/
 223
 224 /*
 225  * Common settings for all Local Bus SDRAM commands.
 226  * At run time, either BSMA1516 (for CPU 1.1)
 227  *                  or BSMA1617 (for CPU 1.0) (old)
 228  * is OR'ed in too.
 229  */
 230 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 231                                 | LSDMR_PRETOACT7       \
 232                                 | LSDMR_ACTTORW7        \
 233                                 | LSDMR_BL8             \
 234                                 | LSDMR_WRC4            \
 235                                 | LSDMR_CL3             \
 236                                 | LSDMR_RFEN            \
 237                                 )
 238
 239 /*
 240  * The CADMUS registers are connected to CS3 on CDS.
 241  * The new memory map places CADMUS at 0xf8000000.
 242  *
 243  * For BR3, need:
 244  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 245  *    port-size = 8-bits  = BR[19:20] = 01
 246  *    no parity checking  = BR[21:22] = 00
 247  *    GPMC for MSEL       = BR[24:26] = 000
 248  *    Valid               = BR[31]    = 1
 249  *
 250  * 0    4    8    12   16   20   24   28
 251  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 252  *
 253  * For OR3, need:
 254  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 255  *    disable buffer ctrl OR[19]    = 0
 256  *    CSNT                OR[20]    = 1
 257  *    ACS                 OR[21:22] = 11
 258  *    XACS                OR[23]    = 1
 259  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 260  *    SETA                OR[28]    = 0
 261  *    TRLX                OR[29]    = 1
 262  *    EHTR                OR[30]    = 1
 263  *    EAD extra time      OR[31]    = 1
 264  *
 265  * 0    4    8    12   16   20   24   28
 266  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 267  */
 268
 269 #define CONFIG_FSL_CADMUS
 270
 271 #define CADMUS_BASE_ADDR 0xf8000000
 272 #ifdef CONFIG_PHYS_64BIT
 273 #define CADMUS_BASE_ADDR_PHYS   0xff8000000ull
 274 #else
 275 #define CADMUS_BASE_ADDR_PHYS   CADMUS_BASE_ADDR
 276 #endif
 277 #define CONFIG_SYS_BR3_PRELIM \
 278         (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
 279 #define CONFIG_SYS_OR3_PRELIM    0xfff00ff7
 280
 281 #define CONFIG_SYS_INIT_RAM_LOCK        1
 282 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 283 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 284
 285 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 286 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 287
 288 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 289 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)   /* Reserved for malloc */
 290
 291 /* Serial Port */
 292 #define CONFIG_SYS_NS16550_SERIAL
 293 #define CONFIG_SYS_NS16550_REG_SIZE     1
 294 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 295
 296 #define CONFIG_SYS_BAUDRATE_TABLE \
 297         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 298
 299 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 300 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 301
 302 /*
 303  * I2C
 304  */
 305 #ifndef CONFIG_DM_I2C
 306 #define CONFIG_SYS_I2C
 307 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 308 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 309 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 310 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 311 #else
 312 #define CONFIG_SYS_SPD_BUS_NUM 0
 313 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 314 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 315 #endif
 316 #define CONFIG_SYS_I2C_FSL
 317
 318 /* EEPROM */
 319 #define CONFIG_ID_EEPROM
 320 #define CONFIG_SYS_I2C_EEPROM_CCID
 321 #define CONFIG_SYS_ID_EEPROM
 322 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 323 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 324
 325 /*
 326  * General PCI
 327  * Memory space is mapped 1-1, but I/O space must start from 0.
 328  */
 329 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 330 #ifdef CONFIG_PHYS_64BIT
 331 #define CONFIG_SYS_PCI1_MEM_BUS         0xe0000000
 332 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc00000000ull
 333 #else
 334 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 335 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 336 #endif
 337 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 338 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 339 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 340 #ifdef CONFIG_PHYS_64BIT
 341 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
 342 #else
 343 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 344 #endif
 345 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 346
 347 #ifdef CONFIG_PCIE1
 348 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 349 #ifdef CONFIG_PHYS_64BIT
 350 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc20000000ull
 351 #else
 352 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 353 #endif
 354 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe3000000
 355 #ifdef CONFIG_PHYS_64BIT
 356 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
 357 #else
 358 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 359 #endif
 360 #endif
 361
 362 /*
 363  * RapidIO MMU
 364  */
 365 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xc0000000
 366 #ifdef CONFIG_PHYS_64BIT
 367 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc40000000ull
 368 #else
 369 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc0000000
 370 #endif
 371 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 372
 373 #ifdef CONFIG_LEGACY
 374 #define BRIDGE_ID 17
 375 #define VIA_ID 2
 376 #else
 377 #define BRIDGE_ID 28
 378 #define VIA_ID 4
 379 #endif
 380
 381 #if defined(CONFIG_PCI)
 382 #undef CONFIG_EEPRO100
 383 #undef CONFIG_TULIP
 384
 385 #if !defined(CONFIG_DM_PCI)
 386 #define CONFIG_FSL_PCI_INIT             1       /* Use common FSL init code */
 387 #define CONFIG_PCI_INDIRECT_BRIDGE      1
 388 #define CONFIG_SYS_PCIE1_NAME           "Slot"
 389 #ifdef CONFIG_PHYS_64BIT
 390 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 391 #else
 392 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 393 #endif
 394 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 395 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 396 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /*   1M */
 397 #endif
 398
 399 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 400
 401 #endif  /* CONFIG_PCI */
 402
 403 #if defined(CONFIG_TSEC_ENET)
 404
 405 #define CONFIG_TSEC1    1
 406 #define CONFIG_TSEC1_NAME       "eTSEC0"
 407 #define CONFIG_TSEC2    1
 408 #define CONFIG_TSEC2_NAME       "eTSEC1"
 409 #define CONFIG_TSEC3    1
 410 #define CONFIG_TSEC3_NAME       "eTSEC2"
 411 #define CONFIG_TSEC4
 412 #define CONFIG_TSEC4_NAME       "eTSEC3"
 413 #undef CONFIG_MPC85XX_FEC
 414
 415 #define TSEC1_PHY_ADDR          0
 416 #define TSEC2_PHY_ADDR          1
 417 #define TSEC3_PHY_ADDR          2
 418 #define TSEC4_PHY_ADDR          3
 419
 420 #define TSEC1_PHYIDX            0
 421 #define TSEC2_PHYIDX            0
 422 #define TSEC3_PHYIDX            0
 423 #define TSEC4_PHYIDX            0
 424 #define TSEC1_FLAGS             TSEC_GIGABIT
 425 #define TSEC2_FLAGS             TSEC_GIGABIT
 426 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 427 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 428
 429 /* Options are: eTSEC[0-3] */
 430 #define CONFIG_ETHPRIME         "eTSEC0"
 431 #endif  /* CONFIG_TSEC_ENET */
 432
 433 /*
 434  * Environment
 435  */
 436
 437 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 438 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 439
 440 /*
 441  * BOOTP options
 442  */
 443 #define CONFIG_BOOTP_BOOTFILESIZE
 444
 445 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 446
 447 /*
 448  * Miscellaneous configurable options
 449  */
 450 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 451
 452 /*
 453  * For booting Linux, the board info and command line data
 454  * have to be in the first 64 MB of memory, since this is
 455  * the maximum mapped by the Linux kernel during initialization.
 456  */
 457 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 458 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 459
 460 #if defined(CONFIG_CMD_KGDB)
 461 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 462 #endif
 463
 464 /*
 465  * Environment Configuration
 466  */
 467 #if defined(CONFIG_TSEC_ENET)
 468 #define CONFIG_HAS_ETH0
 469 #define CONFIG_HAS_ETH1
 470 #define CONFIG_HAS_ETH2
 471 #define CONFIG_HAS_ETH3
 472 #endif
 473
 474 #define CONFIG_IPADDR    192.168.1.253
 475
 476 #define CONFIG_HOSTNAME  "unknown"
 477 #define CONFIG_ROOTPATH  "/nfsroot"
 478 #define CONFIG_BOOTFILE "8548cds/uImage.uboot"
 479 #define CONFIG_UBOOTPATH        8548cds/u-boot.bin      /* TFTP server */
 480
 481 #define CONFIG_SERVERIP  192.168.1.1
 482 #define CONFIG_GATEWAYIP 192.168.1.1
 483 #define CONFIG_NETMASK   255.255.255.0
 484
 485 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 486
 487 #define CONFIG_EXTRA_ENV_SETTINGS               \
 488         "hwconfig=fsl_ddr:ecc=off\0"            \
 489         "netdev=eth0\0"                         \
 490         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 491         "tftpflash=tftpboot $loadaddr $uboot; " \
 492                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 493                         " +$filesize; " \
 494                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 495                         " +$filesize; " \
 496                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 497                         " $filesize; "  \
 498                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 499                         " +$filesize; " \
 500                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 501                         " $filesize\0"  \
 502         "consoledev=ttyS1\0"                    \
 503         "ramdiskaddr=2000000\0"                 \
 504         "ramdiskfile=ramdisk.uboot\0"           \
 505         "fdtaddr=1e00000\0"                     \
 506         "fdtfile=mpc8548cds.dtb\0"
 507
 508 #define CONFIG_NFSBOOTCOMMAND                                           \
 509    "setenv bootargs root=/dev/nfs rw "                                  \
 510       "nfsroot=$serverip:$rootpath "                                    \
 511       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 512       "console=$consoledev,$baudrate $othbootargs;"                     \
 513    "tftp $loadaddr $bootfile;"                                          \
 514    "tftp $fdtaddr $fdtfile;"                                            \
 515    "bootm $loadaddr - $fdtaddr"
 516
 517 #define CONFIG_RAMBOOTCOMMAND \
 518    "setenv bootargs root=/dev/ram rw "                                  \
 519       "console=$consoledev,$baudrate $othbootargs;"                     \
 520    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 521    "tftp $loadaddr $bootfile;"                                          \
 522    "tftp $fdtaddr $fdtfile;"                                            \
 523    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 524
 525 #define CONFIG_BOOTCOMMAND      CONFIG_NFSBOOTCOMMAND
 526
 527 #endif  /* __CONFIG_H */