include/configs/MPC8548CDS.h

   1 /*
   2  * Copyright 2004, 2007 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8548cds board configuration file
  25  *
  26  * Please refer to doc/README.mpc85xxcds for more info.
  27  *
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1       /* BOOKE */
  34 #define CONFIG_E500             1       /* BOOKE e500 family */
  35 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  36 #define CONFIG_MPC8548          1       /* MPC8548 specific */
  37 #define CONFIG_MPC8548CDS       1       /* MPC8548CDS board specific */
  38
  39 #define CONFIG_PCI              /* enable any pci type devices */
  40 #define CONFIG_PCI1             /* PCI controller 1 */
  41 #define CONFIG_PCIE1            /* PCIE controler 1 (slot 1) */
  42 #undef CONFIG_RIO
  43 #undef CONFIG_PCI2
  44 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  45 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  46 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  47
  48 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  49 #define CONFIG_ENV_OVERWRITE
  50 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  51 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  52
  53 #define CONFIG_FSL_VIA
  54
  55 /*
  56  * When initializing flash, if we cannot find the manufacturer ID,
  57  * assume this is the AMD flash associated with the CDS board.
  58  * This allows booting from a promjet.
  59  */
  60 #define CONFIG_ASSUME_AMD_FLASH
  61
  62 #ifndef __ASSEMBLY__
  63 extern unsigned long get_clock_freq(void);
  64 #endif
  65 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  66
  67 /*
  68  * These can be toggled for performance analysis, otherwise use default.
  69  */
  70 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  71 #define CONFIG_BTB                      /* toggle branch predition */
  72 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  73 #define CONFIG_CLEAR_LAW0               /* Clear LAW0 in cpu_init_r */
  74
  75 /*
  76  * Only possible on E500 Version 2 or newer cores.
  77  */
  78 #define CONFIG_ENABLE_36BIT_PHYS        1
  79
  80 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  81 #define CONFIG_SYS_MEMTEST_END          0x00400000
  82
  83 /*
  84  * Base addresses -- Note these are effective addresses where the
  85  * actual resources get mapped (not physical addresses)
  86  */
  87 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  88 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  89 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  90 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  91
  92 #define CONFIG_SYS_PCI1_ADDR    (CONFIG_SYS_CCSRBAR+0x8000)
  93 #define CONFIG_SYS_PCI2_ADDR    (CONFIG_SYS_CCSRBAR+0x9000)
  94 #define CONFIG_SYS_PCIE1_ADDR   (CONFIG_SYS_CCSRBAR+0xa000)
  95
  96 /* DDR Setup */
  97 #define CONFIG_FSL_DDR2
  98 #undef CONFIG_FSL_DDR_INTERACTIVE
  99 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
 100 #define CONFIG_DDR_SPD
 101 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
 102
 103 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER        /* DDR controller or DMA? */
 104 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 105
 106 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 107 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 108
 109 #define CONFIG_NUM_DDR_CONTROLLERS      1
 110 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 111 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 112
 113 /* I2C addresses of SPD EEPROMs */
 114 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 115
 116 /* Make sure required options are set */
 117 #ifndef CONFIG_SPD_EEPROM
 118 #error ("CONFIG_SPD_EEPROM is required")
 119 #endif
 120
 121 #undef CONFIG_CLOCKS_IN_MHZ
 122
 123 /*
 124  * Local Bus Definitions
 125  */
 126
 127 /*
 128  * FLASH on the Local Bus
 129  * Two banks, 8M each, using the CFI driver.
 130  * Boot from BR0/OR0 bank at 0xff00_0000
 131  * Alternate BR1/OR1 bank at 0xff80_0000
 132  *
 133  * BR0, BR1:
 134  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 135  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 136  *    Port Size = 16 bits = BRx[19:20] = 10
 137  *    Use GPCM = BRx[24:26] = 000
 138  *    Valid = BRx[31] = 1
 139  *
 140  * 0    4    8    12   16   20   24   28
 141  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 142  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 143  *
 144  * OR0, OR1:
 145  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 146  *    Reserved ORx[17:18] = 11, confusion here?
 147  *    CSNT = ORx[20] = 1
 148  *    ACS = half cycle delay = ORx[21:22] = 11
 149  *    SCY = 6 = ORx[24:27] = 0110
 150  *    TRLX = use relaxed timing = ORx[29] = 1
 151  *    EAD = use external address latch delay = OR[31] = 1
 152  *
 153  * 0    4    8    12   16   20   24   28
 154  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 155  */
 156
 157 #define CONFIG_SYS_BOOT_BLOCK           0xff000000      /* boot TLB block */
 158 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_BOOT_BLOCK   /* start of FLASH 16M */
 159
 160 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 161 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 162
 163 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 164 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 165
 166 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 167 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 168 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 169 #undef  CONFIG_SYS_FLASH_CHECKSUM
 170 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 171 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 172
 173 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 174
 175 #define CONFIG_FLASH_CFI_DRIVER
 176 #define CONFIG_SYS_FLASH_CFI
 177 #define CONFIG_SYS_FLASH_EMPTY_INFO
 178
 179
 180 /*
 181  * SDRAM on the Local Bus
 182  */
 183 #define CONFIG_SYS_LBC_CACHE_BASE       0xf0000000      /* Localbus cacheable */
 184 #define CONFIG_SYS_LBC_CACHE_SIZE       64
 185 #define CONFIG_SYS_LBC_NONCACHE_BASE    0xf8000000      /* Localbus non-cacheable */
 186 #define CONFIG_SYS_LBC_NONCACHE_SIZE    64
 187
 188 #define CONFIG_SYS_LBC_SDRAM_BASE       CONFIG_SYS_LBC_CACHE_BASE       /* Localbus SDRAM */
 189 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 190
 191 /*
 192  * Base Register 2 and Option Register 2 configure SDRAM.
 193  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 194  *
 195  * For BR2, need:
 196  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 197  *    port-size = 32-bits = BR2[19:20] = 11
 198  *    no parity checking = BR2[21:22] = 00
 199  *    SDRAM for MSEL = BR2[24:26] = 011
 200  *    Valid = BR[31] = 1
 201  *
 202  * 0    4    8    12   16   20   24   28
 203  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 204  *
 205  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 206  * FIXME: the top 17 bits of BR2.
 207  */
 208
 209 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 210
 211 /*
 212  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 213  *
 214  * For OR2, need:
 215  *    64MB mask for AM, OR2[0:7] = 1111 1100
 216  *                 XAM, OR2[17:18] = 11
 217  *    9 columns OR2[19-21] = 010
 218  *    13 rows   OR2[23-25] = 100
 219  *    EAD set for extra time OR[31] = 1
 220  *
 221  * 0    4    8    12   16   20   24   28
 222  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 223  */
 224
 225 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 226
 227 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* LB clock ratio reg */
 228 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg */
 229 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 230 #define CONFIG_SYS_LBC_MRTPR            0x00000000      /* LB refresh timer prescal*/
 231
 232 /*
 233  * LSDMR masks
 234  */
 235 #define CONFIG_SYS_LBC_LSDMR_RFEN       (1 << (31 -  1))
 236 #define CONFIG_SYS_LBC_LSDMR_BSMA1516   (3 << (31 - 10))
 237 #define CONFIG_SYS_LBC_LSDMR_BSMA1617   (4 << (31 - 10))
 238 #define CONFIG_SYS_LBC_LSDMR_RFCR16     (7 << (31 - 16))
 239 #define CONFIG_SYS_LBC_LSDMR_PRETOACT7  (7 << (31 - 19))
 240 #define CONFIG_SYS_LBC_LSDMR_ACTTORW7   (7 << (31 - 22))
 241 #define CONFIG_SYS_LBC_LSDMR_ACTTORW6   (6 << (31 - 22))
 242 #define CONFIG_SYS_LBC_LSDMR_BL8        (1 << (31 - 23))
 243 #define CONFIG_SYS_LBC_LSDMR_WRC4       (0 << (31 - 27))
 244 #define CONFIG_SYS_LBC_LSDMR_CL3        (3 << (31 - 31))
 245
 246 #define CONFIG_SYS_LBC_LSDMR_OP_NORMAL  (0 << (31 - 4))
 247 #define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH  (1 << (31 - 4))
 248 #define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH  (2 << (31 - 4))
 249 #define CONFIG_SYS_LBC_LSDMR_OP_MRW     (3 << (31 - 4))
 250 #define CONFIG_SYS_LBC_LSDMR_OP_PRECH   (4 << (31 - 4))
 251 #define CONFIG_SYS_LBC_LSDMR_OP_PCHALL  (5 << (31 - 4))
 252 #define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK  (6 << (31 - 4))
 253 #define CONFIG_SYS_LBC_LSDMR_OP_RWINV   (7 << (31 - 4))
 254
 255 /*
 256  * Common settings for all Local Bus SDRAM commands.
 257  * At run time, either BSMA1516 (for CPU 1.1)
 258  *                  or BSMA1617 (for CPU 1.0) (old)
 259  * is OR'ed in too.
 260  */
 261 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( CONFIG_SYS_LBC_LSDMR_RFCR16           \
 262                                 | CONFIG_SYS_LBC_LSDMR_PRETOACT7        \
 263                                 | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \
 264                                 | CONFIG_SYS_LBC_LSDMR_BL8              \
 265                                 | CONFIG_SYS_LBC_LSDMR_WRC4             \
 266                                 | CONFIG_SYS_LBC_LSDMR_CL3              \
 267                                 | CONFIG_SYS_LBC_LSDMR_RFEN             \
 268                                 )
 269
 270 /*
 271  * The CADMUS registers are connected to CS3 on CDS.
 272  * The new memory map places CADMUS at 0xf8000000.
 273  *
 274  * For BR3, need:
 275  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 276  *    port-size = 8-bits  = BR[19:20] = 01
 277  *    no parity checking  = BR[21:22] = 00
 278  *    GPMC for MSEL       = BR[24:26] = 000
 279  *    Valid               = BR[31]    = 1
 280  *
 281  * 0    4    8    12   16   20   24   28
 282  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 283  *
 284  * For OR3, need:
 285  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 286  *    disable buffer ctrl OR[19]    = 0
 287  *    CSNT                OR[20]    = 1
 288  *    ACS                 OR[21:22] = 11
 289  *    XACS                OR[23]    = 1
 290  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 291  *    SETA                OR[28]    = 0
 292  *    TRLX                OR[29]    = 1
 293  *    EHTR                OR[30]    = 1
 294  *    EAD extra time      OR[31]    = 1
 295  *
 296  * 0    4    8    12   16   20   24   28
 297  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 298  */
 299
 300 #define CONFIG_FSL_CADMUS
 301
 302 #define CADMUS_BASE_ADDR 0xf8000000
 303 #define CONFIG_SYS_BR3_PRELIM    0xf8000801
 304 #define CONFIG_SYS_OR3_PRELIM    0xfff00ff7
 305
 306 #define CONFIG_L1_INIT_RAM
 307 #define CONFIG_SYS_INIT_RAM_LOCK        1
 308 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 309 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 310
 311 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000      /* relocate boot L2SRAM */
 312
 313 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 314 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 315 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 316
 317 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 318 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 319
 320 /* Serial Port */
 321 #define CONFIG_CONS_INDEX       2
 322 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 323 #define CONFIG_SYS_NS16550
 324 #define CONFIG_SYS_NS16550_SERIAL
 325 #define CONFIG_SYS_NS16550_REG_SIZE     1
 326 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 327
 328 #define CONFIG_SYS_BAUDRATE_TABLE \
 329         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 330
 331 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 332 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 333
 334 /* Use the HUSH parser */
 335 #define CONFIG_SYS_HUSH_PARSER
 336 #ifdef  CONFIG_SYS_HUSH_PARSER
 337 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 338 #endif
 339
 340 /* pass open firmware flat tree */
 341 #define CONFIG_OF_LIBFDT                1
 342 #define CONFIG_OF_BOARD_SETUP           1
 343 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 344
 345 #define CONFIG_SYS_64BIT_VSPRINTF       1
 346 #define CONFIG_SYS_64BIT_STRTOUL        1
 347
 348 /*
 349  * I2C
 350  */
 351 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 352 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 353 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 354 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 355 #define CONFIG_SYS_I2C_SLAVE            0x7F
 356 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 357 #define CONFIG_SYS_I2C_OFFSET           0x3000
 358
 359 /* EEPROM */
 360 #define CONFIG_ID_EEPROM
 361 #define CONFIG_SYS_I2C_EEPROM_CCID
 362 #define CONFIG_SYS_ID_EEPROM
 363 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 364 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 365
 366 /*
 367  * General PCI
 368  * Memory space is mapped 1-1, but I/O space must start from 0.
 369  */
 370 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
 371
 372 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 373 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 374 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 375 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 376 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 377 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 378
 379 #ifdef CONFIG_PCI2
 380 #define CONFIG_SYS_PCI2_MEM_BASE        0xa0000000
 381 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 382 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 383 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 384 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
 385 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 386 #endif
 387
 388 #ifdef CONFIG_PCIE1
 389 #define CONFIG_SYS_PCIE1_MEM_BASE       0xa0000000
 390 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BASE
 391 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 392 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 393 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 394 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /*   1M */
 395 #endif
 396
 397 #ifdef CONFIG_RIO
 398 /*
 399  * RapidIO MMU
 400  */
 401 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
 402 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M */
 403 #endif
 404
 405 #ifdef CONFIG_LEGACY
 406 #define BRIDGE_ID 17
 407 #define VIA_ID 2
 408 #else
 409 #define BRIDGE_ID 28
 410 #define VIA_ID 4
 411 #endif
 412
 413 #if defined(CONFIG_PCI)
 414
 415 #define CONFIG_NET_MULTI
 416 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 417
 418 #undef CONFIG_EEPRO100
 419 #undef CONFIG_TULIP
 420
 421 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 422
 423 /* PCI view of System Memory */
 424 #define CONFIG_SYS_PCI_MEMORY_BUS       0x00000000
 425 #define CONFIG_SYS_PCI_MEMORY_PHYS      0x00000000
 426 #define CONFIG_SYS_PCI_MEMORY_SIZE      0x80000000
 427
 428 #endif  /* CONFIG_PCI */
 429
 430
 431 #if defined(CONFIG_TSEC_ENET)
 432
 433 #ifndef CONFIG_NET_MULTI
 434 #define CONFIG_NET_MULTI        1
 435 #endif
 436
 437 #define CONFIG_MII              1       /* MII PHY management */
 438 #define CONFIG_TSEC1    1
 439 #define CONFIG_TSEC1_NAME       "eTSEC0"
 440 #define CONFIG_TSEC2    1
 441 #define CONFIG_TSEC2_NAME       "eTSEC1"
 442 #define CONFIG_TSEC3    1
 443 #define CONFIG_TSEC3_NAME       "eTSEC2"
 444 #define CONFIG_TSEC4
 445 #define CONFIG_TSEC4_NAME       "eTSEC3"
 446 #undef CONFIG_MPC85XX_FEC
 447
 448 #define TSEC1_PHY_ADDR          0
 449 #define TSEC2_PHY_ADDR          1
 450 #define TSEC3_PHY_ADDR          2
 451 #define TSEC4_PHY_ADDR          3
 452
 453 #define TSEC1_PHYIDX            0
 454 #define TSEC2_PHYIDX            0
 455 #define TSEC3_PHYIDX            0
 456 #define TSEC4_PHYIDX            0
 457 #define TSEC1_FLAGS             TSEC_GIGABIT
 458 #define TSEC2_FLAGS             TSEC_GIGABIT
 459 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 460 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 461
 462 /* Options are: eTSEC[0-3] */
 463 #define CONFIG_ETHPRIME         "eTSEC0"
 464 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 465 #endif  /* CONFIG_TSEC_ENET */
 466
 467 /*
 468  * Environment
 469  */
 470 #define CONFIG_ENV_IS_IN_FLASH  1
 471 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 472 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 473 #define CONFIG_ENV_SIZE         0x2000
 474
 475 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 476 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 477
 478 /*
 479  * BOOTP options
 480  */
 481 #define CONFIG_BOOTP_BOOTFILESIZE
 482 #define CONFIG_BOOTP_BOOTPATH
 483 #define CONFIG_BOOTP_GATEWAY
 484 #define CONFIG_BOOTP_HOSTNAME
 485
 486
 487 /*
 488  * Command line configuration.
 489  */
 490 #include <config_cmd_default.h>
 491
 492 #define CONFIG_CMD_PING
 493 #define CONFIG_CMD_I2C
 494 #define CONFIG_CMD_MII
 495 #define CONFIG_CMD_ELF
 496 #define CONFIG_CMD_IRQ
 497 #define CONFIG_CMD_SETEXPR
 498
 499 #if defined(CONFIG_PCI)
 500     #define CONFIG_CMD_PCI
 501 #endif
 502
 503
 504 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 505
 506 /*
 507  * Miscellaneous configurable options
 508  */
 509 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 510 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 511 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 512 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 513 #if defined(CONFIG_CMD_KGDB)
 514 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 515 #else
 516 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 517 #endif
 518 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 519 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 520 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 521 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 522
 523 /*
 524  * For booting Linux, the board info and command line data
 525  * have to be in the first 8 MB of memory, since this is
 526  * the maximum mapped by the Linux kernel during initialization.
 527  */
 528 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 529
 530 /*
 531  * Internal Definitions
 532  *
 533  * Boot Flags
 534  */
 535 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 536 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 537
 538 #if defined(CONFIG_CMD_KGDB)
 539 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 540 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 541 #endif
 542
 543 /*
 544  * Environment Configuration
 545  */
 546
 547 /* The mac addresses for all ethernet interface */
 548 #if defined(CONFIG_TSEC_ENET)
 549 #define CONFIG_HAS_ETH0
 550 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 551 #define CONFIG_HAS_ETH1
 552 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 553 #define CONFIG_HAS_ETH2
 554 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 555 #define CONFIG_HAS_ETH3
 556 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 557 #endif
 558
 559 #define CONFIG_IPADDR    192.168.1.253
 560
 561 #define CONFIG_HOSTNAME  unknown
 562 #define CONFIG_ROOTPATH  /nfsroot
 563 #define CONFIG_BOOTFILE 8548cds/uImage.uboot
 564 #define CONFIG_UBOOTPATH        8548cds/u-boot.bin      /* TFTP server */
 565
 566 #define CONFIG_SERVERIP  192.168.1.1
 567 #define CONFIG_GATEWAYIP 192.168.1.1
 568 #define CONFIG_NETMASK   255.255.255.0
 569
 570 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 571
 572 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 573 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 574
 575 #define CONFIG_BAUDRATE 115200
 576
 577 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 578  "netdev=eth0\0"                                                \
 579  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 580  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 581         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 582         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 583         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 584         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 585         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 586  "consoledev=ttyS1\0"                           \
 587  "ramdiskaddr=2000000\0"                        \
 588  "ramdiskfile=ramdisk.uboot\0"                  \
 589  "fdtaddr=c00000\0"                             \
 590  "fdtfile=mpc8548cds.dtb\0"
 591
 592 #define CONFIG_NFSBOOTCOMMAND                                           \
 593    "setenv bootargs root=/dev/nfs rw "                                  \
 594       "nfsroot=$serverip:$rootpath "                                    \
 595       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 596       "console=$consoledev,$baudrate $othbootargs;"                     \
 597    "tftp $loadaddr $bootfile;"                                          \
 598    "tftp $fdtaddr $fdtfile;"                                            \
 599    "bootm $loadaddr - $fdtaddr"
 600
 601
 602 #define CONFIG_RAMBOOTCOMMAND \
 603    "setenv bootargs root=/dev/ram rw "                                  \
 604       "console=$consoledev,$baudrate $othbootargs;"                     \
 605    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 606    "tftp $loadaddr $bootfile;"                                          \
 607    "tftp $fdtaddr $fdtfile;"                                            \
 608    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 609
 610 #define CONFIG_BOOTCOMMAND      CONFIG_NFSBOOTCOMMAND
 611
 612 #endif  /* __CONFIG_H */