include/configs/MPC8548CDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * mpc8548cds board configuration file
   9  *
  10  * Please refer to doc/README.mpc85xxcds for more info.
  11  *
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #define CONFIG_SYS_SRIO
  17 #define CONFIG_SRIO1                    /* SRIO port 1 */
  18
  19 #define CONFIG_PCI1             /* PCI controller 1 */
  20 #define CONFIG_PCIE1            /* PCIE controller 1 (slot 1) */
  21 #undef CONFIG_PCI2
  22
  23 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  24
  25 #ifndef __ASSEMBLY__
  26 #include <linux/stringify.h>
  27 #endif
  28
  29 /*
  30  * These can be toggled for performance analysis, otherwise use default.
  31  */
  32 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  33
  34 /*
  35  * Only possible on E500 Version 2 or newer cores.
  36  */
  37 #define CONFIG_ENABLE_36BIT_PHYS        1
  38
  39 #define CONFIG_SYS_CCSRBAR              0xe0000000
  40 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  41
  42 /* DDR Setup */
  43 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  44
  45 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  46
  47 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  48 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  49
  50 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  51
  52 /* I2C addresses of SPD EEPROMs */
  53 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  54
  55 /* Make sure required options are set */
  56 #ifndef CONFIG_SPD_EEPROM
  57 #error ("CONFIG_SPD_EEPROM is required")
  58 #endif
  59
  60 /*
  61  * Physical Address Map
  62  *
  63  * 32bit:
  64  * 0x0000_0000  0x7fff_ffff     DDR                     2G      cacheable
  65  * 0x8000_0000  0x9fff_ffff     PCI1 MEM                512M    cacheable
  66  * 0xa000_0000  0xbfff_ffff     PCIe MEM                512M    cacheable
  67  * 0xc000_0000  0xdfff_ffff     RapidIO                 512M    cacheable
  68  * 0xe000_0000  0xe00f_ffff     CCSR                    1M      non-cacheable
  69  * 0xe200_0000  0xe20f_ffff     PCI1 IO                 1M      non-cacheable
  70  * 0xe300_0000  0xe30f_ffff     PCIe IO                 1M      non-cacheable
  71  * 0xf000_0000  0xf3ff_ffff     SDRAM                   64M     cacheable
  72  * 0xf800_0000  0xf80f_ffff     NVRAM/CADMUS            1M      non-cacheable
  73  * 0xff00_0000  0xff7f_ffff     FLASH (2nd bank)        8M      non-cacheable
  74  * 0xff80_0000  0xffff_ffff     FLASH (boot bank)       8M      non-cacheable
  75  *
  76  * 36bit:
  77  * 0x00000_0000 0x07fff_ffff    DDR                     2G      cacheable
  78  * 0xc0000_0000 0xc1fff_ffff    PCI1 MEM                512M    cacheable
  79  * 0xc2000_0000 0xc3fff_ffff    PCIe MEM                512M    cacheable
  80  * 0xc4000_0000 0xc5fff_ffff    RapidIO                 512M    cacheable
  81  * 0xfe000_0000 0xfe00f_ffff    CCSR                    1M      non-cacheable
  82  * 0xfe200_0000 0xfe20f_ffff    PCI1 IO                 1M      non-cacheable
  83  * 0xfe300_0000 0xfe30f_ffff    PCIe IO                 1M      non-cacheable
  84  * 0xff000_0000 0xff3ff_ffff    SDRAM                   64M     cacheable
  85  * 0xff800_0000 0xff80f_ffff    NVRAM/CADMUS            1M      non-cacheable
  86  * 0xfff00_0000 0xfff7f_ffff    FLASH (2nd bank)        8M      non-cacheable
  87  * 0xfff80_0000 0xfffff_ffff    FLASH (boot bank)       8M      non-cacheable
  88  *
  89  */
  90
  91 /*
  92  * Local Bus Definitions
  93  */
  94
  95 /*
  96  * FLASH on the Local Bus
  97  * Two banks, 8M each, using the CFI driver.
  98  * Boot from BR0/OR0 bank at 0xff00_0000
  99  * Alternate BR1/OR1 bank at 0xff80_0000
 100  *
 101  * BR0, BR1:
 102  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 103  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 104  *    Port Size = 16 bits = BRx[19:20] = 10
 105  *    Use GPCM = BRx[24:26] = 000
 106  *    Valid = BRx[31] = 1
 107  *
 108  * 0    4    8    12   16   20   24   28
 109  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 110  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 111  *
 112  * OR0, OR1:
 113  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 114  *    Reserved ORx[17:18] = 11, confusion here?
 115  *    CSNT = ORx[20] = 1
 116  *    ACS = half cycle delay = ORx[21:22] = 11
 117  *    SCY = 6 = ORx[24:27] = 0110
 118  *    TRLX = use relaxed timing = ORx[29] = 1
 119  *    EAD = use external address latch delay = OR[31] = 1
 120  *
 121  * 0    4    8    12   16   20   24   28
 122  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 123  */
 124
 125 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 126 #ifdef CONFIG_PHYS_64BIT
 127 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfff000000ull
 128 #else
 129 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 130 #endif
 131
 132 #define CONFIG_SYS_FLASH_BANKS_LIST \
 133         {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
 134 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 135 #undef  CONFIG_SYS_FLASH_CHECKSUM
 136 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 137 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 138
 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 140
 141 #define CONFIG_SYS_FLASH_EMPTY_INFO
 142
 143 #define CONFIG_HWCONFIG                 /* enable hwconfig */
 144
 145 /*
 146  * SDRAM on the Local Bus
 147  */
 148 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 149 #ifdef CONFIG_PHYS_64BIT
 150 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS  0xff0000000ull
 151 #else
 152 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS  CONFIG_SYS_LBC_SDRAM_BASE
 153 #endif
 154 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 155
 156 /*
 157  * Base Register 2 and Option Register 2 configure SDRAM.
 158  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 159  *
 160  * For BR2, need:
 161  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 162  *    port-size = 32-bits = BR2[19:20] = 11
 163  *    no parity checking = BR2[21:22] = 00
 164  *    SDRAM for MSEL = BR2[24:26] = 011
 165  *    Valid = BR[31] = 1
 166  *
 167  * 0    4    8    12   16   20   24   28
 168  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 169  *
 170  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 171  * FIXME: the top 17 bits of BR2.
 172  */
 173
 174 /*
 175  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 176  *
 177  * For OR2, need:
 178  *    64MB mask for AM, OR2[0:7] = 1111 1100
 179  *                 XAM, OR2[17:18] = 11
 180  *    9 columns OR2[19-21] = 010
 181  *    13 rows   OR2[23-25] = 100
 182  *    EAD set for extra time OR[31] = 1
 183  *
 184  * 0    4    8    12   16   20   24   28
 185  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 186  */
 187
 188 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* LB clock ratio reg */
 189 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg */
 190 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 191 #define CONFIG_SYS_LBC_MRTPR            0x00000000      /* LB refresh timer prescal*/
 192
 193 /*
 194  * Common settings for all Local Bus SDRAM commands.
 195  * At run time, either BSMA1516 (for CPU 1.1)
 196  *                  or BSMA1617 (for CPU 1.0) (old)
 197  * is OR'ed in too.
 198  */
 199 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 200                                 | LSDMR_PRETOACT7       \
 201                                 | LSDMR_ACTTORW7        \
 202                                 | LSDMR_BL8             \
 203                                 | LSDMR_WRC4            \
 204                                 | LSDMR_CL3             \
 205                                 | LSDMR_RFEN            \
 206                                 )
 207
 208 /*
 209  * The CADMUS registers are connected to CS3 on CDS.
 210  * The new memory map places CADMUS at 0xf8000000.
 211  *
 212  * For BR3, need:
 213  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 214  *    port-size = 8-bits  = BR[19:20] = 01
 215  *    no parity checking  = BR[21:22] = 00
 216  *    GPMC for MSEL       = BR[24:26] = 000
 217  *    Valid               = BR[31]    = 1
 218  *
 219  * 0    4    8    12   16   20   24   28
 220  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 221  *
 222  * For OR3, need:
 223  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 224  *    disable buffer ctrl OR[19]    = 0
 225  *    CSNT                OR[20]    = 1
 226  *    ACS                 OR[21:22] = 11
 227  *    XACS                OR[23]    = 1
 228  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 229  *    SETA                OR[28]    = 0
 230  *    TRLX                OR[29]    = 1
 231  *    EHTR                OR[30]    = 1
 232  *    EAD extra time      OR[31]    = 1
 233  *
 234  * 0    4    8    12   16   20   24   28
 235  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 236  */
 237
 238 #define CONFIG_FSL_CADMUS
 239
 240 #define CADMUS_BASE_ADDR 0xf8000000
 241 #ifdef CONFIG_PHYS_64BIT
 242 #define CADMUS_BASE_ADDR_PHYS   0xff8000000ull
 243 #else
 244 #define CADMUS_BASE_ADDR_PHYS   CADMUS_BASE_ADDR
 245 #endif
 246
 247 #define CONFIG_SYS_INIT_RAM_LOCK        1
 248 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 249 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 250
 251 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 252 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 253
 254 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 255
 256 /* Serial Port */
 257 #define CONFIG_SYS_NS16550_SERIAL
 258 #define CONFIG_SYS_NS16550_REG_SIZE     1
 259 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 260
 261 #define CONFIG_SYS_BAUDRATE_TABLE \
 262         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 263
 264 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 265 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 266
 267 /*
 268  * I2C
 269  */
 270 #if !CONFIG_IS_ENABLED(DM_I2C)
 271 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 272 #else
 273 #define CONFIG_SYS_SPD_BUS_NUM 0
 274 #endif
 275
 276 /* EEPROM */
 277 #define CONFIG_SYS_I2C_EEPROM_CCID
 278
 279 /*
 280  * General PCI
 281  * Memory space is mapped 1-1, but I/O space must start from 0.
 282  */
 283 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 284 #ifdef CONFIG_PHYS_64BIT
 285 #define CONFIG_SYS_PCI1_MEM_BUS         0xe0000000
 286 #define CONFIG_SYS_PCI1_MEM_PHYS        0xc00000000ull
 287 #else
 288 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 289 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 290 #endif
 291 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 292 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 293 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 294 #ifdef CONFIG_PHYS_64BIT
 295 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
 296 #else
 297 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 298 #endif
 299 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 300
 301 #ifdef CONFIG_PCIE1
 302 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 303 #ifdef CONFIG_PHYS_64BIT
 304 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc20000000ull
 305 #else
 306 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 307 #endif
 308 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe3000000
 309 #ifdef CONFIG_PHYS_64BIT
 310 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
 311 #else
 312 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 313 #endif
 314 #endif
 315
 316 /*
 317  * RapidIO MMU
 318  */
 319 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xc0000000
 320 #ifdef CONFIG_PHYS_64BIT
 321 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc40000000ull
 322 #else
 323 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc0000000
 324 #endif
 325 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 326
 327 #ifdef CONFIG_LEGACY
 328 #define BRIDGE_ID 17
 329 #define VIA_ID 2
 330 #else
 331 #define BRIDGE_ID 28
 332 #define VIA_ID 4
 333 #endif
 334
 335 #if defined(CONFIG_PCI)
 336 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 337 #endif  /* CONFIG_PCI */
 338
 339 #if defined(CONFIG_TSEC_ENET)
 340
 341 #define CONFIG_TSEC1    1
 342 #define CONFIG_TSEC1_NAME       "eTSEC0"
 343 #define CONFIG_TSEC2    1
 344 #define CONFIG_TSEC2_NAME       "eTSEC1"
 345 #define CONFIG_TSEC3    1
 346 #define CONFIG_TSEC3_NAME       "eTSEC2"
 347 #define CONFIG_TSEC4
 348 #define CONFIG_TSEC4_NAME       "eTSEC3"
 349 #undef CONFIG_MPC85XX_FEC
 350
 351 #define TSEC1_PHY_ADDR          0
 352 #define TSEC2_PHY_ADDR          1
 353 #define TSEC3_PHY_ADDR          2
 354 #define TSEC4_PHY_ADDR          3
 355
 356 #define TSEC1_PHYIDX            0
 357 #define TSEC2_PHYIDX            0
 358 #define TSEC3_PHYIDX            0
 359 #define TSEC4_PHYIDX            0
 360 #define TSEC1_FLAGS             TSEC_GIGABIT
 361 #define TSEC2_FLAGS             TSEC_GIGABIT
 362 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 363 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 364 #endif  /* CONFIG_TSEC_ENET */
 365
 366 /*
 367  * Environment
 368  */
 369
 370 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 371 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 372
 373 /*
 374  * Miscellaneous configurable options
 375  */
 376
 377 /*
 378  * For booting Linux, the board info and command line data
 379  * have to be in the first 64 MB of memory, since this is
 380  * the maximum mapped by the Linux kernel during initialization.
 381  */
 382 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 383 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 384
 385 /*
 386  * Environment Configuration
 387  */
 388
 389 #define CONFIG_IPADDR    192.168.1.253
 390
 391 #define CONFIG_HOSTNAME  "unknown"
 392 #define CONFIG_ROOTPATH  "/nfsroot"
 393 #define CONFIG_UBOOTPATH        8548cds/u-boot.bin      /* TFTP server */
 394
 395 #define CONFIG_SERVERIP  192.168.1.1
 396 #define CONFIG_GATEWAYIP 192.168.1.1
 397 #define CONFIG_NETMASK   255.255.255.0
 398
 399 #define CONFIG_EXTRA_ENV_SETTINGS               \
 400         "hwconfig=fsl_ddr:ecc=off\0"            \
 401         "netdev=eth0\0"                         \
 402         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 403         "tftpflash=tftpboot $loadaddr $uboot; " \
 404                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 405                         " +$filesize; " \
 406                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 407                         " +$filesize; " \
 408                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 409                         " $filesize; "  \
 410                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 411                         " +$filesize; " \
 412                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 413                         " $filesize\0"  \
 414         "consoledev=ttyS1\0"                    \
 415         "ramdiskaddr=2000000\0"                 \
 416         "ramdiskfile=ramdisk.uboot\0"           \
 417         "fdtaddr=1e00000\0"                     \
 418         "fdtfile=mpc8548cds.dtb\0"
 419
 420 #endif  /* __CONFIG_H */