include/configs/MPC8555CDS.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8555cds board configuration file
  25  *
  26  * Please refer to doc/README.mpc85xxcds for more info.
  27  *
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1       /* BOOKE */
  34 #define CONFIG_E500             1       /* BOOKE e500 family */
  35 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41 */
  36 #define CONFIG_CPM2             1       /* has CPM2 */
  37 #define CONFIG_MPC8555          1       /* MPC8555 specific */
  38 #define CONFIG_MPC8555CDS       1       /* MPC8555CDS board specific */
  39
  40 #define CONFIG_PCI
  41 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  42 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  43 #define CONFIG_ENV_OVERWRITE
  44 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  45
  46 #define CONFIG_FSL_VIA
  47
  48
  49 #ifndef __ASSEMBLY__
  50 extern unsigned long get_clock_freq(void);
  51 #endif
  52 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  53
  54 /*
  55  * These can be toggled for performance analysis, otherwise use default.
  56  */
  57 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  58 #define CONFIG_BTB                          /* toggle branch predition */
  59
  60 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  61 #define CONFIG_SYS_MEMTEST_END          0x00400000
  62
  63 /*
  64  * Base addresses -- Note these are effective addresses where the
  65  * actual resources get mapped (not physical addresses)
  66  */
  67 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  68 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  69 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  70 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  71
  72 /* DDR Setup */
  73 #define CONFIG_FSL_DDR1
  74 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  75 #define CONFIG_DDR_SPD
  76 #undef CONFIG_FSL_DDR_INTERACTIVE
  77
  78 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  79
  80 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  81 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  82
  83 #define CONFIG_NUM_DDR_CONTROLLERS      1
  84 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  85 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  86
  87 /* I2C addresses of SPD EEPROMs */
  88 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  89
  90 /* Make sure required options are set */
  91 #ifndef CONFIG_SPD_EEPROM
  92 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  93 #endif
  94
  95 #undef CONFIG_CLOCKS_IN_MHZ
  96
  97 /*
  98  * Local Bus Definitions
  99  */
 100
 101 /*
 102  * FLASH on the Local Bus
 103  * Two banks, 8M each, using the CFI driver.
 104  * Boot from BR0/OR0 bank at 0xff00_0000
 105  * Alternate BR1/OR1 bank at 0xff80_0000
 106  *
 107  * BR0, BR1:
 108  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 109  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 110  *    Port Size = 16 bits = BRx[19:20] = 10
 111  *    Use GPCM = BRx[24:26] = 000
 112  *    Valid = BRx[31] = 1
 113  *
 114  * 0    4    8    12   16   20   24   28
 115  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 116  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 117  *
 118  * OR0, OR1:
 119  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 120  *    Reserved ORx[17:18] = 11, confusion here?
 121  *    CSNT = ORx[20] = 1
 122  *    ACS = half cycle delay = ORx[21:22] = 11
 123  *    SCY = 6 = ORx[24:27] = 0110
 124  *    TRLX = use relaxed timing = ORx[29] = 1
 125  *    EAD = use external address latch delay = OR[31] = 1
 126  *
 127  * 0    4    8    12   16   20   24   28
 128  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 129  */
 130
 131 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 8M */
 132
 133 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 134 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 135
 136 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 137 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 138
 139 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 140 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 141 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 142 #undef  CONFIG_SYS_FLASH_CHECKSUM
 143 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 144 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 145
 146 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 147
 148 #define CONFIG_FLASH_CFI_DRIVER
 149 #define CONFIG_SYS_FLASH_CFI
 150 #define CONFIG_SYS_FLASH_EMPTY_INFO
 151
 152
 153 /*
 154  * SDRAM on the Local Bus
 155  */
 156 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 157 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 158
 159 /*
 160  * Base Register 2 and Option Register 2 configure SDRAM.
 161  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 162  *
 163  * For BR2, need:
 164  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 165  *    port-size = 32-bits = BR2[19:20] = 11
 166  *    no parity checking = BR2[21:22] = 00
 167  *    SDRAM for MSEL = BR2[24:26] = 011
 168  *    Valid = BR[31] = 1
 169  *
 170  * 0    4    8    12   16   20   24   28
 171  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 172  *
 173  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 174  * FIXME: the top 17 bits of BR2.
 175  */
 176
 177 #define CONFIG_SYS_BR2_PRELIM          0xf0001861
 178
 179 /*
 180  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 181  *
 182  * For OR2, need:
 183  *    64MB mask for AM, OR2[0:7] = 1111 1100
 184  *                 XAM, OR2[17:18] = 11
 185  *    9 columns OR2[19-21] = 010
 186  *    13 rows   OR2[23-25] = 100
 187  *    EAD set for extra time OR[31] = 1
 188  *
 189  * 0    4    8    12   16   20   24   28
 190  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 191  */
 192
 193 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 194
 195 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 196 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 197 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 198 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 199
 200 /*
 201  * Common settings for all Local Bus SDRAM commands.
 202  * At run time, either BSMA1516 (for CPU 1.1)
 203  *                  or BSMA1617 (for CPU 1.0) (old)
 204  * is OR'ed in too.
 205  */
 206 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 207                                 | LSDMR_PRETOACT7       \
 208                                 | LSDMR_ACTTORW7        \
 209                                 | LSDMR_BL8             \
 210                                 | LSDMR_WRC4            \
 211                                 | LSDMR_CL3             \
 212                                 | LSDMR_RFEN            \
 213                                 )
 214
 215 /*
 216  * The CADMUS registers are connected to CS3 on CDS.
 217  * The new memory map places CADMUS at 0xf8000000.
 218  *
 219  * For BR3, need:
 220  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 221  *    port-size = 8-bits  = BR[19:20] = 01
 222  *    no parity checking  = BR[21:22] = 00
 223  *    GPMC for MSEL       = BR[24:26] = 000
 224  *    Valid               = BR[31]    = 1
 225  *
 226  * 0    4    8    12   16   20   24   28
 227  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 228  *
 229  * For OR3, need:
 230  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 231  *    disable buffer ctrl OR[19]    = 0
 232  *    CSNT                OR[20]    = 1
 233  *    ACS                 OR[21:22] = 11
 234  *    XACS                OR[23]    = 1
 235  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 236  *    SETA                OR[28]    = 0
 237  *    TRLX                OR[29]    = 1
 238  *    EHTR                OR[30]    = 1
 239  *    EAD extra time      OR[31]    = 1
 240  *
 241  * 0    4    8    12   16   20   24   28
 242  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 243  */
 244
 245 #define CONFIG_FSL_CADMUS
 246
 247 #define CADMUS_BASE_ADDR 0xf8000000
 248 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 249 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 250
 251 #define CONFIG_SYS_INIT_RAM_LOCK        1
 252 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 253 #define CONFIG_SYS_INIT_RAM_END 0x4000      /* End of used area in RAM */
 254
 255 #define CONFIG_SYS_GBL_DATA_SIZE        128         /* num bytes initial data */
 256 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 257 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 258
 259 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 260 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 261
 262 /* Serial Port */
 263 #define CONFIG_CONS_INDEX     2
 264 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 265 #define CONFIG_SYS_NS16550
 266 #define CONFIG_SYS_NS16550_SERIAL
 267 #define CONFIG_SYS_NS16550_REG_SIZE    1
 268 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 269
 270 #define CONFIG_SYS_BAUDRATE_TABLE  \
 271         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 272
 273 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 274 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 275
 276 /* Use the HUSH parser */
 277 #define CONFIG_SYS_HUSH_PARSER
 278 #ifdef  CONFIG_SYS_HUSH_PARSER
 279 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 280 #endif
 281
 282 /* pass open firmware flat tree */
 283 #define CONFIG_OF_LIBFDT                1
 284 #define CONFIG_OF_BOARD_SETUP           1
 285 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 286
 287 /*
 288  * I2C
 289  */
 290 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 291 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 292 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 293 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 294 #define CONFIG_SYS_I2C_SLAVE            0x7F
 295 #define CONFIG_SYS_I2C_NOPROBES        {0x69}   /* Don't probe these addrs */
 296 #define CONFIG_SYS_I2C_OFFSET           0x3000
 297
 298 /* EEPROM */
 299 #define CONFIG_ID_EEPROM
 300 #define CONFIG_SYS_I2C_EEPROM_CCID
 301 #define CONFIG_SYS_ID_EEPROM
 302 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 303 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 304
 305 /*
 306  * General PCI
 307  * Addresses are mapped 1-1.
 308  */
 309 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 310 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 311 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 312 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 313 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 314 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 315 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 316 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 317
 318 #define CONFIG_SYS_PCI2_MEM_VIRT        0xa0000000
 319 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
 320 #define CONFIG_SYS_PCI2_MEM_PHYS        0xa0000000
 321 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 322 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
 323 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 324 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
 325 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 326
 327 #ifdef CONFIG_LEGACY
 328 #define BRIDGE_ID 17
 329 #define VIA_ID 2
 330 #else
 331 #define BRIDGE_ID 28
 332 #define VIA_ID 4
 333 #endif
 334
 335 #if defined(CONFIG_PCI)
 336
 337 #define CONFIG_NET_MULTI
 338 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 339 #define CONFIG_MPC85XX_PCI2
 340
 341 #undef CONFIG_EEPRO100
 342 #undef CONFIG_TULIP
 343
 344 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 345 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 346
 347 #endif  /* CONFIG_PCI */
 348
 349
 350 #if defined(CONFIG_TSEC_ENET)
 351
 352 #ifndef CONFIG_NET_MULTI
 353 #define CONFIG_NET_MULTI        1
 354 #endif
 355
 356 #define CONFIG_MII              1       /* MII PHY management */
 357 #define CONFIG_TSEC1    1
 358 #define CONFIG_TSEC1_NAME       "TSEC0"
 359 #define CONFIG_TSEC2    1
 360 #define CONFIG_TSEC2_NAME       "TSEC1"
 361 #define TSEC1_PHY_ADDR          0
 362 #define TSEC2_PHY_ADDR          1
 363 #define TSEC1_PHYIDX            0
 364 #define TSEC2_PHYIDX            0
 365 #define TSEC1_FLAGS             TSEC_GIGABIT
 366 #define TSEC2_FLAGS             TSEC_GIGABIT
 367
 368 /* Options are: TSEC[0-1] */
 369 #define CONFIG_ETHPRIME         "TSEC0"
 370
 371 #endif  /* CONFIG_TSEC_ENET */
 372
 373 /*
 374  * Environment
 375  */
 376 #define CONFIG_ENV_IS_IN_FLASH  1
 377 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 378 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 379 #define CONFIG_ENV_SIZE         0x2000
 380
 381 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 382 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 383
 384 /*
 385  * BOOTP options
 386  */
 387 #define CONFIG_BOOTP_BOOTFILESIZE
 388 #define CONFIG_BOOTP_BOOTPATH
 389 #define CONFIG_BOOTP_GATEWAY
 390 #define CONFIG_BOOTP_HOSTNAME
 391
 392
 393 /*
 394  * Command line configuration.
 395  */
 396 #include <config_cmd_default.h>
 397
 398 #define CONFIG_CMD_PING
 399 #define CONFIG_CMD_I2C
 400 #define CONFIG_CMD_MII
 401 #define CONFIG_CMD_ELF
 402 #define CONFIG_CMD_IRQ
 403 #define CONFIG_CMD_SETEXPR
 404
 405 #if defined(CONFIG_PCI)
 406     #define CONFIG_CMD_PCI
 407 #endif
 408
 409
 410 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 411
 412 /*
 413  * Miscellaneous configurable options
 414  */
 415 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 416 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 417 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 418 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 419 #if defined(CONFIG_CMD_KGDB)
 420 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 421 #else
 422 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 423 #endif
 424 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 425 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 426 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 427 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 428
 429 /*
 430  * For booting Linux, the board info and command line data
 431  * have to be in the first 16 MB of memory, since this is
 432  * the maximum mapped by the Linux kernel during initialization.
 433  */
 434 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 435
 436 /*
 437  * Internal Definitions
 438  *
 439  * Boot Flags
 440  */
 441 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 442 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 443
 444 #if defined(CONFIG_CMD_KGDB)
 445 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 446 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 447 #endif
 448
 449 /*
 450  * Environment Configuration
 451  */
 452
 453 /* The mac addresses for all ethernet interface */
 454 #if defined(CONFIG_TSEC_ENET)
 455 #define CONFIG_HAS_ETH0
 456 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 457 #define CONFIG_HAS_ETH1
 458 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 459 #define CONFIG_HAS_ETH2
 460 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 461 #endif
 462
 463 #define CONFIG_IPADDR    192.168.1.253
 464
 465 #define CONFIG_HOSTNAME  unknown
 466 #define CONFIG_ROOTPATH  /nfsroot
 467 #define CONFIG_BOOTFILE  your.uImage
 468
 469 #define CONFIG_SERVERIP  192.168.1.1
 470 #define CONFIG_GATEWAYIP 192.168.1.1
 471 #define CONFIG_NETMASK   255.255.255.0
 472
 473 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 474
 475 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 476 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 477
 478 #define CONFIG_BAUDRATE 115200
 479
 480 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 481    "netdev=eth0\0"                                                      \
 482    "consoledev=ttyS1\0"                                                 \
 483    "ramdiskaddr=600000\0"                                               \
 484    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 485    "fdtaddr=400000\0"                                                   \
 486    "fdtfile=your.fdt.dtb\0"
 487
 488 #define CONFIG_NFSBOOTCOMMAND                                           \
 489    "setenv bootargs root=/dev/nfs rw "                                  \
 490       "nfsroot=$serverip:$rootpath "                                    \
 491       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 492       "console=$consoledev,$baudrate $othbootargs;"                     \
 493    "tftp $loadaddr $bootfile;"                                          \
 494    "tftp $fdtaddr $fdtfile;"                                            \
 495    "bootm $loadaddr - $fdtaddr"
 496
 497 #define CONFIG_RAMBOOTCOMMAND \
 498    "setenv bootargs root=/dev/ram rw "                                  \
 499       "console=$consoledev,$baudrate $othbootargs;"                     \
 500    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 501    "tftp $loadaddr $bootfile;"                                          \
 502    "bootm $loadaddr $ramdiskaddr"
 503
 504 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 505
 506 #endif  /* __CONFIG_H */